Chap9. BIST 1

Built-In Self-Test

Chap9. BIST 2

Built-in Self Test (BIST)

• Basics• Test Pattern Generators• Response Analyzers• BIST Examples• BIST of PLAs

BIST

Chap9. BIST 3

BIST - General Organization

Test Generator

Circuit Under Test(CUT)

Response Compressor

BIST Basics

Chap9. BIST 4

BIST - Goal

• Reduce input/output pin signal traffic.• Permit easy circuit initialization and observation.• Eliminate as much test pattern generation as possible.• Achieve fair fault coverages on general class of failure

mode.• Reduce test time.• Execute at-speed testing.• Test circuit during burn-in.

BIST Basics

Chap9. BIST 5

BIST Issues

• Area overhead• Performance degradation• Fault coverage• Ease of Implementation• Capability for system test• Diagnosis capability

BIST Basics

Chap9. BIST 6

BIST Techniques

• Stored Vector Based– Microinstruction support– Stored in ROM

• Algorithmic Hardware Test Pattern Generators– Counter– Linear Feedback Shift Register– Cellura Automata

BIST Basics - LFSR

Chap9. BIST 7

Linear Feedback Shift Register

D1 D2 D3 D4

+

Type 1

D1 D2 D4+

Type 2

• Unit delay - D Flip flop• Modulo 2 adder - XOR gate• Modulo 2 multiplier -connection

BIST Basics - LFSR

D3

Chap9. BIST 8

LFSR - Why?

• Simple and Regular Structure• Compatible with scan DFT design• Capable of exhaustive and/or pseudo exhaustive testin

g• Low aliasing probability

BIST Basics - LFSR

Chap9. BIST 9

LFSR - Recurrence Relation

• Generating Function

• Characteristic polynomial

G x a xmm

m( )

0

g x g xii

i

n( )

0

...

DnDn-1D2 D3D1

gn-1

+

g2

+

g1

+

...

Is a-1 a-2 a-3 ... a-n+1 a-n

Cs am-1 am-2 am-3 ... am-n+1 am-n

BIST Basics - LFSR

Chap9. BIST 10

LFSR - Recurrence Relation (continue)

G(x)

BIST Basics - LFSR

m=0= am xm

= gi am-i xm = gi xi am-i xm-i

= gi xi [a-i x -i +...+ a-1 x -1 + am xm]

= gi xi [a-i x -i +...+ a-1 x -1 + G(x)]

m=0

i =1

n

i =1

n

m=0

i =1

n

m=0

i =1

n

am = gi am-i i =1

n

Chap9. BIST 11

LFSR - Recurrence Relation (continue)

G x g x G x g x a x a x

G xg x a x a x

g x

G xg x a x a x

g x

a a a

i

i

i

n

i

i

i

i

i

n

i

i

i

i

i

n

i

i

i

n

i

i

i

i

i

n

( ) ( )

( )

( )( )

11

1

1

11

1

1

11

1

1 2

1

if n n1 0 1 1 and a G x

g x( )

( )

BIST Basics - LFSR

G(x) is function of initial state and g(x)

Chap9. BIST 12

LFSR Example

D4D3D2D1

g x x x( ) 4 1 1

a n 1 1 0 0 00 0 0 10 0 1 10 1 1 11 1 1 11 1 1 01 1 0 11 0 1 00 1 0 11 0 1 10 1 1 01 1 0 01 0 0 10 0 1 00 1 0 01 0 0 0

D4 D2D1D3

BIST Basics - LFSR

+

Chap9. BIST 13

LFSR - Definitions

• If the sequence generated by an n-stage LFSR has period 2n-1, then it is called a maximum-length sequence.

• The characteristic polynomial associated with maximum-length sequence is called a primitive polynomial.

• An irreducible polynomial is one that cannot be factored; i.e., it is not divisible by any other polynomial other than 1 and itself.

BIST Basics - LFSR

Chap9. BIST 14

LFSR - Theories

• If the initial state of an LFSR is a-1=a-2=...=a1-n=0, a-n=1, then the LFSR sequence {am} is periodic with a period that is the smallest integer k for which P(x) divides (1+xk)

• An irreducible polynomial P(x) satisfies the following two conditions is a primitive polynomial:– It has an odd number of terms including the 1 term.– If its degree n is greater than 3, then P(x) must divide 1+xk, wh

ere k=2n-1

BIST Basics - LFSR

Chap9. BIST 15

LFSR - Properties

• The number of 1s in an m-sequence differs from the number of 0s by one.

• An m-sequence produces an equal number of runs of 1s and 0s.

• In every m-sequence, one half the runs have length 1, one fourth have length 2, one eighth have length 3, and so forth, as long as the fractions result in integral numbers of runs.

BIST Basics - LFSR

Chap9. BIST 16

LFSR - Properties (continue)

• M-sequences generated by LFSRs are called pseudo random sequence.

• The autocorrelation of any output bit is very close to zero.• The correlation of any two output bits is very close to zero

.

BIST Basics - LFSR

Chap9. BIST 17

LFSR - Polynomial Multiplication

D1+

g1

D2+

gn-2

Dn-1+

gn-1

Dn+

gn g0

...

inputf(x)

outputh(x) g x g x g x g x

Input f x

Output h x

h x g x f x

nn

nn( )

( )

( )

( ) ( ) ( )

11

00

BIST Basics - LFSR

Chap9. BIST 18

LFSR - Polynomial Multiplication

D1D2D3+D4+

g x x x( ) 4 3 1

10113 2x x

Output stream D4 D3 D2 D1 Input stream 0 0 0 0 1 1 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 1 x7 x5 x4 x2 1

x x x x x x x x4 3 3 2 7 5 4 21 1 1

BIST Basics - LFSR

Chap9. BIST 19

LFSR - Polynomial Division

g x g x g x g x

M x

Q x

R x

M x P x g x R x

nn

nn( )

( )

( )

( )

( ) ( ) ( ) ( )

11

00

Input

Output

Remainder

D1+

g1

+

gn-2

+

gn-1 gng0

...input output

+ D2 Dn-1 Dn

BIST Basics - LFSR

Chap9. BIST 20

LFSR - Polynomial Division (example)

Input011011011

Output 11001

M(x)

Q(x)g x x x( ) 4 3 1

D1 D2 D3 + D4+

M(x) D3 D2 D1 D0 Q(x) 0 1 1 0 1 1 0 1 1 0 0 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 0 0 1

after 4 shifts

BIST Basics - LFSR

x+x2+x4+x5+x7+x8 1+x+x4

1 +x +x41 +x2+x3

(x8+x7+x5+x4+x2+x) (x4+x3+1) = x4+x+1 R(x) = x3+x2+1

Chap9. BIST 21

LFSR - Summary

• LFSRs have two types.• LFSRs can implement polynomial division and multiplic

ation in GF(2).• As polynomial multipliers, LFSRs are capable of genera

ting random vector.• As polynomial divisors, LFSRs are capable of compress

ing test responses.

BIST Basics - LFSR

Chap9. BIST 22

Cellura Automata (CA)

• A One-Dimensional Array of Cells.• Each cell contains a storage device and next state logic.• Next state is a function of current state of the cell and its

neighboring cells.

Three-Cell Neighbor -- von Newmann Neighborhood

DQ

NextState

DQ

DQ

NextState

NextState

BIST Basics - CA

Chap9. BIST 23

Cellura Automata - Name

• Name of CA Functions is determined by its truth table.

BIST Basics - CA

State A0 A1 A2 A3 A4 A5 A6 A7 Ci+1

Ci

Ci-1

Next State KMap FCA

A0 A2

A1 A3 A5

A4 A6

A7

Name Aii

i

0

7

2

Example: F C CCA i i 1 Name = 64+32+4+2 = 102

0 1 0 1

(defined by Wolfram)

0 1 0 1

CiCi-1

00 01 11 10Ci+1

01

0 0 0 0 1 1 1 10 0 1 1 0 0 1 10 1 0 1 0 1 0 1

Chap9. BIST 24

Cellura Automata - Hardware

BIST Basics - CA

DQ

Fca

DQ

Fca

DQ

Fca

DQ

Fca

DQ

Fca

DQ

Fca

0 0

CA with Null Boundary Condition

Standard - All the CAs are of the same typeHybrid - The CAs are of different type

Chap9. BIST 25

Cellura Automata - Hardware

BIST Basics - CA

DQ

Fca

DQ

Fca

DQ

Fca

DQ

Fca

DQ

Fca

DQ

Fca

CA with cyclic Boundary Condition

Chap9. BIST 26

BIST - Pattern Generation

PG Hardware

• Stored Patterns• Counter Based• LFSR Based• Cellura Automata

Pattern Generated

• Deterministic• Pseudorandom• Exhaustive• Pseudo exhaustive

BIST - TestGen

Chap9. BIST 27

TG - Stored Pattern

• Functional Chip Tests• Test for structured logic such as ILA• Supplemental test for uncovered faults• Test control for other methods• Architecture support self test command

BIST - TestGen - Stored Pattern

Chap9. BIST 28

Stored Pattern- Supplement for Uncovered faults

• Hard-to-detect faults not covered by random testing

BIST - TestGen - Stored Pattern

hard to detect fault

Chap9. BIST 29

TG - Counter Based

• Generates regular test sequences such as walking sequences and counting sequences for memory and interconnect testing

1 0 0 0 0 0 0 00 1 0 0 0 0 0 00 0 1 0 0 0 0 00 0 0 1 0 0 0 00 0 0 0 1 0 0 00 0 0 0 0 1 0 00 0 0 0 0 0 1 00 0 0 0 0 0 0 1

Walking Sequence0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

Counting Sequence

BIST - TestGen - Counter Based

Chap9. BIST 30

TG - LFSR

• Exhaustive Testing• Pseudoexhaustive Testing• Pseudorandom Testing• Weighted Pseudorandom Testing

BIST - TestGen - LFSR

Chap9. BIST 31

TG - Exhaustive Testing

• Apply all possible input combinations

• A complete functional testing• 100% coverage on all possible f

aults• Testing time and hardware over

head are the major considerations for circuits with large number of inputs.

BIST - TestGen - LFSR

LFSR

CUT

SA

Chap9. BIST 32

BIST - Pseudo-exhaustive Testing (PET)

• Apply all possible input combination to every partitioned subcircuits.

• 100% faults coverage on single faults and multiple faults within the subcircuit.

• Testing time is determined by the number of subcircuits and the number of inputs to the subcircuit.

• Partitioning is a difficult task.

Chap9. BIST 33

TG - PET Hardware Example

Subcircuitunder test

MUX

LFSR

SA

CUT

normal inputs

BIST - TestGen - LFSR

Chap9. BIST 34

BIST - Pseudo Random Testing

• Apply random test sequence generated by LFSR/CA.• Simplest to design and implement• Lowest in hardware overhead• Fault coverage is a function of the test length and the te

stability of the circuits

BIST - TestGen - LFSR

Chap9. BIST 35

BIST - Pseudo Random Testing Hardware

Combinational Sequential

LFSR

Combinationalcircuit

SA

LFSR

Combinationalcircuit

SA

(Circular BIST)

BIST - TestGen - LFSR

(BEST)

Chap9. BIST 36

BIST - Pseudo Random Testing Hardware

Circuit Under Test

Shift registerLFSR

SA

LFSR

SA

SR

SR

SR

CUT CUT

BIST - TestGen - LFSR

(CEBT) (STUMPS)

Chap9. BIST 37

Pseudo Random Test Length

• eth: Escape Threshold

• gmin: the detection probability of the hardest to detect

fault by a random vector

• k: the number of faults with detection probability 2gmin

• Example 1: eth=0.001, gmin=1E-5, k=5 m=851,716

• Example 2: eth=0.001, gmin=1E-5, k=50 m=1,081,973

Test length me k

g

k e

gth th

ln /

ln

ln ln

min min1

BIST - TestGen - LFSR

Chap9. BIST 38

BIST - Weighted Pseudo Random Test

LFSR

1/8 3/4 1/2 7/8 1/2

BIST - TestGen - LFSR

0.8 0.6 0.8 0.4 0.5 0.3 0.3

0

DQ

123

DQ

193

DQ

61

DQ

114

DQ

228

DQ

92

DQ

25

0

LFSR Based Weighted Celluar Automaton

Chap9. BIST 39

BIST - Response Compression

• Introduction• Ones-Count Compression• Transition-Count Compression• Syndrome-Count Compression• Signature Analysis• Space Compression

BIST - ResComp

Chap9. BIST 40

BIST - Response Compression

• Bit-to-bit Comparison is infeasible for BIST.• Compress a very long output sequence into a single sig

nature.• Compare the compressed word with the prestored gold

signature to determine the correctness of the circuit.• Many output sequences may have the same signature

after the compression, the aliasing problem.• Poor diagnosis resolution after compression.

BIST - ResComp

Chap9. BIST 41

Ones-Count - Hardware

• Apply predetermined patterns• Count the number of ones in the output sequence.

TestPattern

CUT

CounterClock

BIST - ResComp

Chap9. BIST 42

Ones Counter - Aliasing

• Aliasing Probability

m: the test lengthr: the number of ones

• r=m/2, the case with the highest aliasing probability• r=m and r=0, no aliasing probability• For combinational circuits, the input sequence can be p

ermuted without changing the count.

P mOC

rm

m

1

2 1

12

BIST - ResComp

Chap9. BIST 43

Transition Count

• Apply predetermined patterns• Count the number of the transitions

(0 1 and 1 0)

TestPattern

CUT

CounterClock

DFF

BIST - ResComp

Chap9. BIST 44

Transition Count

• Aliasing Probability

m: the test lengthr: the number of transitions

• r=m/2, highest aliasing probability. r=0 and r=m , no aliasing probability

• For combinational circuits, the input sequence cannot be permuted.

• One can reorder the test sequence to minimize the aliasing probability.

P mTCrm

m

2 1

2 1

11

2

BIST - ResComp

Chap9. BIST 45

Syndrome Testing

• Apply random patterns.• Count the probability of 1.• The property is similar to that of ones count.

randomtest

patternCUT

Syndrome counter

Counter /

Clock

Syndrome

BIST - ResComp

Chap9. BIST 46

Signature Analysis

• Apply predetermined test patterns.• Divide the Output Sequence by LFSR.

TestPattern

CUT LFSR

BIST - ResComp

Chap9. BIST 47

Signature Analysis• Aliasing Probability

m: test length, n: length of LFSR• Aliasing probability is output independent.• An LFSR with two or more nonzero coefficient detect any single

faults.• An LFSR with primitive polynomial detect any double faults sep

arated less than 2n-1

• An LFSR with g0=1 detects all burst error of length less than n.

PSA

m n

mn

2 1

2 12

BIST - ResComp

Chap9. BIST 48

Multiple Input Signature Register (MISR)

D4 + D3 + D2 + D1 +

type 2

type 1

D4 + D3 + D2 + D1 +

+

BIST - ResComp

Chap9. BIST 49

Space Compression

• Use space compression to handle large output circuits.• Use XOR gates to compress space.• Use Error Control Coding to achieve better fault coverage.• Example: A 16 SEC-DED code compresses 16 outputs into 5.

BIST - ResComp

1 2 3 4 5 6 7 8

+ + + + + +

9 10 11 12 13 14 15 16

+ + + + + +

+ + + ++ + + +

P1 P2 P3 P4 P5

+ + + ++

+

Chap9. BIST 50

BIST - Space and Time Compression

CUT TCSCCUT TC

SC

Space-Time Compression Time-Space Compression

BIST - ResComp

Chap9. BIST 51

BIST Examples

• HP Focus Chip, Functional Chip Test• Built-in Logic Block Observation (BILBO)

[Koenemann 79]• Centralized and Separate Board Level BIST (CSBL) [Benowitz

75]• Built-in Evaluation and Self-Test (BEST) [Resnick 83]• Random-Test Socket (RTS) [Bardell 82]• LSSD On-Chip Self Test (LOCST) [LeBlanc 84]• Self test using MISR and Parallel SRSG (STUMPS) [Bardell 82]

BIST - Example

Chap9. BIST 52

BIST Examples (cont.)

• Concurrent BIST Architecture (CBIST) [Saluja 88]• Centralized and Embedded BIST with Boundary Scan (C

EBS)• Random Test Data (RTD) [Bardell 87]• Simultaneous Self Test (SST) [Gupta 82]• Cyclic Analysis Testing System (CATS) [Burkness 87]• Circular Self-Test Path (CSTP) [Krasniewski 89]

BIST - ResComp

Chap9. BIST 53

BIST - HP Focus Chip (Stored Pattern)

• Chip Summaries– 450,000 NMOS devices, 300,000 Nodes– 24MHz Clocks, 300K bits of on-chip ROM– Used in HP9000-500 computer

• BIST Microprogram– Use microinstructions dedicated for testing– 100K-bit BIST microprogram in CPU ROM– Executes 20 million clock cycles– Greater than 95% stuck-at coverage– A power-up test used in system test, filed test, and wafer test

BIST - Example

Chap9. BIST 54

BIST - BILBO

• Built-in Logic Block Observation [Koenemann 79.80]

0

1

MU

X

Z1

QD

Q

Q1

Z2

D

Q

Q

Q2

...

...

...

QD

Q

Qn-1

Zn

D

Q

Q

Qn

S0

...

Si

B2

B1

C1

BILBO1

BILBO2

C2

BILBO3

C3B1 B2 BILBO0 0 shift register0 1 reset1 0 MISR (inputconstantLFSR)1 1 parallel load (normal operation)

BIST - Example

Chap9. BIST 55

BIST - CSBL

• Centralized and Separate Board-Level BIST [Benowitz 75]

• Use only one Signature Register• Tests repeat m times to reduce hardware cost

CUT(C or S)M

UX

MUX SISRCounterPRPG

n

k1

mn

m

1

PIs

POs

k m log2

BIST - Example

Chap9. BIST 56

BIST - BEST

• Built - Evaluation and Self Test [Resnick 83]

• Pseudo random testing• Hardware overhead is low• Test length can be long for CUT with random-pattern re

sistant faults.

PR

PG

CUT(C or S)

MIS

RPI PO

BIST - Example

Chap9. BIST 57

• Random-Test socket [Bar dell 82]

• Combine LSSD Scan Chain and BIST• Can insert test points to reduce test length for random-p

attern resistant faults

BIST - RTS

CUT (S)

Sin SoutClocks Controls

PR

PG

MIS

R

SR

SG

R1 R3

R2 SIS

R

R4

BIST controller

BIST - Example

Chap9. BIST 58

BIST - LOCST

• LSSD On-Chip Self-Test [LeBlanc 84]

• Boundary scan is required to unify the test architecture• Single scan chain may cause high test time overhead.

CUT(S)

Si S0

SRSG

PIs

SRL

R1

SISR

POs

SRL

R2

On-chipmonitor(OCM) Error-detection circuitry

Sin

Sin

Error signalControl signals

BIST - Example

Chap9. BIST 59

BIST - STUMPS

• Self-Test using MISR and Parallel SRSG [Bardell 82,84]

• Multiple scan chain to reduce test time

...

PIs

...

POs

PR

PG

PR

PG

Scan path

Scan path

Scan path

. . .

CUT (S)

So So*External logic

External logic

BIST - Example

Chap9. BIST 60

BIST - CBIST

• Concurrent Built-in Self Test [Saluja 88]

• Detect test patterns from normal inputs sequence

• Once a pattern is detected, compress the response and tick the test clock.

• If waited too long, insert a test pattern from PRPG.

Comparator

PRPG

MUX N / T

N / T

Normal inputs

CUT(C)

MISR

Normal outputs

EN

CBIST Circuitry

BIST - Example

Chap9. BIST 61

BIST - CEBS• Centralized and Embedded BIST architecture

with Boundary Scan [Komanytsky 82.83]

• A low cost version of RTS or LOCST

CUT (S)Si

So

Boundary-scan registerInput. . .. . .

. . .. . .Boundary-scan registerOutput

PIs

POs

RPG (PRPG/SRSG)

SR (MISR/SISR)

Sin

Sout

BIST - Example

Chap9. BIST 62

BIST - RTD

• Random Test Data [Bazdell 87]

• Use MISR to replace internal storage devices for test generation and response comparison

C

MISR

. . .

PR

PG

...M

ISR

Sin Sout

PIs POs

R1 R3

R2

CUT

...BIST - Example

Chap9. BIST 63

BIST - SST

• Simultaneous Self Test [Gupta 82]

• Similar to MISR but without LFSR part

POCUTCombinational

PI

BIST - Example

Chap9. BIST 64

BIST - CATS• Cyclic Analysis Test System [Burkness 87]

• If more outputs than inputs, space compression is needed.• If less outputs than inputs, an output drive multiple inputs.• A synchronous feedback loops can be created, therefore may create r

aces.

BIST - Example

x1

S

x1

xn

. . .

. . .

z1

zn

Sxn

. . .

. . .

z1

zn

... MU

X...

N / TOriginal Circuit BIST Circuit

Chap9. BIST 65

BIST - CSTP

• Circular Self Test Path [Krasniewski 89]

• Similar to SST except that boundaries are scanned

• Not all registers are self-test path registers.

R1

R6

C1

C6

R5

C5

R7

R3

C3

R2

R4

C2

C4

R8

R

R

- conventional register

- self-test path register

POs PIs

Key

C

. . .

. . .

z1 z2 zm

x1 x2 xm

BIST - Example

Chap9. BIST 66

BIST - PLA General Structure

BIST - PLA

AND Plane

First NOR Plane

Input Decoders

. . .

. . .PLA Inputs

OR Plane

Second NOR Plane

Output Buffers

. . .

. . .PLA Outputs

.

.product

lines..

Chap9. BIST 67

BIST - PLA Circuit Structure

BIST - PLA

x1 x2 x3 z1 z2

p1

p2

p3

Vdd

InputDecoders Output

Buffer

Vdd

Chap9. BIST 68

BIST PLA - Fault Model

• Stuck-at faults (A)• Bridging faults (B)• Cross Point faults

– Missing Device fault (C)– Extra Device faults (D)

BIST - PLA

AAND OR

B

C

D

Chap9. BIST 69

BIST PLA - Cross Point faults

• Growth - The missing device in AND plane causes an input variable to disappear from a product term.

• Shrink - The extra device in AND plane causes an input variable to appear in a implicant.

• Disappearance - The missing device in OR plane causes an implicant to disappear from a function.

• Appearance - The extra device in OR plane causes an implicant to appear in a function.

BIST - PLA

Chap9. BIST 70

PLA Testing• Test generation is difficult for large PLAs

- Pseudorandom resistance due to large fan-ins• Easily testable designs - Add moderate hardware overhead to make pattern generation e

asier

- The general idea is to make each product line controllable and observable

• Built-In Self Test - A varieties of technique were proposed - The effectiveness is evaluated by

• Hardware overhead• Test length• Delay per test application

Chap9. BIST 71

The HJA Scheme

• Proposed by Hua, Jou and Abraham

• Solve pitch mismatch problem by using multiplexing in the Augmented Decoder

• Hardware Overhead: fair

- AD, TPG, PC2 and PC3

• Test length: good

- 2M+P+2

• Delay per test application: fair

-Limited by the parity checkers

Chap9. BIST 72

The HJA Scheme (continue)

E3E1

C2 C1 Inputs Feedback Lines

Output Cells

PC3

TPG

Interface Cells OR ArrayAND Array

E2

PC2

Outputs

TPG: Test Pattern GeneratorAD: Augmented DecoderPC: Parity Checkers

AD

Chap9. BIST 73

TFA Scheme

• Proposed by Treuer, Fujiwara and Agarwal

• Hardware overhead: good

- AD, PS, PC3

• Test length: fair

- 2MP + 2M + 1

• Delay per test application: fair

- Limited by the parity checker

Chap9. BIST 74

TFA Scheme (continue)

E3

C2 C1 Inputs Feedback Lines

Output Cells

PC3

Interface Cells OR ArrayAND Array

Outputs

ADSin

PS: Product Line Selector

PS

Chap9. BIST 75

HM Scheme

• Proposed by Hassan and McCluskey

• Hardware overhead: bad

- A M-bit LFSR generates exhaustive patterns

- Three LFSRs compress the results

• Test length: bad

- Bad for PLAs with large number of inputs

• Delay per test application: good

- Use signature analyzer instead of parity checkers

Chap9. BIST 76

HM Scheme (continue)

L

L

AND Array

G

OR Array

LS

InputsOutput

G: Maximum Length Sequence GeneratorL: Parallel LFSRLS: LFSR(s) Used to Compact the Outputs

Complemented Bit Lines

True Bit Lines

Chap9. BIST 77

DM Scheme

• Proposed by Daehn and Mucha

• Using nonlinear feedback shift registers for both pattern generation and response compression

• Hardware overhead: bad

- Three slightly modified BILBOs

• Test length: good

- 2M + P + Q + 1

• Delay per test application: good

Chap9. BIST 78

DM Scheme (continue)

BIST - PLA

AND Plane

BILB

O1

Input Decoders

OR Plane

BILB

O3

Input Decoders

BILBO2

Chap9. BIST 79

The New BIST Design

• Hardware overhead: good

- AD, PS and MISR

• Test length: fair

- 2MP

• Delay per test application: good

- No parity checkers

Chap9. BIST 80

The New BIST Design (continue)

C1

C1Inputs

Feedback Lines

Interface Cells OR ArrayAND Array

Outputs

AD: Augmented DecoderPS: Product Line SelectorMISR: Multiple Input Signature RegisterG(X): Characteristic Polynomial

AD

PS

SinMISR

G(X) = XQ+1 SoutC2

E2E1

Chap9. BIST 81

The New BIST Design

• Use AD and PS to evaluate each device in the AND array

• Use MISR with XQ + 1 as the characteristic polynomial

- Hardware complexity is comparable to that of the parity checker

• Add one extra input

- Make the product lines of the AND array all have an odd number of devices and an odd number of nondevices

• Add one or two product lines

- Make the bit lines of the AND array all have an odd number of devices

- Make the output lines all have an odd number of devices

- Make the PLA have an odd number of product lines

Chap9. BIST 82

Fault Coverage

• MISR with XQ + 1Si(x) = 1 + x + x2 + x4 = 11101Ri(x) = x + x2 = 01100

1 1 1 1 1

0 0 01 1

Si+1(x) = 1 + x3 = 10010

• In order to guarantee the detection of all modeled faults, the E(X) caused by some fault must satisfy the requirement of

E(X) mod XQ + 1 0

Chap9. BIST 83

Fault Coverage

• Theorem 1: E(X) mod XQ + 1 0 if E(X) has an odd number of terms

• Theorem 2: All the single contact faults and stuck at faults cause E(X) to have an odd number of terms in the BIST design

• Theorem 3: R(X) mod XQ +1 has an odd number of terms if R(X) has an odd number of terms

• Corollary 1: F(X) mod XQ + 1 has an even number of terms if F(X) has an even number of terms

• Parity of fault-free signature is 1

Chap9. BIST 84

Fault Coverage

• Parity of faulty signature is 0

• Short faults between two adjacent bit lines are detected by NOR gate E1

• Short faults between two adjacent product lines are detected by the NOR gate E2 combined with a parity counter

• Short faults between two adjacent output are not 100% detectable

Chap9. BIST 85

Conclusion

• Deterministic test pattern generation is used to generate the efficient test patterns

• The simplest MISR is used to compress the results into only ONE bit

• The final signature can be further compressed into only ONE bit

• All the single stuck-at faults and contact faults are detected

• The design gives a better trade-off between the cost and the performance of BIST PLAs