Behavioral Modeling

*Modeling BehaviorArchitecture bodydescribes an implementation of an entitymay be several per entityBehavioral architecturedescribes the algorithm performed by the module

architecture rtl of ex is concurrent declaration part begin concurrent VHDL process (...) sequential declaration part begin sequential VHDL end process; concurrent VHDL end;

Concurrent VHDL constructionsProcess statementWhen else statementWith select statementSignal declarationBlock statement

Assignments are executed sequentially inside processes.

Sequential VHDL constructionsIf-then-else statementCase statementVariable statementVariable assignmentLoop statementReturn statementNull statementWait statement

Process StatementThe process statement is a concurrent statement that defines a specific behavior to be executed when the process becomes active. The behavior of the process is described with a set of sequential statements.It is characterized by the presence of IF, WAIT, CASE, or LOOP, and by a sensitivity list (except when WAIT is used).VARIABLES are optional.General Form is :[label:] PROCESS (sensitivity list)[VARIABLE name type [range] [:= initial_value;]]BEGIN(sequential code)END PROCESS [label];

A simple Example

entity Xor_gate is port (in1, in2 : in bit; Out1 : out bit);end Xor_gate ;architecture behavioral of Xor_gate isbeginprocess (In1, in2)beginOut1

architecture Behavioral_Desc of Adder isbegin process (A, B)begin Sum

Process StatementIf there are several processes in an architecture, they are executed concurrently.A process is either active or suspended.A process becomes active when any of the signal read by the process changes its value.All active processes are executed concurrentlyA process may be suspended upon execution of a wait statement in the process. The process remains suspended until its reactivation condition is met.

half subtractor

entity h_subtractor is port( a : in STD_LOGIC; b : in STD_LOGIC; difference : out STD_LOGIC; borrow : out STD_LOGIC );end h_subtractor;

architecture rtl of h_subtractor isbegin process(a,b)begin

difference

Conditional ControlThese sequential statements provide conditional control i.e statements are executed when a given condition is true

VHDL provides two types of conditional control statementsif then elsifcase end case

If StatementGeneral form isif condition thenstatementelsif condition thenstatementelsestatementend if;

Case StatementGeneral Form iscase expression iswhen value =>statementswhen value | value =>statementswhen discrete_range =>statementswhen others =>statementsend case;

MUX 4*1

entity mux_case is port( a,b,c,d : in STD_LOGIC; sel :in STD_LOGIC_vector (0 to 1); z : out STD_LOGIC );end mux_case;

architecture rtl of mux_case isbeginProcess (sel,a,b,c,d) begin case sel iswhen "00" => z z z z

entity mux4_1 is port( a,b,c,d : in STD_LOGIC; sel : in STD_LOGIC_vector(0 to 1); z : out STD_LOGIC );end mux4_1;

architecture rtl of mux4_1 isbeginprocess (sel) beginif sel= '0' & '0' thenz

entity jk_ff is port( j, k, clk : in STD_LOGIC; q : inout STD_LOGIC );end jk_ff;

architecture rtl of jk_ff is beginprocess (j, k, clk)begin if clk = '1' then if j ='0' and k = '0' thenq

entity jk_ff is port( j, k, clk : in STD_LOGIC; q : inout STD_LOGIC );end jk_ff;

architecture rtl of jk_ff is signal input: std_logic_vector(1 downto 0); begin process (clk)begin if clk = '1' then case input iswhen "00" => q q q q null;end case;end if; input

Architecture Declaration

*/26entity fulladder_bh is port ( A, B, Cin : in bit; Sum, Cout : out bit);end fulladder_bh;

architecture behavioral of fulladder_bh isbegin process (A , B, Cin) begin if ( A = 0 and B = 0 and Cin = 0) then Sum

Example

The following process implements a simple OR gate----- this process is sensitive to signals In1 and In2

Or_process : process (In1, In2)beginOutput

Wait StatementThree kind of reactivation condition can be specified in a wait statementtimeout wait for time-expression;condition wait until Boolean-expression;signal sensitivity wait on signal-list;

Conditions can be mixed. - wait on A, B until Enable = 1;If a process is always sensitive to one set of signals, it is possible to designate sensitivity signals using a sensitivity list. It is illegal to use wait statement in a process with a sensitivity list.Every process is executed once upon initialization.

Some examples of wait statements are

wait on A, B, C; -- statement 1 wait until (A = B); -- statement 2 wait for 10ns; -- statement 3 wait on CLOCK for 20ns; -- statement 4 wait until (SUM > 100) for 50 ms; -- statement 5

Details of the waits typesWait until a=1; means that, for the wait condition to be satisfied and execution of the code to continue, it is necessary for signal a to have an event, i.e. change value, and the new value to be 1, i.e. a rising edge for signal a.Wait on a,b; is satisfied when either signal a or b has an event (changes value).Wait for 10 ns; means that the simulator will wait for 10 ns before continuing execution of the process.The starting time point of the waiting is important and not the actual changes of any signal value.It is also permissible to use the wait for command as follows: constant period:time:=10 ns; wait for 2*period;The wait alternatives can be combined into: wait on a until b=1 for 10 ns;, but the process sensitivity list must never be combined with the wait alternativesExample: wait until a=1 for 10 ns; The wait condition is satisfied when a changes value or after a wait of 10 ns (regarded as an or condition).

Examples of wait statementExample 1process (a)begin c1