Colour Television ChassisMP1.1U
Published by JH 567 TV Service
©Copyright 2005 Philips Consumer EAll rights reserved. No part of this puretrieval system or transmitted, in anymechanical, photocopying, or otherw
AA
Contents Page
1 Specification 22 Precautions and Notices 133 Operation 144 Trouble shooting chart 205 White-Balance Adjustment 256 DDC program and test 267 Flash Update 288 Software Platform Reference TV Application 319 Block diagram & Explain 3310 Waveform of Signal 3711 Check and Measure 4412 Mechanical of Cabinet 4713 PCB Layout 6214 Circuit Diagrams 6515 Spare Parts List 32MF130A/37 8816 Spare Parts List 32MF230A/37 8817 Revision List 89
Printed in the Netherlands Subject to modification EN 3122 785 15691
lectronics B.V. Eindhoven, The Netherlands.blication may be reproduced, stored in a form or by any means, electronic,
ise without the prior permission of Philips.
1、 SPECIFICATION 42MF130A/37 1-1 General Specification
NOTE: *This model complies with the specifications listed below. *Designs and specifications are subject to change without notice. *This model may not be compatible with features and/or specifications that may be added in the future.
Item Specification
Screen size 107cm(42 inch) plasma display panel Aspect 16:9 Display pixels 852(H) x 480 (V) Viewing Angle 160° Number of color 1670 million colors Contrast Ration 3000:1 (in dark room)
Panel Spec
Peak brightness(with filter) 400 cd/m2
Y 1V(p-p), 75 ohm Pr/Cr 0.7 V (p-p), 75 ohm Pb/Cb 0.7 V (p-p), 75 ohm
Component INPUT
Rear(2 Group)
AUDIO 150 mV (rms)
Suggested resolutions: 1080i, 480p, 480i, 720p
DVI INPUT Rear(1 Group) DVI-D HDCP compliant E-EDID compliant
Suggested scan rates: 1080i/60Hz, 1080p/60Hz, 720p/60Hz
VGA INPUT Rear(1 Group) D-SUB 15Pin E-EDID compliant Suggested scan rates:
640 x 480/60Hz, 800 x 600/60Hz, 1024 x 768/60Hz
S-Video Y : 1 V(p-p), 75 ohm, negative sync. C : 0.286 V(p-p) (burst signal), 75 ohm
Video 1 V(p-p), 75 ohm, negative sync. Video INPUT Side(1 Group) Rear(1 Group)
Audio 150 mV(rms) VIDEO 1 V(p-p), 75 ohm, negative sync
Video Output Rear(1 Group) AUDIO 150 mV(rms)
Television System
NTSC standard ATSC standard (8VSB)
Channel Coverage: VHF: 2 through 13 UHF: 14 through 69 Cable TV: Mid band (A-8 through A-1, A through I) Super band (J through W) Hyper band (AA through ZZ, AAA, BBB) Ultra band (65 through 94, 100 through 125)
Audio Power Internal Speaker 5 W + 5 W Power input sources 100 -240V, 50/60 Hz
Power Power consumption
350 W (on average) / 1W in standby mode (power cord plugged in and power OFF)
Dimension Width x Height x Depth Without Stand: 1038 x 660 x 82 (mm) Include Stand: 1038 x 726.5 x 270 (mm)
Without Stand 35.5 kg Net weight
With Stand 43 kg Accessory 1pcs power cord, 1pcs remote control, (with two *AAA*sized alkaline batteries)
Choose Part Wall Mounting Bracket
NOTE: This TV does not provide ATSC TV/S-VIDEO/HD/VGA/DVI Output. 2
1、 SPECIFICATION 42MF230A/37 1-1 General Specification
NOTE: *This model complies with the specifications listed below. *Designs and specifications are subject to change without notice. *This model may not be compatible with features and/or specifications that may be added in the future.
Item Specification
Screen size 107cm(42 inch) plasma display panel Aspect 16:9 Display pixels 1024(H) x 768 (V) Viewing Angle 160° Number of color 1670 million colors Contrast Ration 3000:1 (in dark room)
Panel Spec
Max. brightness 1000 cd/m2 Y 1V(p-p), 75 ohm Pr/Cr 0.7 V (p-p), 75 ohm Pb/Cb 0.7 V (p-p), 75 ohm
Component INPUT
Rear(2 Group)
AUDIO 150 mV (rms)
Suggested resolutions: 1080i, 480p, 480i, 720p
DVI INPUT Rear(1 Group) DVI-D HDCP compliant E-EDID compliant
Suggested scan rates: 1080i/60Hz, 480p/60Hz, 720p/60Hz
VGA INPUT Rear(1 Group) D-SUB 15PinE-EDID compliant Suggested scan rates:
640 x 480/60Hz, 800 x 600/60Hz, 1024 x 768/60Hz
S-Video Y : 1 V(p-p), 75 ohm, negative sync. C : 0.286 V(p-p) (burst signal), 75 ohm
Video 1 V(p-p), 75 ohm, negative sync. Video INPUT Side(1 Group) Rear(1 Group)
Audio 150 mV(rms) VIDEO 1 V(p-p), 75 ohm, negative sync
Video Output Rear(1 Group) AUDIO 150 mV(rms)
Television System
NTSC standard ATSC standard (8VSB)
Channel Coverage: VHF: 2 through 13 UHF: 14 through 69 Cable TV: Mid band (A-8 through A-1, A through I) Super band (J through W) Hyper band (AA through ZZ, AAA, BBB) Ultra band (65 through 94, 100 through 125)
Audio Power Internal Speaker 5 W + 5 W Power input sources 100 -240V, 50/60 Hz
Power Power consumption
450 W (on average) / 1W in standby mode (power cord plugged in and power OFF)
Dimension Width x Height x Depth Without Stand: 1038 x 660 x 82 (mm) Include Stand: 1038 x 726.5 x 270 (mm)
Without Stand 35.5 kg Net weight
With Stand 43 kg Accessory 1pcs power cord, 1pcs remote control, (with two *AAA*sized alkaline batteries)
Choose Part Wall Mounting Bracket
NOTE: This TV does not provide ATSC TV/S-VIDEO/HD/VGA/DVI Output. 3
1-2 Feature Summary 42MF130A/37
The following is the specification summary for the display:
107 cm (42”) 16:9 PLASMA DISPLAY PANEL
Resolutions: 852 (H) X 480 (V) pixels, (1 pixel = 1 R, G, B cells)
1.095 mm (H) X 1.110mm(V) pixel pitch.
Viewing Angle: 160° Vertically and Horizontally
Typical Maximum Contrast Ratio: 3000:1
Typical Maximum Brightness (with filter): 400 cd/m2
ATSC receiver, MPEG-2 decoder
NTSC receiver, Video decoder
Closed Caption / V-chip
Composite, S-Video, and component video receiver
DVI digital video interface
D-SUB analog video with rate 50Hz to 85 Hz vertical refresh rate and 31KHz to
80KHz horizontal frequency
MIPS controller
Field upgradeable firmware
Universal Power Supply designed for worldwide application
Operating power consumption less than 350 W
Standby power consumption less than 1 W
UL, FCC, certification
Dimension: width – 1038mm, height – 660mm, depth – 82mm, weight – 35 Kg
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1-2 Feature Summary 42MF230A/37
The following is the specification summary for the display:
107 cm (42”) 16:9 PLASMA DISPLAY PANEL
Resolutions: 1024 (H) X 768(V) pixels, (1 pixel = 1 R, G, B cells)
0.912 mm (H) X 0.693mm(V) pixel pitch.
Viewing Angle: 160° Vertically and Horizontally
Typical Maximum Contrast Ratio: 3000:1
Typical Maximum Brightness: 1000 cd/m2
ATSC receiver, MPEG-2 decoder
NTSC receiver, Video decoder
Closed Caption / V-chip
Composite, S-Video, and component video receiver
DVI digital video interface
D-SUB analog video with rate 50Hz to 85 Hz vertical refresh rate and 31KHz to
80KHz horizontal frequency
MIPS controller
Field upgradable firmware
Universal Power Supply designed for worldwide application
Operating power consumption less than 450 W
Standby power consumption less than 1 W
UL, FCC, certification
Main Dimension: width 1038mm, height 640mm, depth 110mm, weight 43 Kg
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1-3 External interface Most of these interfaces are located at the back-panel. There’s also a group of connectors located on the side of this device for easier access. The following figures depict these A/V connectors.
Side A/V Connectors
S-Video Video L R Earphone
AV2 Input
Back Panel A/V Connectors
S-Video Video R L
AV1 Input
AV Output Video R L
Y Pb/Cb Pr/Cr R L
AV4 Component Input
AV3 Component Input Y Pb/Cb Pr/Cr R L
VGA L/ R
PC Input DVI L/ R
DVI Input ANT
ATSC/NTSC
RS-232
1-3-1 Video/Audio Inputs The following sections specify the video/audio inputs for 42MFx30A/37
1-3-1-1 TV Antenna Interface ①. TV Antenna Connector
42MFx30A/37 shall provide a F-type cable connector with 75 ohms termination on its back panel for reception of radio frequency signals.
②. TV Systems 42MFx30A/37 shall be capable of receiving the following broadcasting systems in the North America region.
• Analog terrestrial and cable broadcasting in NTSC system and “M” sound system.
• All 18 formats specified for ATSC digital broadcasting
• Clear QAM digital cable broadcasting
③. TV Channel Coverage The RF tuner shall be capable of covering 55.25 to 859.25 MHz and tuning to the following
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channels: • VHF: channel 2 through 13
• UHF: channel 14 through 69
• Mid band cable: A1 through A8, A through I
• Super band cable: J through W
• Hyper band cable: AA through ZZ, AAA, BBB
• Ultra band cable: channel 65 through 94, 100 through 125
④. Closed Caption 42MFx30A/37 shall support closed caption and text mode for both video and TV system. These supports shall include channel ½ and field ½ selectable features.
⑤. V-Chip 42MFx30A/37 shall support MPAA grade for movie and TV Parental Guideline for TV. This support shall include changeable password.
1-3-1-2 AV1 A standard definition (SD) analog video/audio source designated as AV1 shall be located on its back panel. It comprises the following electrical connections. Only one of the two video inputs shall be connected.
①. S-Video Input 42MFx30A/37 shall provide a 4-pin mini-DIN connector for connection to an external S-Video source.
②. CVBS Video Input 42MFx30A/37 shall provide a RCA type receptacle for connection to an external CVBS source.
③. Audio Inputs 42MFx30A/37 shall provide two RCA type receptacles for the stereo audio signal associated with AV1 input.
1-3-1-3 AV2 A standard definition analog video/audio source designated as AV2 shall be located at the side of 42MFx30A/37. It comprises the following electrical connections. Only one of the two video inputs shall be connected.
①. S-Video Input 42MFx30A/37 shall provide a 4-pin mini-DIN connector for connection to an external S-Video source.
②. CVBS Video Input 42MFx30A/37 shall provide a RCA type receptacle for connection to an external CVBS source.
③. Audio Inputs 42MFx30A/37 shall provide two RCA type receptacles for the stereo audio signal associated with AV2 input.
1-3-1-4 AV3 A YPbPr/YcbCr type component video interface designated as AV3 shall be located on its back panel. It comprises the following electrical connections.
①. Video Inputs 42MFx30A/37 shall provide three RCA type receptacles for connection to an external component video source.
②. Audio Inputs 42MFx30A/37 shall provide two RCA type receptacles for the stereo audio signal associated
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with Component1 input. 1-3-1-5 AV4
A YPbPr/YcbCr type component video interface designated as AV4 shall be located on its back panel. It comprises the following electrical connections.
①. Video Inputs 42MFx30A/37 shall provide three RCA type receptacles for connection to an external component video source.
②. Audio Inputs 42MFx30A/37 shall provide two RCA type receptacles for the stereo audio signal associated with Component2 input.
1-3-1-6 PC Input 42MFx30A/37 accommodates a VGA type computer connection as specified below.
①. Video Input connector 42MF130A/37 shall provide a 15-pin D-Sub connector on its back panel for connection to a VGA type video source. The VGA signal input on the display shall be capable of receiving RGB analog video, H and V syncs, and DDC. The table below specifies pin-outs of this connector.
Analog Connector Pin-outs
PIN MNEMONIC SIGNAL
1 RV Red Video 2 GV Green Video 3 BV Blue Video 4 NC None 5 GND Ground (DDC Return) 6 RG Red GND 7 GG Green GND 8 BG Blue GND 9 +5 V +5 V (from the PC) 10 SG Sync Ground 11 NC None 12 SDA DDC Data 13 HS Horizontal Sync 14 VS Vertical Sync 15 SCL DDC Clock
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11 15
5
10
②. Audio Inputs
42MFx30A/37 shall provide a 3.5 mm jack for the stereo audio signal associated with VGA input.
③. Input Formats 42MFx30A/37 shall support the following input format on its VGA input.
Horizontal Vertical
Mode Resolution Total Nominal
Frequency (KHz)
Sync Polarity
Nominal Freq. (Hz)
Sync Polarity
Nominal Pixel Clock (MHz)
VGA 640x480@60Hz 800 x 525 31.469 N 59.940 N 25.175 SVGA 800x600@60Hz 1056 x 628 37.879 P 60.317 P 40.000 XGA 1024x768@60Hz 1344x806 48.363 N 60.004 N 65.000
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1-3-1-7 DVI 42MFx30A/37 shall accommodate a DVI type digital video source as specified in this section.
①①. Video Inputs42MFx30A/37 shall provide a 24 contact DVI-D receptacle on its back panel for receiving TMDS digital video. The table below specifies pin assignments for the DVI-D connector.
DVI-D Digital connector pin assignmentsPIN MNEMONIC SIGNAL
1 TX 2 - TMDS Data 2 - 2 TX 2 + TMDS Data 2 + 3 SHLD 2 / 4 TMDS Data 2 / 4 Shield4 TX 4 - TMDS Data 4 - 5 TX 4 + TMDS Data 4 + 6 DDC Clk DDC Clock7 DDC Data DDC Data 8 N/C No Connect9 TX 1 - TMDS Data 1 -
10 TX 1 + TMDS Data 1 + 11 SHLD 1 / 3 TMDS Data 1 / 3 Shield12 TX 3 - TMDS Data 3 - 13 TX 3 + TMDS Data 3 + 14 +5V +5V Power (from the PC) 15 GND Ground (Return for +5V) 16 HPD Hot Plug Detect 17 TX 0 - TMDS Data 0 - 18 TX 0 + TMDS Data 0 + 19 SHLD 0 / 5 TMDS Data 0 / 5 Shield20 TX 5 - TMDS Data 5 - 21 TX 5 + TMDS Data 5 + 22 TX CLK SHLD TMDS Clock Shield23 TX CLK + TMDS Clock +24 TX CLK - TMDS Clock -
②②. Audio Inputs42MFx30A/37 shall provide a 3.5 mm jack for input.
③③. HDCP support HDCP must be supported on the DVI input. RProtection System specification version 1.1 for d
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the stereo audio signal associated with DVI
efer to the High-bandwidth Digital Content etails.
42MF230A/37 shall support the following input format on its DVI input.
Mode Resolution Total Nominal
HFrequency (KHz)
Nominal Vertical
Frequency (KHz)
Nominal Pixel Clock Frequency
(MHz)
VGA 640x480@60Hz 800 x 525 31.469 59.940 25.175 SVGA 800x600@60Hz 1056 x 628 37.879 60.317 40.000 XGA 1024x768@60Hz 1344x806 48.363 60.004 65.000 720P 1280×720P 45.00 60 74.25 1080i 1920×1080i 33.75 60 74.25 480p 720×480p 31.54 60 27.00
④④. Input Formats
42MF130A/37 shall support the following input format on its DVI input.
Mode Resolution TotalNominal
HFrequency(KHz)
NominalVertical
Frequency(KHz)
Nominal Pixel Clock Frequency
(MHz)
VGA 640x480@60Hz 800 x 525 31.469 59.940 25.175SVGA 800x600@60Hz 1056 x 628 37.879 60.317 40.000XGA 1024x768@60Hz 1344x806 48.363 60.004 65.000720P 1280×720P 74.25 60
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1-3-2 Audio/Video Outputs 1-3-2-1 Composite Video Output
42MFx30A/37 shall provide a RCA type receptacle on its back panel for composite video output. 1-3-2-2 Analog Audio Output
42MFx30A/37 shall provide two RCA type receptacles for external connection to a stereo amplifier.
1-3-2-3 Head Phone 42MFx30A/37 shall provide a 3.5 mm jack at side of 42MFx30A/37 for external connection of a stereo headphone.
1-3-3 Power Interface 1-3-3-1 Power Connector
42MFx30A/37 shall support an IEC C-13/C-14 (Standard) type male power receptacle for connection to AC power source.
1-3-3-2 Power Input Range The operating range shall be from 100 to 265 VAC sinusoidal for 42MF130A and 100 to 240VAC
1-3-3-3 Power Consumption ①①. Operating Power
Power consumption for the display over the specified voltage and frequency ranges shall be less than 350 W for the assemblies with speakers for 42MF130A and less than 450 W
②②. Standby Power 42MFx30A/37 power also below than one watt in the standby mode.
1-3-4 Service Interface 42MFx30A/37 shall provide a 9-pin D-sub connector on its back panel for firmware upgrading purpose. This interface shall conform to RS-232 standard with the following pin-outs.
Pin Function 1 NC2 TXD transmitted data 3 RXD received data 4 Shorted with pin 6 5 FG frame ground 6 Shorted with pin 4 7 Shorted with pin 8 8 Shorted with pin 7 9 NC
The method of firmware upgrading please see “Flash update process” chapter.
1-4 User interface 1-4-1 Power Indicator
42MFx30A/37 shall make use of an LED type indicator located on the front of the display. The LED color shall indicate the power states as given in the following table.
LED colors Mode H-Sync V-Sync Video Pw-cons. Indicator
Power-On On On Active < 450W< 350W/ Blue LED Standby Off Off Off < 1W Red LED
sinusoidal for 42MF230A. Input power frequency range shall be from 50 to 60 Hz over the specified input voltage range.
for 42MF230A.
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1-4-2 Remote Control Receiver 42MFx30A/37 shall provide an infra-red (IR) optical detector on its front panel for use as the receiver for remote controller signal. The IR communication protocol shall conform to RC-5 standard. The minimum IR reception angles shall be +/- 30 degrees horizontally and vertically. The required operating distance of the remote control shall be 7 m.
1-4-3 On-Screen Display
42MFx30A/37 shall provide an On Screen Display (OSD) system for customer setup. The following table gives the structure of the OSD menus.
Main menu Sub menu Function Default Reset
Tuning Band To select between Terrestrial and Cable System Air —
Signal Strength To display the signal strength in order to aid the antenna adjustment — —
Auto Channel Search
To scan all TV channels and store them in memory — —
Manual Channel Set To enable or disable channels — —
Channel Label To rename a channel — —
SETUP
Manu Language
To select the language for OSD among English, Spanish, and French English —
CONTRAST To adjust the contrast value between 0 and 63 50 Yes
BRIGHTNESS To adjust the brightness value between 0 and 63 50 Yes
SHARPNESS To adjust the sharpness value between 0 and 63 50 Yes
COLOR To adjust the color value between 0 and 63 50 Yes TINT To adjust the tint value between 0 and 63 50 Yes COLOR Temperature
To adjust the color temperature and white balance. Yes
Aspect Ratio To select aspect ratio among Normal, Zoom, Wide, and Cinema Normal Yes
VIDEO
Settings To restore all video settings to factory default — — Audio Language
To select audio language among English, Spanish, and French English Yes
BASS Sets the bass value between 0 and 63 31 Yes TREBLE Sets the treble value between 0 and 63 31 Yes
BALANCE Sets the left/right balance value between 0 and 63 31 Yes
AUDIO
Restore Default To restore all audio settings to factory default — — Time Set To set current time — —
Sleep Timer To set the timer period to turn off the TV. Selectable values are OFF, 30, 60, and 90 minutes
OFF —
Password Set To set or change Parental Control password TBD —
FEATURE
Parental Control To select V CHIP settings Un-locked —
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1-5 External Mounting Requirements 42MFx30A/37 shall be designed so that the display enclosure can be easily removed from thebase for external mounting applications. When the base is removed, there shall be no additional non-removable parts that are visible from the front of the display
1-6 Environmental Requirements 1-6-1 Temperature Ranges
Operating Temperature (Independent of altitude) 42MF130A.................... 5°C to 35°C 42MF230A.................... 0°C to 40°C
42MF130A.................... 20% to 80% 42MF230A.................... 10% to 85%
42MF130A.................... 5% to 80% 42MF230A.................... 5% to 85%
42MF130A......... 0 to 6,562 ft. (0 to 2,000 m) 42MF230A......... 0 to 6,562 ft. (0 to 3,000 m) 42MF130A......... 0 to 9843 ft. (0 to 3,000 m) 42MF230A......... 0 to 9843 ft. (0 to 3,000 m)
Non-Operating Temperature (Independent of altitude) 42MF130A.................... -20°C to 60°C 42MF230A.................... -10°C to 85°C
1-6-2 Humidity Operating (non-condensing)
Non-Operating (38.7°C maximum wet bulb temperature
1-6-3 Altitude Operating
Non-Operating
1-6-4 Vibration and Shock All testing shall be done in each of three mutually perpendicular axes, referenced to the position of the system as it is in front of the user (i.e., front-to-back, side-to-side, and top-to-bottom).
2、、Precautions and Notices::2-1 Precaution of assembly
(1)Please do not press or scratch PDP panel surface with anything hard. (2)Please wipe out PDP panel surface with absorbent cotton or soft cloth in case of it being soiled (3)Please wipe out drops of adhesive like saliva and water in PDP panel surface immediately. They might
damage to cause panel surface variation and color change (4)Do not apply any strong mechanical shock to the PDP panel
2-2 Precaution of Operation::(1)Please be sure to unplug the power cord before remove the back-cover. (make sure the power is turn-off) (2)Please do not change variable resistance settings in PDP MODULE; They are adjusted to the most
suitable value. If they are changed, it might happen LUMINANCE does not satisfy. (3)Please consider that PDP MODULE takes longer time to become stable of radiation characteristic in
low temperature than in room temperature. (4)Please pay attention to displaying the same pattern for very long-time. Image might stick on PDP.
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3、Operation 3-1 Operation of Remote Control Transmitter
42MFx30A/37 shall provide an IR remote controller as accessory.
“POWER”To switch TV set between
power on and standby modes.
“MUTE” To mute the audio output.
“MENU”To enter Menu mode.
“ENTER”To enter sub Menu or sub
item.
“MTS” To select audio programoptions.
“CC” To select close caption options (CC1, CC2 ...)
“VOL- (�)/ VOL+(�)”To decrease or increase the
sound volume. Also to navigateleft or right the Menu.
“0~9 number”To enter TV channel number.
“LAST” To switch to the previouslyviewed channel.
“EPG”To enter or exit Electronic
Program Guide.
“SOURCE” To select input source.
“SLEEP”To Adjust sleep timer options.
“•(dot)” To enter sub channel number.
“CH+ (� )/ CH – (�)” To select the next higher or lower channel. Also to navigate up or down the Menu.
“Exit” To exit Menu or other OSD.
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3-2 Front panel controls
- CH + - VOL + MENU MODE
⑦
⑥
⑤
④
③
②
①
� IR: Remote Control Sensor.
② Power switch: Press to power on or power off the TV set..
③ ● LED: Power Indicator. ④ MODE Mode: Press to select input signal modes or use as Enter in Menu operation. ⑤ MENU Menu: Press to enter Menu or exit Menu.
⑥ -VOL+ Left: Press to decrease the sound volume level or move Left in Menu operation. Right: Press to increase the sound volume level or move Right in Menu operation.
⑦ -CH+
Down: Press to select the next lower Program number or move Down in Menu operation. Up: Press to select the next higher Program number or move up in Menu operation.
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3-3 OSD MENU Description 3-3-1 Main MENU
1. Press “MENU” key on remote control or
front panel controls to bring up Main Menu.
2. Press “ ” or “ ” to move the cursor up
and down the sub menu list.
3. Press “ ” or “” to select sub menu item.
4. Press "Enter" to enter sub-item then use
“ ” or “ ” to adjust.
3-3-2 SETUP MENU 1. Tuning Band: Select TV signal source
between Air and Cable. Select “Cable” if youare connecting to a cable box and select“Air” if you are directly connecting to theantenna.
2. DTV Signal: Display signal strength to aidantenna adjustment.
3. Auto Ch Search: Automatically scan andstore all TV channels.
4. Manual Ch Set: Enter channel setup table. 5. Channel Labels: Display and edit channel
names.6. Menu Language: Select language for menu
(English Español).
DTV signal menu indicates signal strengthin real-time.
Auto channel scan menu displays channelnumber being scanned.
Manual Channel Set Menu Displays all the channel numbers that arefound.Tune either to ATSC or NTSC channels. Add or delete Channel number.
Channel Labels Menu allows user labeling.
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3-3-3 Video MENU
1. Press “ ” or “ ” to move the cursor upor down the sub-item list.
2. Press "Enter" to enter the highlightedsub-item menu.
3. Press “ ” or “ ” to adjust the value ofthe sub-item. 4. Press "Enter" again to exit the sub-item.
Contrast: Contrast adjustment, 0~100.
Brightness: Brightness adjustment, 0~100.
Color: Color chroma adjustment, 0~100.
Tint: Tint adjustment, 0~100.
Aspect Ratio: Aspect Ratio selection.
Normal Zoom Wide Cinema.
Settings: Restore default setting.
3-3-4 Audio MENU
1. Press “ ” or “ ” to move the cursor upor down the sub-item list.
2. Press "Enter" to enter the highlightedsub-item menu.
3. Press “ ” or “ ” to adjust the value of the sub-item.
4. Press "Enter" again to exit the sub-item.
Audio Language:
English Español Français.
Bass: Bass adjustment, 0 ~ 100.
Treble: Treble adjustment, 0 ~ 100.
Balance: Balance adjustment, 0 ~ 100.
Restore Default: Restore Audio Language,
Treble, Base, and Balance setting to default.
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3-3-5 Featuree MENU
1. Press “ ” or “ ” to move the cursor up
or down the sub-item list.
2. Press "Enter" to enter the highlighted
sub-item menu.
3. Press “ ” or “ ” to adjust the value of
the sub-item.
4. Press "Enter" again to exit the sub-item.
Sleep Timer: Select minutes into standbyOff 30 60 90.
Password Set: Enter and change ParentalControl Password.
Parental Control: Setup TV and Movierating controls.
3-3-6 Closed Captions
Parental Control Menu: Controls
viewing of rated TV and Movie
programs.
Note: Need password to change
settings. Default passwd = : 0000
1. Press “CC” key on remote control to select closed captions mode. NTSC TV: Off CC1 CC2 … ATSC TV: Off CS1 CS2 … 2. Select desired closed caption mode.
CC1
NTSC TV
CS1
ATSC TV
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3-3-7 EPG Press the “EPG” key on the remote control
to display the Electronic Program Guide(EPG). A message window will bedisplayed on screen.
EPG Message Window 3-3-8 TV channel arrangement Each digital channel may comprise of
several sub-channels. To select a digital channel using the remotecontrol: 1. Enter main channel number. 2. Press the “•” key. 3. Enter the sub-channel number.
Ch 5.4 19
4、Trouble shooting chart If replace “IMAGE BOARD”, Please re-do “DDC-content” program & “WHITE-BALANCE” & Flash Update.
4-1 PANEL Trouble shooting Please reference the “PANEL Service Manual”. 4-2 Turn PDP on and Check:
Put the power switch after inserting the cable.
Power Cable
Power Switch
LED Light
If PDP under the normal working, display of LED is blue. Then, the screen show is nor dark. If the color of LED is red under standby state, you should press the “power” bottom of remote control or you should press the front standby key. Then, turn PDP TV on. If it is nothing about OSD or display on screen, service PDP. The procedure and maintain the step meet as follows:
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4-2-2 Solution process of whole PDP:
R128
Q5
Screen is nothing under power on
Check AC input of PDC
Check PowerSTB5V(U516 3PIN)Voltage: 5V
Check the REL-SW state of power IOinterface, High Voltage:Turn on Low Voltage:Standby Test Point: C pole of Q5 High Voltage:5V(4.2---5.3V) Low Voltage:0V
If REL-SW is ok,check otherpower.
Check the voltage of CN703: PIN5 -- 12 V PIN8 -- 3.3 V PIN9 -- 3.3 V PIN11 -- 6 V (Samsung PANEL)
Check device circuit and logic circuit,Vs, Vset, Vsc, Ve etc. Arrow shows test point.
If there was anythingunmoral, test voltage andrepair it.
Process of repair as follow
Image board
CN
703 C
N704
Q5
Fig1: Voltage sheetName Voltage Reference VS 170V Voltage for driving sustain VA 70V Voltage for driving address VE 155V Voltage for driving X-bias VSET 160V Voltage for driving reset Vscan -65V Voltage for driving scan VCC 15V Voltage for driving FET D3V3 3.3V Voltage for driving logic
U516
21
4-2-3 STB POWER Solution process
No input of +5VSB,or output is unmoral Test point:CN903 PIN2 Voltage:5V(4.9-5.1)
Test AC Input of CON901ok or not? Voltage:AC 100 V ~ 120 V/200 V ~ 240 V
Test voltage of C905is DC300V or not?
Check FUSE F901,BD901ok or not?
Check IC901 and D901ok or not?
+5VSB OK
No input of AC Powerout, or output is unmoral Test point:CN902 Voltage: AC INPUT±1V
NG
NG
OK
OK
OK
NG
NG
PS-ON ok or not? Test point:CN903 PIN4 Voltage:DC5V(High)
Vccp ok? Test pads of C909 Voltage:DC13V-25V
Q901, Q902, Q903, Q904,
M902 ok or not?
AC POWER-OUT OK
OK
OK
OK
Check circuit of IMAGE BOARD, and check PS-ON OK or not?
Do these process under the state is +5VSB
POWER un-moral
Note:Must distinguish connect Grand point of Power primary and secondary level. 22
4-2-4 Solution processes for DC Power
NG
OK
Test input voltage: L701 -- 12 V L703 -- 6 V L721 -- 3.3 V (Samsung PANEL)
Test voltage as follow: L705-- 8V L706-- 5V L704-- 5V L718-- 2.5V L719-- 1.2V
OK
Check the junction that CN703 to CN704 or CN701 to CN702 ok or not?
Is there any short or cold solder?
4-2-5 Solution processes for SCALER
NG
Check power supply , input and output signal of U1(ZR391055) and U2(DS90C2501)ok or not?.
OK
OK
Check input and output signal of U8,and TX0-/TX0+ signal etc. okor not?
Is there any short orcold solder?
NGReplace U8
23
4-2-6 Solution processes VIDEO
NG
Check the state of powerswitch ,and DC power.
1.Test input signal of U14 under VIDEO and S-VIDEO mode 2. Test input signal of U1 at C18/C19/C20 under YCbCr mode
Check circuit of U6 (PW1231) ok or not?
Check U1
OK
OK
Is there any short or disconnection, and signal is wrong. (The signal of standard color barwill be very clear)
Is there any short or disconnection, CLK and SYNC signal to U1circuit?
NG
OK
OK
Check circuit of U20(SCALAR)and LVDS
NG Is there any short or disconnection, CLK and SYNC signal to U6 circuit?
OK
U6
X5
No display under Video, S-video, YCbCr and YPbPr mode
24
5、White-Balance Adjustment 5-1 Equipments list
Chroma7100 1set VG828 video signal generator 1set Chroma-2326 1set
5-2 Preparation and Adjustment process 1、Preparation: Connect rear Video port of PDP with AV port of VG-828. Connect component port of PDP with YPbPr port of VG-828 Connect VGA port of PDP with corresponding port of Chrom2326 Turn power of PDP and test instrument on. Before open lens, Press O-CAL of Chrom-7100 and revise lens.
2、Adjustment process AV Adjustment
1). Change to Video mode, you can press “SOURCE” of remote. Press “Vol - ”, adjust volume until Min. Then press number key “6543”and enter factory Menu.
2). Press “SOURCE” and change to Video Rear mode 3). When setting of VG-828 is TIM946/PAT922, 32 Gray steps. Then, see the color of picture
is deflection or not. And the Gray steps distinguish 28 steps from 32steps or not. ①. If dark of Gray is deflection, press “CH+/-”and adjust:
②. If
4). WinsChcothe
5). W
Gr Note: adjustPleaseand fin
1.White.BRoCVBS (vMin=0,vMax=100,vDef=50) →50, 2.White.BBoCVBS (vMin=0,vMax=100,vDef=50) →50, 3.White.BGoCVBS (vMin=0,vMax=100,vDef=50) →50,
sharpness of Gray is deflection, press “CH+/-”and adjust:
4.White.BRgCVBS (vMin=0,vMax=100,vDef=50) →50, 5.White.BBgCVBS (vMin=0,vMax=100,vDef=50) →50,
hen the Gray is ok, change input signal to white picture at P936, Use colored analysis trument Chroma7100 measure colors temperature value of picture at present (whether roma7100 is it given to picture center to pop one's head), On pressing the remote ntroller such as the specification of going beyond "program + /- "key choose following projects adjust:
4.White.BRgCVBS (vMin=0,vMax=100,vDef=50) →50, 5.White.BBgCVBS (vMin=0,vMax=100,vDef=50) →50,
hen adjustment about white is ok, changes signal to P822 that Gray steps picture. The ay picture has no deflection color, and the Gray steps distinguish 28 steps from 32steps
The white balance is adjusted in the course, will influence each other to adjust in the ment of gray steps and white picture, and need to change repeatedly. notice that can't enter the mode of the factory in every station homework after adjusting ishing, so as not to miss movements and revise the white balance data again.
25
VGA Adjustment
Setting of Chroma2326 as follows: Gray picture: TIM4/PAT48 White picture: TIM4/PAT105
Change to VGA mode, press “CH+/-”and adjust following items. Method same as AV mode:
67891
Note: Prewhite bal(White.BB
COMPONENT
1). VG828
2). Changas AV
12345
Adjustme
6、DDC program6-1 Equipments DDC teste PC D-SUB ca DVI cable Barcode re Prepare befo
1. Turn on2. Connec
6-2 Program and
1. Choose diffesubmenu anbe shown RRGB progr
. White.BRoVga (vMin=0,vMax=100,vDef=50) →50,
. White.BBoVga (vMin=0,vMax=100,vDef=50) →50,
. White.BGoVga (vMin=0,vMax=100,vDef=50) →50,
. White.BRgVga (vMin=0,vMax=100,vDef=50) →50, 0. White.BBgVga (vMin=0,vMax=100,vDef=50) →50,
ss “Source” and change mode that Video Rear to VGA, then adjustment items of ance same as Video Rear First, press “CH+/-” and adjust under the VGA mode. gCVBS(vMin=0,vMax=100,vDef=50)→50 CVBS change to VGA)
Adjustment: setting as follow:
Gray picture:TIM954/PAT922 White picture:TIM954/PAT936
e to COMPONENT1 mode,press “CH+/-”and adjust following items. Method same mode:
. White.BRoVga (vMin=0,vMax=100,vDef=50) →50,
. White.BBoVga (vMin=0,vMax=100,vDef=50) →50,
. White.BGoVga (vMin=0,vMax=100,vDef=50) →50,
. White.BRgVga (vMin=0,vMax=100,vDef=50) →50,
. White.BBgVga (vMin=0,vMax=100,vDef=50) →50,
nt stand of white Balance: x=299±15,y=315±15
and test list and prepare r 1PCS 1set ble 1PCS 1PCS ader 1set
re test: the power of your PC and programmer, then make good connection of them. t the D-SUB wire and DVI wire to the DDC program equipment and the PDP monitor.
test process rent DDC menu according to different customer , do use PAGE DOWN/PAGE UP to go to the d parent menu until find the right model. Press enter to access the program interface. There will GB on the screen. Then switch to RGB program on the DDC connector。Press any key to access am interface ,then there will be “input serial no.:” prompt on the screen.
26
2. Use Bar Readers to read the serial no to the program,then make sure the serial no you have read is the same as on the barcode. Then set the PDP to blue screen mode, press enter to start.
3. Watch the information of the program, it means programmed OK when the following interface come out.
please CHECK Manufacturer Name、Vendor Assigned Code、Model Name、Serial Number:****[?????????****](same as Barcode)、Week of Manufacture:**、Year of Manufacture:****、Checksum:
**(same as the last byte of data table, reference to the note of RGB programming picture)and so on.
4. Press Enter to access RGB DDC test interface,follow the DDC test picture,CHECK Manufacturer Name、Vendor Assigned Code、Model Name、Serial Number:****[?????????****](same as Barcode)、Week of Manufacture:**、Year of Manufacture ****、Video Input:Analog、Checksum:**(same as the last byte of data table, reference to the note of RGB programming picture)and so on.
5. Press any key to access DVI program interface, there will be “DVI” shown on the screen. Switch the of switch on the DDC connector, press any key to access DVI program interface, there will be “input serial no.:” promote.
6. Use Bar Readers to read the serial no to the program,then make sure the serial no you have read is the same as on the barcode. Then set the PDP to blue screen mode, press enter to start.
7. Watch the information of the program, it means programmed OK when the following interface come out. please CHECK Manufacturer Name、Vendor Assigned Code、Model Name、Serial Number:****[?????????****](same as Barcode)、Week of Manufacture:**、Year of Manufacture:****、Checksum:
**(same as the last byte of data table, reference to the note of DVI programming picture)and so on.
8. Press Enter to access DVI DDC test interface,follow the DDC test picture,CHECK Manufacturer Name、Vendor Assigned Code、Model Name、Serial Number:****[?????????****](same as Barcode)、Week of Manufacture:**、Year of Manufacture ****、Video Input:Analog、Checksum:**(same as the last byte of data table, reference to the note of DVI programming picture)and so on。If the recording is failure, check the connection of equipment and record again from the step4.If all of these work does not take work ,please ask IE department for help.
9. Notice :the “?” and “*” symbol will be changed according to the year of manufacture ,and so on. 27
7、、Flash Update 7-1 The list of Instrument
1、Prepare 1 piece of RS232 cable(The Pin connection see the Figure-1,If difference, please re-connect thecable)and 1 set of PC.
2、 Connect the RS232 cable with PC and PDP(See the Figure-2).
7-2 Th
ThsyDoSte
RXDTXDDTRGNDDSRRTSCTS
To PCTo PC9 Pin (Fem
Signa
To Philips PDPTo Philips PDP
RXDTXDDTRGNDDSRRTSCTS
RXDTXDDTRGNDDSRRTSCTS
To PCTo PC9 Pin (Fem
Signa
To Philips PDPTo Philips PDP
e operation explaining Flash Update
Note: Operation Under the situation of PDP working normally.
e iDev is a Windows utility that installs hex files into the FLASH ROM of the target Image Processorstem. iDev is a Windows-based application.wnloading is done through an RS-232 connection, which is bidirectional and serial.p 1: Open the file iDev (You should
Figure-1 Figure-2
RS232 Connector
PC
RS232 Cable
PDP1
2 3 4 5 6 7 8
9
12 RXD Received Data 3 TXD Transmitted Data4 DTR Data Terminal Ready5 GND Signal Ground6 DSR Data Set Ready7 RTS Request To Send8 CTS Clear To Send9
ale)
l Pin
9 Pin (Female)
Signal Pin1
2 3 4 5 6 7 8
9
1 2 3 4 5 6 7 8
9
12 RXD Received Data 3 TXD Transmitted Data4 DTR Data Terminal Ready5 GND Signal Ground6 DSR Data Set Ready7 RTS Request To Send8 CTS Clear To Send9
ale)
l Pin
9 Pin (Female)
Signal Pin
28
Step 2: Choose the director of the file to flash
Note: Connect the computer’s serial port (usually COM1) to the serial port of the ZORAN evaluation board using a null modem cable, and select speed. Step 3: Flash only the file required
29
Step 5: Press reset or cycle the power from the Evaluation Board and click “down”
Step 6: View hex file flashing progress, after the files have been downloaded, Click “Close” to exit
30
8、Software Platform Reference TV Application 8-1 Introduction
This document describes Phobos’s reference TV application, supporting the basic control functionalities required to watch television. The reference application is designed to assist Phobos customers in implementing a DTV system, using the Generation9-Elite IC and its APIs. This reference application is intended to support U.S. based terrestrial analog/digital broadcasting(NTSC/ATSC), and includes Electronic Program Guide (EPG), closed captioning, and parental control, as well as basic TV controls and underlying A/V decoding. The reference TV application layer lies on top of Phobos’s Cougar API middleware that provides the Transport/Audio/Video/graphics driver functionalities as a chip-independent set of APIs.
8-1-1 Supported Functions
The supported application functions are: • Power control • Source selection • Channel change (up/down, recall and direct digit key input) • Volume and mute control • Closed caption selection • Electronic program guide • Menus: audio, video, setup, feature
8-2 The Phobos Reference TV Application
This chapter describes basic TV controls such as channel changing, source selection, and mute/volume control. These basic functionalities are made available through the combination of GUI and standardized TV APIs. The application also utilizes the results of PSIP parsing and decoding of EIA708/608 data. These are used to support closed captioning and parental control, both of which are required on television sets sold within the U.S. In addition to Tuner, AV Input and Channel Map APIs, the reference application uses a set of Control Array APIs to control the hardware blocks. These provide a standardized way to control the various hardware blocks in the TV chassis.
8-2-1 Power Control
The current reference application does not support standby power control as part of this implementation. Instead, pressing the power button on the remote and front panel controls the display and audio outputs only. A power-on configures the system based on Control Array values stored in non-volatile memory.
8-2-2 Source Selection
The Reference platform has analog/digital base band inputs as well as transport input through ATSC digital channel. The TV/Input button cycles through the input sources:
1. RF 2. Front Composite (shared with S-video) 3. Rear Composite (shared with S-video) 4. YPbPr Component 1 5. YPbPr Component 2 6. VGA 7. HDMI input
The displayed banner for changing source is the same as the channel banner, except for displaying source number and name. 31
8-2-3 Channel Change There are three ways to select a channel in the reference TV application: channel up/down, digital, and last buttons in remote controller.
• Pressing the channel up or down key tunes to the next highest or lowest channel in the selected channel map; a channel in a different channel group (analog or digital) is tuned at the limits of the available scan. The channel map is established through the Auto Program menu, which automatically removes any no signal channels. After channel scanning, the channels are grouped as digital channels and analog channels.
• For digital channels, the channels are sorted on the virtual channel number. Further manual editing of the channel list can be done through the Manual Channel Set menu. If no channels are enabled in the selected channel map after initial power on, then the channel up/down keys select the channel number next to the current channel, and determine the analog or digital channel based on the availability of signal.
• Channels can be directly accessed by pressing the digit keys on the remote controller. The channel selected is tuned immediately if the OK key is pressed, or will be tuned automatically after two seconds of inactivity following the last entered digit. If the entered digit keys starts with a zero (“0”), the channel number will be tuned to the second digit (for instance, the digits 03, entered in sequence, will tune immediately to channel 3). Any channel may be selected by this method, regardless of its presence or absence in the current channel map.
• Pressing the Last key in the remote control tunes the channel selected prior to the currently tuned channel. For ATSC channels, it selects the sub-program number as well as the channel number.
The above channel-change operations are implemented via the Tuner and Channel Map APIs. After tuning, the application displays the information of the currently-tuned channel. This includes:
1. Channel number [Ch 9-1] 2. Channel Label [for instance, KQED] 3. Current Time [for instance, 12:30 PM] 4. Rating information [for instance, TV-PG]
The virtual channel number will be displayed if the current channel is digital. The channel label is extracted from input signal if there is no label setting for the current channel. The channel label can be explicitly set with Channel Labels menu, which will use TLChMapSetChannelName to store the label.
8-2-4 Volume and Mute Control
Pressing the volume Up or Down button changes the current volume in the Control Array and applies this change to the hardware block. The range of control is determined by the Control Array; the current implementation has a range from 0 to 63. Pressing either of the volume keys clears the mute audio mode of operation, if previously set. If no button is pressed for five seconds after pressing the last volume Up or Down button, the volume display will be automatically removed. The reference application supports audio mute or un-mute by pressing the Mute key. When mute is enabled, the audio is muted, displaying an icon on upper right side. The mute condition is cleared when the TV is powered off. Pressing the Mute key invokes the mute icon on the right corner of screen.
8-2-5 Closed Caption Selection
This section describes how to enable Closed Caption (CC) on the Phobos TV application. When the TV is switched ON, captions are disabled by default. The user switches captions ON using the [SUBTITLE] key on the remote. Each time the [SUBTITLE] key is pressed, a new language/CC option, is displayed near the bottom center of the display. The sequence of options available are listed below (depending upon the stream type — ATSC/NTSC). For ATSC, English – Spanish – French – Off For NTSC, CC1 – CC2 – CC3 – CC4 – Off The displayed CC option can be set either by the user pressing the [OK] key on remote, or else it is set automatically after two
32
seconds. 8-2-6 Navigating a Menu
Pressing the Menu button displays the most-recently-used menu. The main menu is presented in two areas: a group of icons, and a list of sub-menus based on the selected icon. After launching the menu, the Left/Right buttons are used to select one of the two areas. The icons and sub-menus can then be navigated through the Up/Down arrow keys, which moves the highlighted item up or down, depending on the key pressed. This display gives the user a method of selecting among the various sub-menus available, in order to configure the system. The action wraps from first to last when an up arrow is received and the first list item is highlighted, and from the last to the first when a down arrow is received and the last list item is highlighted. If no key is pressed for one minute after pressing the last navigation or OK buttons, the volume display will be automatically removed.
9、Block diagram & Explain 9-1 PDP block diagram and functions
Panel
Image Board PCB
POWER PCB
CN5008 to CN8003
CN4001 to CN8086
Power Down Control PCB
Front AV PCB
CN009 to J11
CN004 to J30
J6 to Panel
J42 to P210
CN904 to CN703
CN903 to CN704 & J603
CN706 to CN903
CN8001 to CN902
Key Board PCB
Function of Board: 1) IMAGE Board : Control all input signals, Decode the video signal, De-interlace, and
send digital signals (LVDS signal) sent from image Board and display 2) PDC Board: Power Down Control Board 3) SIDE AV Board: The input signal interface 4) Power Board: Supply Power for Panel and Image Board 5) KEY Board: POWER, Signal Source, MENU, CH+, CH - / VOL +, VOL - 6) Power ON /OFF: Turn power on/off
33
Part apt to decrease:1) BEZEL, REAR COVER& GLASS FILTER2) Panel 3) Terminal Board’s RCA plug
9-2 Image board block diagram and signal introduce/process9-2-1 Image board block diagram
34
9-2-2 Signal introduce/process
AnalogAV
Process
ScanDrive
Y
ATSC/NTSC TV (Tuner) Audio Process
SMPS Powersupply
DATA Drive
ScanDrive
X
Logic (Memory Con
X-Y Con.)
PDP ModuleATSC/NTSC TV
PPDDPP PPaanneell
Speaker
MPEG Signal
Process
SignalSCALERProcess
PDP Module
Video / Audio block
PanelSDI-42HD
35
ATSC+NTSC TV RF signal are separated into 2 way output when enter into Tuner. One is NTSC (Analog signal) that output video signal by mixing, amplifying, demodulating. Video signal are separated into Y/C signal throughTEA6415C, and transferred into ITU601 through ADV7401, then send into Video-audio process chip Generation9. Tuner output SIF audio signal to MSP3450G to process, amplify, then put in D-type amplifier TA2024.
The other ATSC (Digital signal, ATSC channel bandwidth is 6MHZ) via Tuner transferred into TS-stream through 44MHZ intermediate frequency amplify, ASW filter, QAM\OFDM demodulate, then enter into Generation-9 to MPEG decode, video part revert into video signal through coding, and transferred into double-field TTL signal by this chip process. Then put into Scaler and LVDS drive chip DS90C2501, through coding output 5 pair LVDS signal to drive PDP panel module. Digital audio signal from Generation-9 revert into Audio signal to MSP3450G through PCM decoding.
Program information in TS-stream be parsed and stored, user could know related program information through OSD query menu. For multi-program TS-stream, user could appoint to see some program in this stream through program guide EPG.
AV, S-video, YPBPR, DVI, D-Sub and each Audio signal through two group of 74HC4052 switch with ATSC audio signal together put into MSP3450G, through alt, woof, balance, volume, SRS, BEE process, then amplify by D power amplifier TA2024,output to loud-speaker.
36
9-2-2 Input signal introduce1. VIDEO: transmit bright & chroma signal , it is general ,its picture quality is equal to the general VCD.
S-VIDEO transmit the bright and the chroma single, and can reduce/control the cross-interfere , it is betterthan the Video.
2. RGB&D-SUB(Pc interface ): general RGB simulative input interface . 3. YCbCr(NTSC/PAL): is composed of one bright and two chromatism signals U/V. due to the eye is more
sensitive for bright than chroma , RGB via the formulae Y=0.39R+0.50G+0.11B to transform into one brightand two chromatism signals U(R-Y), V(B-Y).
4. VIDEO、、S-VIDEO、、YCBCR: the frequency 15.6KHZ 50(PAL)/60HZ(NTSC), interleaved simulative signal.5. YPbPr: non-interlaced signal, belong to DTV scope, support 480P,720P,1080i format, current is NTSC.
6. DVI:digital Visual Interface, has 29pin(DVI-I)and 25pin (DVI-D), now many top grade display card own it.
10、、Waveform of signal10-1 Waveform of input signal
(Instrument outputs the sub board signal,,Instrument::VG828/ TG19CC/Oscillograph)YCbCr: Timing946 Pattern946 color bar pictureY Luminance Signal R Red Signal
B Blue Signal
YCbCr: Timing 949 Pattern936 Full White Picture
37
Y Luminance Signal
YCbCr:Timing 949 Pattern921 Gray Picture Y Luminance Signal
YPbPr:Timing955 Pattern946Color Bar Picture Y Luminance Signal R Red Signal
B Blue Signal
38
YPbPr:Timing953 Pattern921 Gray Picture Y Luminance Signal
YPbPr:Timing954 Pattern936 Full white picture Y Luminance Signal
Video: Timing946 Pattern946 Color Picture Video: Timing949 Pattern936 Full White Picture
Video: Timing949 Pattern921 Gray Steps Picture
39
S-video: Timing946 Patern946 color bar picture S-video: Timing949 Pattern936 Full white picture
S-video: Timing949 Pattern921 gray steps picture
10-2 Signal waveform in the image board Video: Timing946 Pattern946 color bar picture U14(Y/C separate)In (pin3 C136)/(pin20 C142)
40
U14(Y/C separate)Out pin18/17 R119/R120
Video: Timing 949 Pattern936 white picture U7 decoder output 8bit digital signal:
S-Video: Timing 946 Pattern946 color bar picture U14 pin8, pin10
S-Video: Timing 949 Pattern946color bar picture U7 8bit digital signal output:
41
YCbCr: Timing946 Pattern946 Full white picture Y signal—L55 R signal—L53
B signal—L54:
YCbCr:Timing 949、946 Pattern921、936、946 gray scale, color bar, white picture U7 decoder output 8bit digital signal waveform
YPbPr: Timing 955 PATTERN946 color bar picture Y signal—L55 R signal—L53
42
B signal—L54
43
11、Check and Measure 11-1 Image board
Test the power of each chip with the universal meter, to ground impedance and earth situation.
11-1-1 Power Check and Measure
CN703
CN704
J603
Supply with getting red arrow point three interface J603, CN703 and CN704 that identification come out for power, image of board with the interface among having picture, it corresponding power make detection method separately among following several picture.: (Only for SUMWUNG POWER) ①. In the following the first picture it is successively 1 to 6 pin of J603 from left to right:
Among them, 1pin and 2pin connect 12V voltage; 3pin, 4pin and 5pin are digital earth; The second picture it is 1 to 5 pin of CN704 from left to right: Among them,2pin and 4pin of CN704 connect digital earth, 1pin of CN704 connect D6V voltage, 3pin of CN704 connect D12V voltage ,The following picture shows:
44
successively 1 to 11 pin of CN703 from left to right. AmongthemIn the following picture it is
, The second pin connects STB5V,3pin 、6pin 、7pin and 10pin are grounded digitally,5in connect D12V voltage, 8pin and 9pin connect D3.3V voltage,11pin connect D6Vvoltage .The following picture shows:
11-1-2 Voltage value of IC necessary
Voltage Corresponding IC position and pin
3.3V
U706 Pin3; U704 Pin3; U710 Pin3; U2 Pin38; U9 Pin13; U13 Pin3; U10 Pin91;
D40 Pin5; D41 Pin5; U68 Pin3; U30 Pin3, Pin1; J32 Pin7; U48 Pin26; U52 Pin20
STB5V
CN703 Pin2; E708;R301;R635;R68
5V
L722,L713;L706,C718,E717;CN706(PDC Board) Pin2;
TP9;R126,R128;L216,L217;R301,R635,R638
6VU709 Pin3; U702 Pin3; U711 Pin3;
CN703 Pin10; L703;C702
12V
J603 Pin1,Pin2; U701 Pin3; R322;L702,E711;CN703 Pin5; L701;
TP8;U601Pin29,Pin30,Pin33;C700;U602 Pin8; U12 Pin2,Pin4; C695
2
45
11-2 SIDE AV Board The picture below is AV SIDE board, The interface pointed out in order to provides the power for Audio board. The enlarged interface picture show in its connection.
Shown order connect power(it depends on to be 1 pin to 10 pin from left to right) according to the picture:
CN004
11-3 PDC Board The following picture show PDC Board, among them getting red difference label about connection with PDC Board and main board, power board and switch of board.
CN901: Connect with P9Z1 of Power Switch Board; CN902: Connect with CN8001 of Power Board; CN903: Connect with CN706 of Imager Board.
CN903
CN902
CN901
The following picture shows the pin connection of CN903:
46
12、Mechanical Introduction 12-1 PDP Internal view
47
12、Mechanical of cabinet front disassembly 42MF130A
48
12-2 Mechanical of cabinet front disassembly 42MF230A
49
12-3 Disassembly and assembly 12-3-1 PDP stand removal
1
3 2
1) Unplug the AC power and all signal cables.
2) Place the PDP upside down on a tabletop (use a protection sheet or EPE bag), Take care, that this
is flat and free from obstacles like screws, to prevent damaging the fragile PDP glass filter (1).
3) Remove the four black colored screws around the stand holder (2).
4) Remove the Base assembly from PDP as the direction arrowhead showed (3).
50
12-3-2 Back Cover Removal
Notes: Must be press down the power button before remove the back cover, if don’t do this it well be avert broken switch at the remove the back cover.
4) Push in the power button before remove the back cover(4) (to prevent damaging the power button).
Push
5) Carefully prize up the back cover from the left of the PDP (5). Don’t remove the cover in this st
ep, otherwise, the power button should be damaged.
6) Carefully remove the Back Cover from thetop of the PDP, and store in a safe place.
5 4
7) Done.
1
2
3
5) Remove the six big black colored screws in the panel holder as the red-circle showed (1). 6) Remove the seven black colored screws around the terminals as the green-pane showed (2). 7) Remove the eighteen black colored screws around the back cover as the blue-pane showed (3).
51
12-3-3 Rear Low Cover removal
1) Remove the three black screws in Rear low cover (1). 2) Carefully use a allen screwdriver to remove the six silver colored allen screws M3*6mm (2). 3) Remove the five black screws (3).
ZOOM-1 ZOOM-1 1
2 3
4) Remove the one silver screws and remove the GND cable (4).
5) Disconnect the AC cable from AC FILTER Board (5). 5 4
6)Remove the Rear Low Cover as the
direction arrowhead showed (6).
6
7)Done.
52
12-3-4 Main Board(MGPC) removal
1) Disconnect the all connectors(J42,CN706,J14,J603,CN703,CN704,J11,J30 and J6 form M
GPC(main board). See the above figure.
2) Remove the six silver screws from MGPC(main board)(1).
3) Remove the MGPC board from PCB plate. 4) Done.
PCB Plate
1 1
J6
53
12-3-5 PCB Plate Removal
1) Remove the two Cable Clips from the PCB Plate(1)(2).
2) Remove the six sliver screws(3).
3) Cut the cable tie(4), Note, please carefully cut it, don’t make the cable damage.
4) Remove the PCB Plate
1 2
4 3
54
12-3-6 Key Board Remove
1) Remove the four silver screws(1).
2) Pull the Bezel downside(2), then push and take out the KEY board
assembly(3).
Pull
Push and take it out
2
3
3) Remove the five silver screws to disassemble the key board from Key button.
55
12-3-7 Side AV Board Removal
1) Remove the two silver screws (1).
2) Remove the side cover from Side AV board(2)
1
2
3) Disconnect the CN004 and CN009 from Side AV board.
4) Remove the four silver screws (3).
CN004 CN009
3 3
56
12-3-8 PDC(power down control)Board Removal
1) Remove the four sliver screws (1) and remove the panel stand from panel holder as
the direction arrowed showed.
2) Remove the four silver flat screws (2).
3) Remove the two black screws (3)
4) Remove the two silver screws (4)
5) Remove the panel holder from PDP.
ZOOM 1
1 2 3
2
4
ZOOM 2
Panel Holder Panel stand
CN901
CN902
CN903
5
6) Disconnect CN901,CN902 and CN903 from PDC
board.
7) Remove the four sliver screws (5), and remove
the PDC board.
57
12-3-9 Panel Module Removal
1) Remove the eight silver flat screws around the two panel holder (1).
Panel Holder-1
Panel Holder-2
ZOOM 1 ZOOM 2
ZOOM 3 ZOOM 4
1 1
11
2) Remove all the aluminum foil around the panel (2), after assemble the new panel, must re-affix the aluminum foil, if it’s broken must change a new one, otherwise, the EMI can be affected.
3) Remove the twelve silver screw around the PANEL corner (3). 4) Two people hold the panel holder 1 and 2 respectively, then uplift
the panel module and move it out form the front cover(Bezel), and store in a safe place.
2
3
3 3
4
3
58
12-4 Block Wiring diagram 12-4-1 PDP boards block wiring diagram
Main PSU
Image boardImage board
Sub
-PS
U
Key board
Internal speakerRight
Internal speaker Left
AC inSocket
J42 CN706 J14 J603
CN703
CN704
J11
J30
J6
Power input
PDC B/d
CN901
CN902CN903
output
Side AV B/d
CN004
CN009
AC switch B/d
Power filter B/d
AC input
input
AC output
PANEL ModulePANEL Module
Main PSU
Image boardImage board
Sub
-PS
U
Key board
Internal speakerRight
Internal speaker Left
AC inSocket
J42 CN706 J14 J603
CN703
CN704
J11
J30
J6
Power input
PDC B/d
CN901
CN902CN903
output
Side AV B/d
CN004
CN009
AC switch B/d
Power filter B/d
AC input
input
AC output
Main PSU
Image boardImage board
Sub
-PS
U
Key board
Internal speakerRight
Internal speaker Left
Main PSUMain PSUMain PSUMain PSU
Image boardImage boardImage boardImage board
Sub
-PS
US
ub-P
SU
Key boardKey board
Internal speakerRight
Internal speaker Left
Internal speakerRight
Internal speaker Left
AC inSocket
J42 CN706 J14 J603
CN703
CN704
J11
J30
J6
Power input
PDC B/d
CN901
CN902CN903
output
Side AV B/d
CN004
CN009
AC switch B/d
Power filter B/d
AC input
input
AC output
AC inSocket
J42 CN706 J14 J603
CN703
CN704
J11
J30
J6
Power input
PDC B/d
CN901
CN902CN903
output
Side AV B/d
CN004
CN009
AC switch B/d
Power filter B/d
AC input
input
AC output
PANEL ModulePANEL Module
59
No. Pin Connection Name Pin function
1 J42 to Key board MGPC key control signal output
J42 Connector(13 Pins): Pin 1= GND Pin 2= +5VSB Pin 3= IR Pin 4= ENTER Pin 5= LED-B Pin 6=LED-A Pin 7=KEY6 Pin 8=CH+ Pin 9= CH- Pin 10=VOL+ Pin 11=VOL- Pin 12=MENU Pin 13=TV video
2 CN706 to CN903 PDC board DC output, and MGPC standby PDC power control output
CN706 Connector(4 Pins): Pin 1,3= GND Pin 2=+5VSB Pin 4=REL-SW
CN903 Connector(4 Pins): Pin 1,3= GND Pin 2=+5VSB Pin 4=PS-ON
3 J14 to speaker MGPC audio signal output J14 Connector (2 Pins+2 Pins): LO+/COMLO- and RO+/COMRO-
4 J603 to Sub-PSU MGPC audio circuit power input
J603 Connector(6 Pins): Pin 1,2=+12V Audio Pin 3,4,6=GND Pin 5 = NC
5 CN703 to Sub-PSU MGPC power input and relay control output
CN703 Connector(11 Pins): Pin 1=NC Pin 2=STB5V Pin 4=Relay-SW Pin 5=D12V Pin 8,9=D3.3V Pin 11=D6V Pin 3,6,7,10 =GND
6 CN704 to Sub-PSU MGPC power input CN704 Connector(5 Pins): Pin 1=D6V Pin 3=D12V Pin 2,4=GND Pin 5=NC
7 J11 to CN004 To Earphone output J11 Connector(5 Pins): Pin 1,3=GND Pin 2=EAR-L Pin 4 = EAR-R Pin 5=Phone-on
8 J30 to CN009 Side AV signal input
J30 Connector(10 Pins): Pin 1,3,5,9=GND Pin 2=CVBS IN-2 Pin 4=FRONT-Y Pin 6=FRONT-C Pin 7=FRONT-AV-SEL Pin 8=SM-L Pin 10=SM-R
9 J6 to Panel Logic b/d MGPC LVDS signal output
J6 LVDS connector(31 Pins): Pin 1,8,9=NC Pin 2,4,6,11,14,15,18,19,
22,23,26,27,30,31=GND Pin 12=TXE3p Pin 13=TXE3m Pin 16=TXECp Pin 17=TXECm Pin 20=TXE2p Pin 21=TXE2m Pin 24=TXE1p Pin 25=TXE1m Pin 28=TXE0p Pin 29=TXE0m
60
61
13、PCB LAYOUT 13-1 Image board PCB LAYOUT
62
13-2 Audio board PCB LAYOUT
63
13-3 Tuner board PCB LAYOUT
13-4 Key board PCB LAYOUT
64
DELBANE noitarepO daeR-otuA nO-rewoP TUO - 3R.)YLNO M652 gnusmaS rof (
eludoM VTD snoitpO gniffutSxednI teehS
teehS eltiT - 10 egaPF/I suB lacoL - 20 egaP
F/I 0 MARDS RDD - 30 egaProtaludomeD / renuT - 40 egaP
nI oiduA / oediV - 50 egaPF/I IMDH - 60 egaP
stupnI oediV golanA - 70 egaPF/I tropsnarT/redoceD - 80 egaP
ecafretnI oediV - 01 egaPecafretnI oiduA - 11 egaP
teseR/ OXCV / OIS - 21 egaPkcolB sOIPG / desunU - 31 egaPsrotcennoC GATJ/ytilitU - 41 egaP
1 dnG dna rewoP - 51 egaP2 dnG dna rewoP - 61 egaP
.gnittes tluafeD - * :etoN
3 dnG dna rewoP - 71 egaP4 dnG dna rewoP - 81 egaP5 dnG dna rewoP - 91 egaP
noitceleSeciveD tooB = ]42,32,22[Jkcolc ICP LANRETXE htiw ecived atad tib-8 BL morf toob = 111kcolc ICP LANRETXE htiw ecived atad tib-61 BL morf toob = 011
ecived zHK 004 sserdda tib-61 C2I morf toob = 101ecived zHK 001 sserdda tib-61 C2I morf toob = 001
)zHM 72( kcolc ICP lanretni htiw ecived atad tib-8 BL morf toob = 110)zHM 72( kcolc ICP lanretni htiw ecived atad tib-61 BL morf toob = 010
kcolc zHM 1 ,ecived atad tib-8 /sserdda tib-42 IPS morf toob = 100kcolc zHM 1 ,ecived atad tib-8 /sserdda tib-61 IPS morf toob = 000
snoitpO repmuJ draoB ytilitU
)A
)B
edom GATJE - FFO - 72Jedom GATJ - NO - 72J
)2
* .ylno draob D&R roF- NI - 81PT-1PT.ver draob lanif roF - TUO - 81PT-1PT
)1
1SC - hsalFatartS 42U ,0SC - hsalF 32U -- 3-2 - 02J ,NO - 61J0SC - hsalFatartS 42U ,.csiD SC - hsalF 32U -- 2-1 - 02J ,FFO - 61J
)3
.deretla eb tonnac stnetnoc yromem hsalFatartS 42U - ,NO - 71J,edom 61x ni ecived hsalFatartS - FFO - 81J)5
.edom 8x ni ecived hsalFatartS -NO - 81J
)4
elbaT sOIPG - 02 egaP
SDVL / emirP oediV - 90 egaP
*.IPS morf pu-toob lamroN TUO - 8R ,NI -7R)C.hsalf DNAN morf pu-tooB NI - 8R ,TUO -7R
)D * TUO - 825R ,525R.putes slevel thgilkcaB DCL - NI - 825R ,525R
* sCAD 9G rot ferV lanrotxE -- TUO - 685R ,485R ,NI - 585R,385R,94D* sCAD 9G rot ferV lanrotnI -- NI - 685R ,485R ,TUO - 585R,385R,94D
)E
DELBASID noitarepO daeR-otuA nO-rewoP TUO - 3R* .)YLNO M652 gnusmaS rof (
.elbane drac ytilitU 232SR ,NI - 343R ,243R)F.elbane rotcennoc kniL-G ,TUO - 343R ,243R
)detats esiwrehto sselnu( :setoN.1.2.3.4
%5 era dna smho ni detsil era srotsiser llA )rotcaf mrof 3060( mliF lateM ,61/1 ,)rotcaf mrof 3060( R7X ,cimarec ,V52 ,%01 era dna ,sdaraforcim ni detsil era sroticapac llA
,seirnehorcim ni detsil era srotcudni llA )rotcaf mrof 5080( dnuow-non ,am001 ,%5 era dna.steehs neewteb noitisnart dna ,labolG era srotcennoC egaP ffO dna stroP langiS
ro stroP langiS tuohtiw semaN langiS.5 tcennoc ylno dna ,lacoL era srotcennoC egaP ffO .teehs emas eht no slangis deman ekil
Image Board
65
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Local Bus I/FPhobos
Stuff option.
GPIO119GPIO107
GPIO108
GPIO109
GPIO110
GPIO123
GPIO104
GPIO120
GPIO122
GPIO121
GPIO112GPIO113
Stuffing Options
GPIO125
TO Page 7
D2
B
2 22Monday, March 28, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
LBUS_A1LBUS_A0
LBUS_A2
LBUS_D12LBUS_D11
LBUS_D5
LBUS_D1LBUS_D0
LBUS_D14LBUS_D13
LBUS_D10LBUS_D9
LBUS_D4
LBUS_D7LBUS_D8
LBUS_D3
LBUS_D6
LBUS_A3
NAND_CS2_n
LBUS_WRL_nLBUS_WRH_nLBUS_RD_n
LBUS_A21
LBUS_A24
LBUS_A22
LBUS_A25
LBUS_A23
LBUS_CS1_n
LBUS_RDY0
LBUS_AS_n
LBUS_CS3_n
LBUS_CS0_n
LBUS_A[0:25]
LBUS_D2
LBUS_D15
LBUS_A17
LBUS_A11LBUS_A12LBUS_A13
LBUS_A8
LBUS_A18
LBUS_A7
LBUS_A16
LBUS_A4
LBUS_A9LBUS_A10
LBUS_A14LBUS_A15
LBUS_A5LBUS_A6
LBUS_A19
LBUS_RDY1_n
LBUS_RDY1_nLBUS_RDY0
LBUS_A24
LBUS_A25
LBUS_WRL_n
LBUS_AS_n
LBUS_RD_n
LBUS_WRH_n
LBUS_RDY0
LBUS_A20
SEL
LBUS_CS2_n
NAND_CS2_nLBUS_CS2_n
LBUS_A1LBUS_A0
LBUS_A2LBUS_A3
LBUS_D5
LBUS_D1LBUS_D0
LBUS_D4
LBUS_D7
LBUS_D3
LBUS_D6
LBUS_D2
LBUS_D[0:15]
LBUS_A20
LBUS_CS1_n
LBUS_CS3_n
LBUS_CS0_n
LBUS_A[0:25]
LBUS_RD_n
LBUS_WRL_n
LBUS_CS4_n
LBUS_AS_n
LBUS_WRH_n
LBUS_RDY0
LBUS_CS5_n
WP_n
LBUS_D[0:15]
LBUS_CS2_n
NAND_GPIO1_n
ACLK_SEL0
FMS_SEL
IDE_HSCBL_n
ACLK_SEL1
CVmix_SEL
AIN_INT_n
CEC
SLEEP_MODE_n
HD_SEL
HDMA_SCDTTV_VIDEO
HDMI_VSYNC
+3.3V
+3.3V
+3.3V+3.3V
+3.3V R29 10K
R7 0
PCI Bus InterfaceZR391055
(Local Bus)
U1A
ZR391055SH
AC19AD19AB18AF21AC18AE20AF22AB17AF19AC15AF20AE15AD18AD13AF18AC13AB10AF17AC11AE16AD9AF16AE6AF15AF5AD15AE5AF14AC9AE14AF11AD14
AD11
AC14AD17AE18AE19AE11AC17AD10AD16AE12AC16AE17
AF8
AC10
AF13AC12
AE13
AD12AF10AF12
AE10AF7AE9AE7AE8AD8
AF9
LAD0_AD0LAD1_AD1LAD2_AD2LAD3_AD3LAD4_AD4LAD5_AD5LAD6_AD6LAD7_AD7LAD8_AD8LAD9_AD9
LAD10_AD10LAD11_AD11LAD12_AD12LAD13_AD13LAD14_AD14LAD15_AD15
LA4_AD16LA5_AD17LA6_AD18LA7_AD19LA8_AD20LA9_AD21
LA10_AD22LA11_AD23LA12_AD24LA13_AD25LA14_AD26LA15_AD27LA16_AD28LA17_AD29LA18_AD30LA19_AD31
PAR
LA3_CBE3_nLA2_CBE2_nLA1_CBE1_nLA0_CBE0_n
FRAME_nPERR_nTRDY_nIRDY_n
STOP_nDEVSEL_n
SERR_n
INTA_n
IDSEL
REQA_nGNTA_n
PCICLK
INTB_nINTC_nINTD_n
REQB_nGNTB_nREQC_nGNTC_nREQD_nGNTD_n
RST_n
RP1A 10Kx41 8
RP2C 10Kx43 6
R80_NS
R310K_NS
RP1B 10Kx42 7
RP1D 10Kx44 5
RP3C 10Kx43 6
RP1C 10Kx43 6
R1 10K
R110_NS
R910K
RP2B 10Kx42 7
ZR391055LOCAL BUS
PINS (Dedicated)
U1E
ZR391055SH
AC6 AC7AD6
AF6AE4
AD5AC8
AC5
AE3AE2AB8AB7AC4AF1
AB9AD7AF4AA7
LA20 LREADY0LREADY1_n
LA21LAS
LWRH_nLWRL_n
LRD_n
LCS0_nLCS1_nLCS2_nLCS3_nLCS4_nLCS5_n
LA22LA23LA24LA25
C10.1uF
RP2D 10Kx44 5
RP2A 10Kx41 8
RP3D 10Kx44 5
NAND FLASH
U2
NAND128W3A0AN1
2930313241424344
1617
98
1819
7
6
12
1336
37
1234510111415202122232425262728333435
38
394045464748
I/O_0I/O_1I/O_2I/O_3I/O_4I/O_5I/O_6I/O_7
CLEALECEREWEWP
R/B
GND
Vcc1
GNDGND
Vcc2
NC1NC2NC3NC4NC5NC6NC7NC8NC9
NC10NC11NC12NC13NC14NC15NC16NC17NC18NC19NC20NC21
LOCK
NC22NC23NC24NC25NC26NC27
RP3A 10Kx41 8
C20.1uF
R28 10K
R27 10K
RP3B 10Kx42 7
R2 10K
R12 10K
66
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR SDRAM 0 I/F
Phobos
D2
B
3 22Monday, March 28, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
DDR0DQ14
DDR0CK DDR0DQ29
DDR0DQ0
DDR0DQ24
DDR0DQ5
DDR0DM2
DDR0DQ7
DDR0CKE
DDR0DQ2
DDR0DQ16
DDR0DQ12
DDR0DQ20
DDR0CK
DDR0DQ18
DDR0WE_n
DDR0DQ25
DDR0DQ11
DDR0DQ27
DDR0DQ30
DDR0DQ10
DDR0DQ16
DDR0CKE
DDR0BS1DDR0DQ13
DDR0DQ31DDR0DQ26
DDR0DQ24
DDR0RAS_n
DDR0DQ17
DDR0DQ15
DDR0DQ[0:31]
DDR0DQ21
DDR0DQ23
DDR0BS1
DDR0DQ19
DDR0DQ17
DDR0BS0
DDR0DM3
DDR0DQ26
DDR0DQ18
DDR0DQ2
DDR0DQ30
DDR0DQ27
DDR0CK_n
DDR0DQ5
DDR0DQ6
DDR0DQ3DDR0DQ4
DDR0DQ1
DDR0DQ12
DDR0DQ29
DDR0BS1
DDR0DQ22
DDR0CK_n
DDR0DQ20
DDR0DQ28
DDR0BS0
DDR0DQ8
DDR0DQ0
DDR0DQ3
DDR0CK_n
DDR0DQ10
DDR0DQ31
DDR0DQS3
DDR0RAS_n
DDR0DQS1
DDR0CAS_n
DDR0DQ25
DDR0DQ22
DDR0DQ6
DDR0DQ19
DDR0DQ21
DDR0DQ28
DDR0DQ23
DDR0DQ8
DDR0DQ9
DDR0DQ4
DDR0DQS2
DDR0DQ15
DDR0DQS0
DDR0RAS_n
DDR0CAS_n
DDR0DQ13
DDR0WE_n
DDR0A[0:12]
DDR0DM1
DDR0DQS3DDR0DQS2DDR0DQS1DDR0DQS0
DDR0DM3DDR0DM2
DDR0DM0
DDR0WE_n
DDR0CK
DDR0DQ11
DDR0CAS_n
DDR0CKE
DDR0BS0
DDR0DM1
DDR0DQ7
DDR0DQ14
DDR0DM0
DDR0DQ1
DDR0DQ9
DDR0A6
DDR0A11
DDR0A2
DDR0A0
DDR0A2
DDR0A5
DDR0A0
DDR0A9
DDR0A9
DDR0A12
DDR0A12
DDR0A8
DDR0A0
DDR0A7
DDR0A1
DDR0A5
DDR0A9
DDR0A4
DDR0A4
DDR0A8
DDR0A11
DDR0A11DDR0A10
DDR0A4
DDR0A1
DDR0A10
DDR0A3
DDR0A7
DDR0A10
DDR0A2
DDR0A7
DDR0A6
DDR0A1
DDR0A3
DDR0A3
DDR0A12
DDR0A8
DDR0A5
DDR0A6
+2.5V
VREF
RP6C 15x43 6
RP18C 15x436
RP15A 15x418
RP14A15x4 18
RP19C 15x436
RP12D 15x445
RP19D 15x445
RP9C 15x43 6
RP10C15x4 36
DDR SDRAM
U4A
K4H561638F-UC(L)/B3
293031323536373839402841 2
4578101113
5456575960626365
4546
2444
23222147
2627
16
20 51
42
A0A1A2A3A4A5A6A7A8A9A10A11 DQ0
DQ1DQ2DQ3DQ4DQ5DQ6DQ7
DQ8DQ9
DQ10DQ11DQ12DQ13DQ14DQ15
CKCK
CSCKE
RASCASWEUDM
BA0BA1
LDQS
LDM UDQS
RES(A12)
RP17A 15x41 8
RP13A15x4 18
RP9D 15x44 5
RP8A 15x41 8RP19A 15x418
RP15B 15x427
DDR SDRAM
U3A
K4H561638F-UC(L)/B3
293031323536373839402841 2
4578101113
5456575960626365
4546
2444
23222147
2627
16
20 51
42
A0A1A2A3A4A5A6A7A8A9A10A11 DQ0
DQ1DQ2DQ3DQ4DQ5DQ6DQ7
DQ8DQ9
DQ10DQ11DQ12DQ13DQ14DQ15
CKCK
CSCKE
RASCASWEUDM
BA0BA1
LDQS
LDM UDQS
RES(A12)
RP13C 15x43 6
RP20A 15x418
RP11C 15x43 6
RP17B15x4 27
RP17D 15x44 5
C4
0.1uF
RP12A 15x41 8
RP10A 15x41 8RP11B 15x42 7
RP18A 15x41 8
RP21B 15x427
RP7B 15x42 7
RP7A 15x418
RP16C 15x43 6
DDR SDRAM 0ZR391055
U1C
ZR391055SH
AD25AD26W23
AC24AE25W26V22U23
AB26W25Y21T24
N23P25P26P24P23T26R25R26
U25T25R23V26U26T23U24V25
Y26W24Y25V24Y24V23AA25AA26
AA24Y23AB25W22AC26AC25AB24AA23
Y22
AF25AC22AD22
AD24AB20AE24
AC23
AD23AA22
AA21
R24
AB22AB23
AB21AE26AC21AF26
S0ADR0S0ADR1S0ADR2S0ADR3S0ADR4S0ADR5S0ADR6S0ADR7
S0ADR8S0ADR9S0ADR10S0ADR11
S0DATA0S0DATA1S0DATA2S0DATA3S0DATA4S0DATA5S0DATA6S0DATA7
S0DATA8S0DATA9
S0DATA10S0DATA11S0DATA12S0DATA13S0DATA14S0DATA15
S0DATA16S0DATA17S0DATA18S0DATA19S0DATA20S0DATA21S0DATA22S0DATA23
S0DATA24S0DATA25S0DATA26S0DATA27S0DATA28S0DATA29S0DATA30S0DATA31
S0DQS3
S0DQS0S0DQS1S0DQS2
S0RAS_nS0CAS_nS0WE_n
S0CLK
S0BS0_nS0BS1_n
S0VREF
S0ADR12
S0CLK_nS0CKE_n
S0DQM0S0DQM1S0DQM2S0DQM3
RP19B 15x42 7
RP14C 15x436
C3
0.1uF
RP6D 15x44 5
RP21A 15x418
RP13B 15x42 7
RP18D 15x44 5
RP15C 15x436
RP14D15x4 45
RP6A 15x41 8
RP18B15x4 27
RP10B 15x427
RP20D 15x445
RP8C 15x43 6
RP9A 15x41 8
RP17C15x4 36
RP16D 15x44 5
RP8D 15x44 5
RP9B 15x42 7
RP12C 15x43 6
RP11D 15x44 5
RP14B15x4 27
RP10D 15x44 5
RP21D 15x445
RP7D 15x445
RP11A 15x41 8
RP20C 15x436
RP7C 15x43 6
RP8B 15x42 7
RP13D 15x445
RP21C 15x436
RP6B 15x42 7
RP12B 15x42 7RP20B 15x427
67
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Tuner / Demodulator
* Do notinstall.
Phobos
add metal shield for Tuner and de-modulater
L45 use Taiyo Yuden P/NLK16081R8K-T1.8uH Inductor 1206/0805SMT
D2
B
4 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
I2CDATA0I2CCLK0
+5VT1
SIF
+5VT1
TU_DATA0TU_DATA1TU_DATA2TU_DATA3TU_DATA4TU_DATA5TU_DATA6TU_DATA7
IF_AGC
IF_AGC
SIF
TU_SDATU_SCK
+5VT2
+5VT2
I2CDATA0I2CCLK0
TU_SCKTU_SDA
SIFI2CDATA0I2CCLK0
TU_CLK
SCLKLRCLK
TU_VALID
TU_ADATA
TU_DATA[0:7]
TU_FRAME
HW_RST_n
TU_CVBS
SIF
5VSB
5VSB
+3.3V5VSB
+3.3V
E3
47uF/16V
12
C4520.01uF
R379 47
C4590.1uF
C4501000pF
L41 BLM18AG601
R38210K
L451.8uH
R383 47
R394100
C4530.01uF
C4580.1uF
R39668
C4550.01uF
R371 47
C4540.01uF
TP10
1
C4410.1uF
U45
uPC3217GV-E1
1
23
4
5
67
8Vcc
IN1IN2
VAGC
GND
OUT1OUT2
GND
L42 BLM18AG601
L441uH
R38147K
C44622pF
E4
47uF/16V
12
R372 47
R4 0
R3862K
R391680
C45618pF
ORENDemodulator
U9A
Cascade-2
9796
9493
3639404143444849
29
28
4101421252731384247
32
82
34
2426505152545657
66
6564
63
1112
8990
1001
5859
2019161813
61
8079
7172
6768
AIN1_PAIN1_N
AIN2_PAIN2_N
D_OUT0D_OUT1D_OUT2D_OUT3D_OUT4D_OUT5D_OUT6D_OUT7
D_VALID
D_CLK
D_IN0D_IN1D_IN2D_IN3D_IN4D_IN5D_IN6D_IN7D_IN8D_IN9
D_FAIL
SCAN_MODESCAN_EN
D_SOP
STAT0STAT1STAT2STAT3STAT4STAT5STAT6STAT7
AU_CLK
AU_SDAU_MCLK
AU_WS
IF_AGCRF_AGC
AIN_OOB_PAIN_OOB_N
PARAM0PARAM1PARAM2PARAM3
SDA_I2CSCL_I2CTU_SDATU_SCLI2C_ADDR
RST
XTIXTO
LO_OUTPLO_OUTN
CRXDRX
R38710K
R370 47
C437150pF
C4510.1uF
C4601000pF
Y325MHz
C4430.01uF
C4421000pF
C44722pF
C445 0.1uF
L38 BLM21A601F
R378100
R377 47
C4350.01uF
C4380.01uF
C4611000pF
C4390.1uF
R36747
R375 47
R368 47
C7560pF
+C510uF
R37447
C4440.01uF
L39220nH
L43
BLM18AG601
Q1BFR93A
IFFilter
SF1X6941D
1
2
3
4
5
R380 47
R384 47
R376 47
R369 47
C4481pF_NS
R418 10K
C60.1uF
R10 0
TU1
DTT761113141516
1 2 965 73 10 11 124 8
GNDGNDGNDGND
RF
AGC
AGC
out
AUD
IO
SCL
SDA
IF o
ut
+5V
CVB
S
FM IF
SIF
VT +5V
R3921M
R3883.9K_1%
C4490.1uF
L37 BLM21A601F
R39368
L40BLM18AG601
R3952K
C4400.1uF
C45718pF
C43647pF
R385 47
R3902K
R373 47
68
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Audio SourceSelection:AUD_SEL A/B/C - 0/0/0 = BOARD AV1AUDIOAUD_SEL A/B/C - 1/0/0 = FRONT PANELAV2 AUDIOAUD_SEL A/B/C - 0/1/0 = YPbPR1AUDIOAUD_SEL A/B/C - 1/1/0 = YPbPR2AUDIOAUD_SEL A/B/C - 0/0/1 = VGA AUDIOAUD_SEL A/B/C - 1/0/1 = DVI AUDIO
Phobos
L
L
YPrPb1 AUDIOINYPrPb2 AUDIOIN
R
AV1IN
Bypass for AudioADC
R
L
DVI AUDIOIN
VIDEO/AUDIO IN
YELLOW
WHITE
RED R
R
R
L
L
FR
ON
T P
AN
EL
IN
VGA AUDIOIN
3D COMB FILTERCON
MOUNT HOLE FOR 3D
side AV Auto-detect
D2
B
5 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
CVBS_IN_2CVBS_IN_2CVBS_IN_2
AV-AUDIO-R
VAVccVAVccVAVccVDVcc
AV-AUDIO-L
AUD_SEL_C
CVBS_IN_1
MCLKVAVcc
VDVcc
AUD_SEL_C
AUD_SEL_AAUD_SEL_BAUD_SEL_B
AUD_SEL_AAUD_SEL_B
PC-R
PC-L
DVI-R
HD2-LHD1-L
HD2-RHD1-R
I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0
SW-C-IN
I2CCLK0I2CCLK0
Y-IN
3D-C
SW-Y-IN
C-IN
3D-Y
AV-IN-L
AV-IN-R
CVBS_IN_2CVBS_IN_2CVBS_IN_2CVBS_IN_2CVBS_IN_2CVBS_IN_2CVBS_IN_2CVBS_IN_2CVBS_IN_2CVBS_IN_2CVBS_IN_2CVBS_IN_2
FRONT_Y
FRONT_C
SML
SMR
FRONT-AV-SEL
FRONT-AV-SEL
CVBS_IN_2
FRONT_Y
CVBS_IN_1
FRONT_C
AUX_ADATA
SCLKMCLK
LRCLKSLEEP_MODE_n
AUD_SEL_A
AUD_SEL_CAUD_SEL_B
AV-IN-L
AV-IN-R
C-IN
Y-IN
I2CCLK0I2CDATA0
SW-C-IN
SW-Y-IN
FRONT-AV-SEL
5V
5V
5V
+3.3V
+3.3V
9V 9V5V 5V
5V 5V
+3.3V
C450.1uF
R39
947
k
C180
100pF
L11 120 ohm
C410.1uF
J8
33P8022 14B
1234567891011121314
C55
0.00
1uF
R9747k
R279
47k
D5
5V10
PE
R11320K
C97
0.00
1uF
C10
30.
001u
F
J30
33P3278 10
12345678910
C20
2200pF
C176
100pF
C25 1.0uF
L20 120 ohm
R122 510
R1113.3K_NS
J41
88P 302 6C
12435
C17 1.0uF
Z61
5V10
PE
R118 10K
D44
5V10
PER109 10K
C22
2200pF
D3
5V10
PE
C15
30.
001u
F
R62
47k
L17 120 ohm
J7
88P7810 4S
5
6
12
4
3
C23 1.0uF
C27 1.0uF
C10
00.
001u
F
D4
5V10
PE
C175
100pF
PAD5Mount_HOLE
11
R61
47k
D24
5V10
PE
R414 100
U6
74HC4051
123456789
10111213141516 A4
A6A
A7A5
EVEEGNDS2
S1S0A3A0A1A2VCC
D6
5V10
PE
C40
1.0uF
C15
10.
001u
F
L18 120 ohm
L28 120 ohm
D2
5V10
PE
C91
0.00
1uF
R9947k
PAD6Mount_HOLE
11
D36
5V10
PE
C34 1.0uF
C460.1uF
C28 1.0uF
C26 1.0uF
C19 1.0uF
R9647k
R10047k
C35 1.0uF
R108 10
Z62
5V10
PE
C240.1uF
J31
88P 302 6C
12435
C57
0.00
1uF
A/D Audio
U13
CS5340_NS
116
278
1012
93
11
6
145
4
15
13
M0M1
MCLKSCLKLRCK
AINLAINR
RSTVL
VQ
VD
RGNDGND
SDOUT
FILT
VA
C15
20.
001u
F
C31 1.0uF
C58
0.00
1uF
R121 510
C39
0.1uF
J1B
88P78106S
23
9
56
8
D7
5V10
PE
L9 120 ohm
R92
47k
C630.1uF
+C4710uF
L12 120 ohm
C38
1.0uF
C54
0.00
1uF
U5
74HC4051
123456789
10111213141516 A4
A6A
A7A5
EVEEGNDS2
S1S0A3A0A1A2VCC
L27 120 ohm
C98
0.00
1uF
C18
1.0uF
R107 10
R39
847
k
R94
47k
R280
47k
C59
0.00
1uF
C53
0.00
1uF
R412 100
C21
1.0uF
C189
100pF
C360.1uF
C56
0.00
1uF
C620.1uF
C9 1.0uF
R397 10K C370.1uF
L19 120 ohm
C14
40.
001u
F R406 10K
C182
100pF
C15
40.
001u
F
C14
30.
001u
F
D8
5V10
PE
C61
0.00
1uF
C99
0.00
1uF
L14 120 ohm
R112
3.3K_NS
R110 10K
R91 10K
C10
20.
001u
FC10 1.0uF
D1
5V10
PER11420K
L10 120 ohm
69
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Phobos
RGB4:4:4
HDMI I/F
HD_SYNC_SEL: S=0 : A=B1PORT S-1 : A=B2PORT
卧式DVI插座
卧式HDMI插座
D2
B
6 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
HDMI_SCL
HDMI_VLDHDMI_VSYNCHDMI_HSYNC
HDMI_CLK
HDMI_SDA
HDMI_VLDHD_VSYNCHD_HSYNC
HDMI_CLK
HW_RST_n
HDMI_+5V
HDMI_CEC
CBL_5V
HDMI_SCLHDMI_SDA
RXDCpRXDCm
RXD0mRXD0pRXD1mRXD1pRXD2mRXD2p
CBL_5V
HDMI_INT
HDMI_HSYNC
HD_SYNC_SEL
HDMI_VSYNCVGA_HSYNC
VGA_VSYNC
HD_HSYNCHD_VSYNC
I2CCLK1I2CDATA1
HDMA_SCDT
HDMI_CEC
CBL_5V HDMI_+5V
HDMI_SCLHDMI_SDA
DVI5VDVI5VDVI5VDVI5V
RXD1pRXD1m
RXD2mRXD2p
RXD0mRXD0p
RXDCpRXDCm
HDMI_LRCLKHDMI_ADATA
HDMI_SCLK
HDMI_VSYNC
I2CDATA1
HW_RST_nHDMI_INT
I2CCLK1
VGA_HSYNC
VGA_VSYNC
HD_SYNC_SEL
HDMA_SCDT
CEC
HDMI_SCLKHDMI_LRCLKHDMI_ADATA
HDMI_ACLK
+3.3V +3.3V
+5V
+5V+5V
+3.3V
+5V
+3.3V
+3.3V
+3.3V +5V
+3.3V
L49ACM2012D-900-2P12 3
4
RP25D 22x44 5
RP5C 22x43 6
RP22D 22x44 5
C46318pF
U68
NDC7002N
12
34
6
5
RP26A 22x41 8
RP5D 22x44 5
R5491M
L46ACM2012D-900-2P12 3
4
R402 4.7K
RP23A 22x41 8
RP26B 22x42 7
D47
5V10
PE
R4011K
CN16
DVI-D Connector
31
12345678
91011121314
16
1718192021222324
252627282930
32
15
SHELL1
DATA2-DATA2+SHLD24DATA4-DATA4+
DDCCDDCD
VSYNC
DATA1-DATA1+SHLD13DATA3-DATA3+
+5V
PLUG_D
DATA0-DATA0+SHLD05DATA5-DATA5+SHLDCK
CLK+CLK-
REDGREEN
BLUEHSYNC
AGNDAGND
SHELL2
GND
RP23C 22x43 6
RP26C 22x43 6
R403 4.7K
RP23B 22x42 7R411 10
U108
24LC21A
7
6
5
8
123
4
VCLK
SCL
SDA
VCC
NCNCNC
GND
D118BAV99L
L47ACM2012D-900-2P12 3
4
R40410K
RP26D 22x44 5
RP23D 22x44 5
R413 10
RP27A 22x41 8
RP24A 22x41 8
R415 10
R40510K
D10
5V10
PE
C4640.1uF
U47
SN74CBT3257
4356
2
7
9
12
11101413
115
168
1A1B22B12B2
1B1
2A
3A
4A
3B13B24B14B2
SOE
VCCGND
R43710K
RP27B 22x42 7
HD
MI
Connector
Type A
.
CN12
HDMI_CONN
12345678910111213141516171819
2021
2322
D2+GND
D2-D1+
GNDD1-D0+
GNDD0-
CK+GNDCK-
CECNC
SCLSDAGND+5V
HPD
ShldShld
ShldShld
RP24C 22x43 6
D119BAV99L
R199 0
R417 10
D45BAV70E
1
23
RP27C 22x43 6
RP24B 22x42 7
D11
5V10
PE
R438 10K
C4300.1uF
ESD
GND REF
D40SRV05-4
12
3 45
6
R419 10
J10
33P3278 3
123
RP27D 22x44 5
R57810K
RP24D 22x44 5
R207 0
U1524LC02B
12
3
4
56
7
8
A0A1
A2
GND
SDASCL
WP
Vcc
C467
0.1uF
HDMIRECEIVER
U10A
SiI9011CLU
124
123
122
121
117
116
115
114
111
110
109
108
105
104
103
102
101
100
99
96
95
94
93
92
35
34
33
32
29
28
27
26
23
22
21
20
17
16
15
14
11
10
9
8
5
4
3
2
127
1281
119
5150
5554
5958
6362
8584
797675747372717067
9189
4241
4039
90
38
44
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
QE8
QE9
QE10
QE11
QE12
QE13
QE14
QE15
QE16
QE17
QE18
QE19
QE20
QE21
QE22
QE23
QO0
QO1
QO2
QO3
QO4
QO5
QO6
QO7
QO8
QO9
QO10
QO11
QO12
QO13
QO14
QO15
QO16
QO17
QO18
QO19
QO20
QO21
QO22
QO23
DE
HSYNCVSYNC
ODCK
RXC+RXC-
RX0+RX0-
RX1+RX1-
RX2+RX2-
XTALINXTALOUT
MCLKSCKWSSD0SD1SD2SD3SPDIFMUTE
INTRSET
DSCLDSDA
CSCLCSDA
SCDT
CI2CA
PWR5V
Pix In (Green)
Pix In (Red)
Pix In (Blue)
ADV7400(DVI In)
0
0
0
7
7
7
U7B
ADV7400A
83848788959697
100
12
13
202134454344
14242930313233
35
868579
P40P39P38P37P36P35P34P33
P32P31
P29
P11P10P21P20P1P0
P28P27P26P25P24P23P22
DCLKIN
HS_INVS_INDE
RP22A 22x41 8
RP25A 22x41 8
L48ACM2012D-900-2P12 3
4R421 10
C46218pF
R208
4.7K
R5760_NS
D9
5V10
PE
D120
BAV70L
ESD
GND REF
D41SRV05-4
12
3 45
6
R442 22
R446 2.2K
RP22B 22x42 7
RP25B 22x42 7
RP5A 22x41 8
Y528.322MHz
U46
NDC7002N
12
34
6
5
R423 10
R400 10
R209
4.7K
RP22C 22x43 6
RP25C 22x43 6
RP5B 22x42 7
R425 10
R445 2.2K
R57710K
70
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Phobos
YC/CVBS AUTODETECTE ANDSWITCH:SDM_SEL[1:0] = 11 CVBS = AIN11 Y = AIN11 , C =AIN12
GREEN
BLUE
RED
RED
GREEN
BLUE
YPbPr1-TOP
Y
C
Analog Video Inputs
R
G
B
Pr
Y
Pb
HD_SEL --> LOW:A,HIGH:B LOW = 0 : YPbPr1 Input HIGH = 1 : YPbPr2 Input
YC
ADDID:0X06
D27 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
VGA_HSYNC
VGA_VSYNC
VGA_+5V
VD_27M_CLK
VGA_SDA
VGA_SCL
DDC_CLK
DDC_DATA
VGA_+5V
VGA_SCLVGA_SDA
HD_SELHD_SELHD_SELHD_SELHD_SELHD_SELHD_SELHD_SELHD_SELHD_SEL
TU_CVBSTU_CVBSTU_CVBS
CVBS_IN_2
CVBS_IN_1
FRONT_Y
FRONT_C
I2CCLK0I2CCLK0I2CCLK0I2CCLK0I2CCLK0I2CCLK0I2CCLK0I2CCLK0I2CCLK0I2CCLK0I2CCLK0I2CCLK0
I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0I2CDATA0
SW-Y-INSW-Y-IN
SW-C-INSW-C-IN C1
Y-IN
C-IN
Y-IN
C-IN
SW-C-INSW-C-INSW-C-INSW-C-INSW-C-INSW-C-INSW-C-INSW-C-IN
TU_CVBSTU_CVBSTU_CVBSTU_CVBSTU_CVBSTU_CVBSTU_CVBSTU_CVBSTU_CVBSTU_CVBSTU_CVBSTU_CVBSTU_CVBSTU_CVBS
Video_Input_Select
Y1Y1Y1Y1
AVOUT1AVOUT1
VGA_HSYNC
VGA_VSYNC
DDC_CLK
DDC_DATA
VD_27M_CLK
HD_SEL
TU_CVBS
Video_Input_Select
CVBS_IN_1
FRONT_Y
FRONT_C
CVBS_IN_2
I2CCLK0
I2CDATA0
SW-Y-IN
SW-C-INY-IN
C-IN
AVOUT1
+5V
DEC_PVcc
+3.3V
+5V
+3.3V
D8V
+5V
+5V
+5V
R70375_1%
R11
710
K_N
S
C469 0.1uF
+C47210uF
L53 3.3UHC474 0.1uF
Q9SST3904 BCE
R298 100k_NS
R224
4.7K
L5 120 ohm
R297 100k_NS
R1444.7K
R450
75_1%
C30 0.1uF
D20
5V10
PE
D37
5V10
PE
D14
5V10
PE
C485 0.1uF
C478 0.1uF
C89
0.00
1uF
+C48810uF
C4760.1uF
R25 4.7K
C64
0.00
1uF
R105
75_1%
U504
PI5V330
25
1114
36
1013 8
1615
1
47912
A1A2A3A4
B1B2B3B4 GND
VCCOEA/B
Y1Y2Y3Y4
R300 100k_NS
R129 75
R106
75_1%
R10275_1%
R2214.7K
L55 3.3UH
D21
5V10
PE
D38
5V10
PE
R103
75_1%
C465.082uF
C4810.1uF
+C137 22uF/16V
D25
5V10
PE
R45475_1%
L51 3.3UH
D22
5V10
PE
CN15
88P78106S
5
6
12
4
3
78
9
C168
150pF
C491
10pF
C4800.01uF
L58 820nH
R407 100
D26
5V10
PE
C4870.1uF
+
C135 22uF/16V
R408 100
R1432.7K
U2924LC02B
12
3
4
56
7
8
A0A1
A2
GND
SDASCL
WP
Vcc
R4521.33K
C504
22pF
R119 75
C83
0.00
1uF
C4860.01uF
D39
5V10
PE
D18
5V10
PE
D23
5V10
PE
C505
22pF
R45375_1%
D13
5V10
PE
C325
47uF/16V
12
R130 75
C33 0.1uF
C47510uF
L56 820nH
D19
5V10
PE
R300_NS
R104
75_1%_NS
R153
820
R389 10K
Q7SST3904 BCE
+C138 22uF/16V
C167
0.01uF
L59 820nH
R154
820
CN1S-VIDEO
12
34
L50 3.3UH
CN13
D-SUB 15
8
15
7
14
6
13
5
4
11
3
10
2
9
1
12
Q8SST3904 BCE
ADV7400(Analog In)
U7A
ADV7400A
52
54
56
58
72
74
76
77
53
55
57
71
73
75
69
68
62
61
65
64
67
38
37
46SOG
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
SOY
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
CAPC2
CAPC1
CAPY2
CAPY1
CML
REFOUT
BAISIN
XTAL
XTAL1
ELPH
L57 820nH
L54 3.3UH
C479 1000pF
C5090.1uF
C88
0.00
1uF
+C139 22uF/16V
+C140 22uF/16V
D15
5V10
PE
C477 0.1uF
U14
TEA6415C
2
3
4
5
6
7
8
9
11
1
19
18
17
16
15
14
13
12
20
10
C29 0.1uF
R98 10K
R1422.7K
R223150
R3110K
R45575_1%
+
C136 22uF/16V
C84
0.00
1uF
L1 120 ohm
R70275_1%
D16
5V10
PE
R22210K_NS
C468 1000pF
C4830.1uF
L2 120 ohm
C4660.01uF
R225 75
L52 3.3UH
D46BAV70E
1
23
R1494.7K
R120 75
R449
75_1%
C470 0.1uF
C490
10pF
L4 120 ohm
C4730.1uF
C32 0.1uF
L3 120 ohm
+C142 22uF/16V
R1484.7K
R70175_1%
R448
75_1%
D17
5V10
PE
C471 0.1uF
+C48210uF
C4840.1uF
R451 1.69K_1%
R296 100k_NS
R1454.7K
R11
610
K_N
S
U30NDC7002N
12
34
6
5
R26 4.7K
71
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Decoder /Transport I/FPhobos
D2
B
8 22Monday, March 28, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
PIC_HSPIC_CLK
PIX_VS
TU_DATA0TU_DATA1TU_DATA2TU_DATA3TU_DATA4TU_DATA5TU_DATA6TU_DATA7
TU_DATA[0:7]
T3_DATA0T3_DATA1
T3_DATA3
T3_CLK
T3_DATA4
T3_DATA2
T3_FRAMET3_VALID
PIX_C7
PIX_C1
T3_DATA7
PIX_C0
PIX_C5
T3_DATA[0:7]
PIX_C4PIX_C3
PIX_C6
PIX_C2
T3_DATA6T3_DATA5
PIC_HSPIX_VS
PIX_C0PIX_C1
PIX_C5
PIX_C3PIX_C4
PIX_C2
PIX_C7PIX_C6
PIX_C[0:7]
PIC_CLK
PIX_Y0PIX_Y1
PIX_Y5
PIX_Y3PIX_Y4
PIX_Y2
PIX_Y7PIX_Y6
TU_VALIDTU_FRAMETU_CLK
TU_DATA[0:7]
T3_CLKT3_FRAMET3_VALID
T3_DATA[0:7]
I2CCLK1I2CDATA1
HW_RST_n
PIX_Y[0:7]
FSC_LOCK
AFVVLD1
AIN_INT_n
R476 22
RP30D 22x44 5
RP28D 22x44 5
R475 22
RP31A 22x41 8
RP29A 22x41 8
RP31B 22x42 7
RP29B 22x42 7
(Digital Out)ADV7400
Y OutC Out
7
7
0
0
U7C
ADV7400A
2223252627284142
91929394
789
10
36
499
15
98
8182
1916
78
80
3
P9P8P7P6P5P4P3P2
P19P18P17P16P15P14P13P12
LLC1
HSVS
FSC_LOCK
FIELD
SDASCLK
SDA2SCLK2
RESET
ALSB
INTRQ
RP31C 22x43 6
RP29C 22x43 6
R115 10K
ZR391055TRANSPORT I/O
U1F
ZR391055SH
C16D15A18D16B16C18C20A19
A20D18
C19
A21
D19B23
C7A4A5
A16A17E19D20B22
A15
D14D13
E9C8B6A6D7D9A8A7
B21B20C17B17C15C14B8B7
B5D8
A22
T1DATA0T1DATA1T1DATA2T1DATA3T1DATA4T1DATA5T1DATA6T1DATA7
T1FRAMET1CLK
T1DVALID
T0CLK
T0DVALIDT0FRAME
T0DATA0T0DATA1T0DATA2T0DATA3T0DATA4T0DATA5T0DATA6T0DATA7
T2CLK
T2DVALIDT2FRAME
T2DATA0T2DATA1T2DATA2T2DATA3T2DATA4T2DATA5T2DATA6T2DATA7
T3DATA0T3DATA1T3DATA2T3DATA3T3DATA4T3DATA5T3DATA6T3DATA7
T3FRAMET3VALID
T3CLK
RP31D 22x44 5
RP29D 22x44 5
R472 22
RP30A 22x41 8
RP28A 22x41 8
R473 22
RP30C 22x43 6
RP28B 22x42 7
R474 22
RP30B 22x42 7
RP28C 22x43 6
72
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Phobos
1a
Backlight connector.
GPIO 1GPIO 0
Video Prime / LVDS D2
B
9 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
TXECmTXECp
LCD_ON
LCD_ON
MAIN_YMAIN_Pr
MAIN_Pb
MAIN_Pr
MAIN_PbMAIN_Y
I2CCLK1I2CDATA1
VSYNCHSYNC
NAND_GPIO1_n
DDC_DATADDC_CLK
DDC_CLKDDC_DATA
TXE0mTXE0mTXE0mTXE0m
TXE3pTXE3pTXE3pTXE3p
TXE1mTXE1mTXE1p
TXE2pTXE2p
TXE3mTXE3m
TXE0pTXE0p
TXE2m
TXE0mTXE0p
TXE1mTXE1p
TXE2mTXE2p
TXECmTXECp
TXE3pTXE3m
HSYNCVSYNCDED-CLK
I2CCLK1I2CDATA1
LVDS-ONLVDS-ONLVDS-ONLVDS-ON
HW_RST_n
TXECmTXECp
MAIN_Pr
MAIN_PbMAIN_Y
I2CDATA1I2CCLK1
NAND_GPIO1_n
DDC_CLKDDC_DATA
LCD_DIMM
VREF_DAC
MAIN_VSYNCMAIN_HSYNC
HW_RST_n
+3.3V
+3.3V
+3.3V
+3.3V
+12V
+2.5V
+3.3V
+2.5V
R136 22
R456 0_NS
R435 10K
RP33C 22x436
D49LM4041DEM3-12
LM4041DEM3-1.2
1
3
2
R528100K_NS
LVDS DRIVER
U8A
DS90C2501
171615141312
98
7654
323130292827262524232221
213
1011
61
7271
98
18
115116117
55
53
51
47
45
43
41
39
56
54
52
48
46
44
42
40
4950
3738
35
34
36
57585960
6968
646362
114
D0D1D2D3D4D5D6D7
D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22D23
HSYNCVSYNCDECLKINCLKIN
RST
I2CCLKI2CDATA
MSEN
REFCLK
A0A1A2
A0P
A1P
A2P
A3P
A4P
A5P
A6P
A7P
A0M
A1M
A2M
A3M
A4M
A5M
A6M
A7M
CLK1PCLK1M
CLK2PCLK2M
DUAL
COLOR
EDGE
ID0ID1ID2ID3
ENAVDDENABKL
GPIO1GPIO2GPIO3
PCLK_INV
R138 22
R458 0
RP33D 22x445
C162
0.1uF
R13310K
R137 22
J3233P3278 12
123456789101112
R457 0_NS
R1402K
R478 10K_NS
RP34A 22x418
R13410K
R480 0
R484 22
RP34C 22x436
R477 10K
R1392K
C660.1uF
RP34D 22x445
R485 22
R483 0
14.31818MHz
U11
CB3LV-3C-14.31818MHz
1
2 3
4OE
Vcc OUT
GND
C680.01uF
RP34B 22x427
RP32A 22x418
RP59D 22x445
R462 0_NS
R52710K_NS
RP32C 22x436
RP59B 22x427
R58310K
J6
33P8026 31
12345678910111213141516171819202122232425262728293031
C650.1uF
R141715_1%
J5
33P8026 31_NS
12345678910111213141516171819202122232425262728293031
R463 0_NS
RP32B 22x427
R460 0_NS
R459 0_NS
R482 10K
R525100K_NS
C671000pF
C690.01uF
RP33A 22x418
RP59C 22x436
+
C7010uF
R5266.2K
RP59A 22x418
RP32D 22x445
R461 0_NS
R584 0_NS
R479 0
R135 22
RP33B 22x427
R48110K
ZR391055PRIMARY VIDEO
U1J
ZR391055SH
F7F6C3B2A1B1F5E4
D3C2C1G5F4E3D2D1
D12
C13
A13
C12
A12A11B11
F3E2
G6
D4
D5E6E5
H5G4
PIXOUT0PIXOUT1PIXOUT2PIXOUT3PIXOUT4PIXOUT5PIXOUT6PIXOUT7
PIXOUT8PIXOUT9
PIXOUT10PIXOUT11PIXOUT12PIXOUT13PIXOUT14PIXOUT15
VREFIN0
VREFOUT0
COMP0
RSET0
ANALOG_RED_PRANALOG_GREEN_YANALOG_BLUE_PB
DDC0DDC1
OSDP
PCLK
HSYNCVSYNCDEVEN
AFHSIO_GPIO0AFVSIO_GPIO1
73
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Supply Bypass, Analog
GPIO185
Stuffing Options.Stuff for CRT only.
RGB / YPbPROUT
Y/C, COMPOUTs
Phobos
RED
L
AVOUT
R
Video Interface D2
B
10 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
MAIN_Pb
MAIN_Pr
MAIN_Y
PIX_Y3PIX_Y4
PIX_Y2
PIX_Y5
PIX_Y7PIX_Y6
PIX_Y0PIX_Y1
CVmix_SEL
AFVVLD1
AFVVLD1
AUX_Y
AUX_C
AV-L
AV-R
FMS_SEL
AVOUT1
CVmix_SEL
PIX_Y[0:7]
MAIN_Pr
MAIN_Y
MAIN_Pb
MAIN_VSYNCMAIN_HSYNC
AFVVLD1
VREF_DAC
FMS_SEL
AV-L
AV-R
AVOUT1
+3.3V
5V
+3.3V
+3.3V5V
+3.3V
L16 120 ohm
U48
FMS6419MS28_NS
1
23
45
67
8
910
11
12
1314
15
16
17
18
19
20
21
22
23
24
252627
28
INmux
Rin ARin B
Gin AGin B
Bin ABin B
CVmux
NC1NC2
Vssa
AUXin
CinYin
NC3
Vssyc
NC4
VCout
Cout
Vcco
Yout
Bout
Gout
Rout
VssVccaVssrgb
Fsel
+C495 220uF
D50
5V10
PE
E2 100uF/16V
C5010.01uF
R16175_NS
C95
0.00
1uFC101
1.0uF
C861000pF
R175 3.3KL15 120 ohm
D35
5V10
PE
R210 3.3K
D34
5V10
PE
R15175_NS
C4990.01uF
R95
47k
R17437.4_1%
R15675_NS
+C496 220uF
R101
47k
R16775_NS
R226 75
R15237.4_1%
+C497 220uF
J3533P3278 6
123456
R14737.4_1%
R16237.4_1%
R487 10K
+C50033uF/16V
R488 10K
+C49833uF/16V
R17375_NS
C93
0.00
1uF
R15737.4_1%
+C492 220uF
J3433P3278 10
123456789
10
C94
0.00
1uF
R585
0
L13 120 ohm
C850.1uF
R486 10K
+C493 220uF
C96
0.00
1uF
ZR391055AUX VIDEO OUT
U1K
ZR391055SH
D6B4E7E8C6A3B3C4
A2
C9
B9
A9
D11
C10
D10
B10
C5
AUXOUT0AUXOUT1AUXOUT2AUXOUT3AUXOUT4AUXOUT5AUXOUT6AUXOUT7
AUXVCLKO
AUXC
AUXY
AUXCVBS
VREFIN1
VREFOUT1
COMP1
RSET1
AUXOSDPR16937.4_1%
C90
0.00
1uF
R14675_NS
+C494 220uF
C870.01uF
R586
0_NS
J1A
88P78106S
13
9
46
7C921.0uF
R1681130_1%
74
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Phobos
00 ?Not Allowed01 ?ACLK fromVCxO10 ?ACLK fromHDMI11 ?NO Audio
Audio Interface
Supply Bypass, Audio
TSSOP10PLACETOPLAYER
SPDIF光纤发送
D2
B
11 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
AUD_L
AUDIO-R
+5V_AUDIO
SCLK
LRCLK
LRCLK
ACLK0
TU_ADATA
GEN_ACLK
HDMI_ACLK
HDMI_SCLKHDMI_LRCLK
SCLKLRCLK
MCLK
ACLK0ACLK1
HDMI_ADATA
SCLK
IEC958O
AUX_ADATAACLK1
+5V_AUDIO
AUDIO-L
AUD_R
ACLK_SEL1ACLK_SEL0
ADATA
IEC958O
ACLK_SEL0
SCLK
LRCLK
TU_ADATA
ACLK_SEL1
GEN_ACLK
HDMI_ACLK
HDMI_SCLKHDMI_LRCLK
HDMI_ADATA
MCLK
AUDIO-R
AUDIO-LAUX_ADATA
+3.3V
+3.3V
+5V
+3.3V
+5V
R182 560
R17810K
R172 22
U16
CS4344
12345 6
78910SDIN
DEM/SCLKLRCKMCLKVQ FILT+
AOUTLGND
VAAOUTR
IR Transmitter
U17
GP1FA514TZ
1
2
3
Nin
Vcc
GND
ZR391055Audio
U1L
ZR391055SH
H2
J2
J4
H3
G2
J5
G1
F2
F1
G3
BCLK
LRCLK
ADATAO0
ADATAO1
ADATAO2
IEC958
ACLK
ADATAI0
ADATAI1
ADATAI2
C1140.1uF
R184 560
+E505
10uF
R299 22
R171 10K
R186267K
C1050.1uF
C1110.1uF
C502
0.1uF
C1040.1uF
R179267K
R181 22
+E506
3.3uF/16V
C1120.1uF
R18710K
R2600
R183 22
R2610
R185 22
+C11047uF/16V
R18010K
U52
SN74LVTH244
2468
11131517
119
181614129753
2010
1A11A21A31A42A12A22A32A4
OE1OE2
1Y11Y21Y31Y42Y12Y22Y32Y4
VccGND
+C10810uF
C134
0.1uF_NS
L62
BLM18AG601
+
C10710uF
C503
0.1uF
C1091500pF+E504
3.3uF/16V
R295100k
R170 10K
R193 22
C1061500pF
R17710K
R294100k
R17610K
C1130.1uF
75
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Phobos
SIO / VCXO /Reset
5678
1,0,01,0,11,1,01,1,1
18.432MHz16.384MHz22.5792MHz24.576MHz
MAIN Time Base
4321
ACLKCLK Sel [1:0]
16.9344MHz
11.2896MHz
Format
12.288MHz
8.192MHz
0,1,1
Audio Clock Frequency Selection, Main Timebase
0,1,00,0,10,0,0
Note: Clear power andground planes under xtalsand traces to VCXOs.Front Panel Control Connector
TO KEY PAD
GPIO184
GPIO166GPIO167GPIO168GPIO169
FOR MSP3455
CH-CH+
ENTER
D2
B
12 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
I2CDATA0I2CCLK0
I2CCLK0
PWR-ONVS-ONUART_RX
KEY3
KEY6
RESET
UART_TX
I2CDATA1I2CCLK1
K-IR
HW_RST_n
K-IR
IRR
CH+
KEY3
KEY2
CH-
PWR_SW
KEY6
GEN_ACLK
ACS2
1055_27M_CLK
ACS0
VD_27M_CLK
PWM
TV_VIDEO
ACS1
MENU
LED-A
KEY2KEY3
K-IR
LED-B
KEY2
VOL-VOL+
KEY6KEY6
I2CDATA0
CH+CH-VOL+VOL-
HW_RST_n
1055_27M_CLK
SPI_SEL
UART_TXUART_RX
LED6
I2CCLK0I2CDATA0
I2CCLK1I2CDATA1
SPI_MOSPI_MISPI_CLK
IRRIRB
PWM
MENU
I2CCLK1
I2CDATA1
I2CCLK0
I2CDATA0
RESETn
LED-2LED-2LED-2LED-2LED-2LED-2LED-2LED-2LED-2LED-2LED-2LED-2LED-2LED-2LED-2LED-2
LED-B
LED-A
LED-1
LED6
VS-ON
I2CCLK0I2CDATA0
I2CCLK1I2CDATA1
HW_RST_n
PWR_SW
GEN_ACLK
ACS2
VD_27M_CLK
ACS1ACS0
TV_VIDEO
PWR-ON
TAPSEL
LED3LED4LED5LED6
UART1_RXUART1_TX
WP_n
SPIEEPROM_WP_n
UART2_RXUART2_TX
TDOTDITCKTMS
TRST
RESETn
IRB
+5VSB
5V
+5VSB
5V
+3.3VSB+5VSB
+3.3V
+5VSB
+3.3V+3.3V
+3.3V
+3.3V
+3.3V
+3.3V +3.3VSB
C1204pF
R1946.2K
R191 10K
U515
P87LPC764BD
120191817161413
12
11
109
84
32
6
7
5 15
P0.0P0.1P0.2P0.3P0.4P0.5P0.6P0.7
P1.0/W
P1.1
SCL/P1.2SDA/P1.3
DSN/P1.4RST/P1.5
P1.6P1.7
X1/P2.1
X2/P2.0
VSS VDD
R410 100R489 220_NS
Y5044.000MHz
12
C41
80.
1uF
C41
90.
1uF
R202 10K
Y127MHz
ZR391055SIO Block
U1I
ZR391055SH
L1R3R2T1J1L3
P2N2
R1P1
M1J3
K5N1
N4
P3
P4
K2
M4H1K3
W1
W2Y1
V4U5
AC20AD21
AD20AF23
AF24
B15B18
L4L2T3
C21
AA1
B19
AE22
UART0_TXUART0_RX
UART0_RTS_nUART0_CTS_nUART0_DTR_nUART0_DSR_n
UART1_TXUART1_RX
UART2_TXUART2_RX
I2C0_CLKI2C0_DAT
I2C1_CLKI2C1_DAT
SPIMISO
SPISEL0
SPIMOSI
SPICLK
IRRIRB
RFR
GPIO3
NC1NC2
NC3NC4
TDOTDI_n
TMS_nTAPSEL
TCLK
PWMCLKIN
GPIO4GPIO5GPIO6
DEVRST_n
USBOC
GPIO7
TRST_n
C60118pF
R195 22+
C11510uF
R188 10K
R49
110
K
R19710K
C1214pF
C41
20.
1uF
J4233P3278 13
123456789
10111213
R42
810
K
R49
010
K
U514
74HCT4066
1
2
3
4
5
6
7 8
9
10
11
12
13
141Y
1Z
2Z
2Y
2E
3E
GND 3Y
3Z
4Z
4Y
4E
1E
Vcc
C60218pF
C41
30.
1uF
U516AP1117E33A
3
1
2
4
VI
GN
D
VO
TAB
C42
10.
1uF
R19810K
Q2
MMBT3906
VCX0U18
MK3722
12
2
1
5
1316
414
3
159
10
6711
8
27MHz
X1
X2
VIN
ACS0ACS1
VDDVDD
VDD
NCACS2
ACLK
GNDGNDGND
PDTS
C118
0.1uF
R42
910
KR
492
10K
R123 10K
C1160.01uF
L715
TI321611U121
TP2
1
C119
0.1uF
C41
40.
1uF
R196 22
R42
010
K
Q6
MMBT3906
SPI_FLASH
U19M25P05-A
1
234
5
678
CS
DoutWP
GND
Din
SCKHOLD
Vcc
C41
50.
1uF
R409 100
R34610K
R416 100R
427
10K
C41
70.
1uFR201
10K
R192 22
R49
410
K
R212 0
C41
60.
1uF
C117
0.01uF
R124 10K
R493180
C42
00.
1uF
R190 10K
R2001K
76
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
IDE / GPIOs Blocks
Note: Trace lengths for D[0:15] shouldbe within +/- .5" of the matched tracelengths for the IDE_RDY~ and IDE_IOR~signals. Line lengths should be lessthan 8".
Note: Termination resistors should belocated within .4" of the connector.
GPIO2
GPIO159GPIO163GPIO162GPIO160GPIO161
GPIO156
GPIO154
GPIO155GPIO12GPIO13GPIO157GPIO158
GPIO11GPIO14
NoteAll DATA/ADR pins have to be setup as OUTPUTcondition during boot-up.
Phobos
Reset Logic
To Page5
To Page5
D2
B
13 22Monday, March 28, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
IDE_HSCBL_n
IDE_D7
IDE_DASP_n
IDE_DASP_n
IDE_D10IDE_D5IDE_D9IDE_D6IDE_D8
IDE_D4
IDE_D12
IDE_D11IDE_D3
IDE_D15
IDE_D1
IDE_DRQ_n
IDE_D0IDE_D14
IDE_DACK_n
IDE_IOW_n
IDE_IOR_n
IDE_INTR
IDE_A2IDE_A0
IDE_A1
IDE_CS3_nIDE_CS1_n
IDE_RST_n
IDE_RDY_n
IDE_D13IDE_D2
HW_RST_n
HD_SYNC_SEL
FSC_LOCK
HDMI_INT
SPIEEPROM_WP_n
LAN_INT
Video_Input_Select
ACS0ACS1ACS2
AUD_SEL_AAUD_SEL_B
IDE_LED_n
IDE_HSCBL_n
AUD_SEL_C
AUD_DOWN
LED2
RST_SW
HW_RST_n
FRONT-AV-SEL
VREF
+2.5V
+3.3V
+3.3V
+5V
+3.3V
+3.3V
RP35A 22x41 8
ZR391055SMART CARDINTERFACES
U1H
ZR391055SH
V2
R4V1
U4
U3
V3
U1
M3
K4
N3
T2
K1
U2M2
T4SC0CLK
SC0DETSC0DATA
SC0CMDV
SC0AUX1
SC0RST
SC1CLK
SC1DET
SC1CMDV
SC1DATA
SC0AUX2
SC1RST
SC0CMDVPPSC1CMDVPP
NRSSCLK_GPIO2
R311 82
RP37C 22x43 6
Reset Ckt
U20
DS1233A
3
2
1
VCC
GND
/RESET
C1240.1uF
R21510K
RP35B 22x42 7
RP37B 22x42 7
RP35C 22x43 6
C122560pF
R316 10K
RP37D 22x44 5
R312 5.6K
RP35D 22x44 5
RP40A 22x41 8
RP39B 22x42 7
RP38A 22x41 8
R313 4.7K
2
43 44
TOP VIEW
2x22 2mm Header
1
CN3IDE_CONN44
123456789
1011121314151617181920212223242526272829303132333435363738394041424344
RESETGNDD7D8D6D9D5D10D4D11D3D12D2D13D1D14D0D15GNDKEYEDDMARQGNDIOWGNDDIORGNDIORDYCSELDMACKGNDINTRQreservedA1PDIAGA0A2CS1CS3DASPGND+5V+5VGNDreserved
D121BAV99L
R315 82
RP36A 22x41 8
RP40B 22x42 7
RP39A 22x41 8
R20410K
RP38B 22x42 7
RP36B 22x42 7
R314 82
RP40C 22x43 6
RP39C 22x43 6
R20310K
RP38C 22x43 6
RP36C 22x43 6
RP40D 22x44 5
RP39D 22x44 5
RP38D 22x44 5
DDR SDRAM 1ZR391055
U1B
ZR391055SH
E25H25D26G26F22G21J22E23
D24C24K26C23
F23D25G22F24E24G23H22C26
F25F26H23G24G25H24E26J23
H26J24J26J25K23K24K25L23
L26L25M26N26M25M23M24N24
E20
E22D22B26
C25E21A26
B24
N25L24
F21
A24
E18B25
D23D21A25C22
S1ADR0S1ADR1S1ADR2S1ADR3S1ADR4S1ADR5S1ADR6S1ADR7
S1ADR8S1ADR9
S1ADR10S1ADR11
S1DATA0S1DATA1S1DATA2S1DATA3S1DATA4S1DATA5S1DATA6S1DATA7
S1DATA8S1DATA9S1DATA10S1DATA11S1DATA12S1DATA13S1DATA14S1DATA15
S1DATA16S1DATA17S1DATA18S1DATA19S1DATA20S1DATA21S1DATA22S1DATA23
S1DATA24S1DATA25S1DATA26S1DATA27S1DATA28S1DATA29S1DATA30S1DATA31
S1DQS3
S1DQS0S1DQS1S1DQS2
S1RAS_nS1CAS_nS1WE_n
S1CLK
S1BS0_nS1BS1_n
S1VREF
S1ADR12
S1CLK_nS1CKE_n
S1DQM0S1DQM1S1DQM2S1DQM3
R310 22
RP36D 22x44 5
IDE INTERFACEZR391055
U1D
ZR391055SH
AD4
AD1
AE1
Y3
AA3
AA2
V5
AC1W4
AD2
Y4
AB2
AB5
W5
AC2
Y6
AB3
Y5
AB4
AF2
AA5
AF3
AA4
AD3AA6
AB6AC3
AE21
IDED0
IDED1
IDED2
IDED3
IDED4
IDED5
IDED6
IDED7IDED8
IDED9
IDED10
IDED11
IDED12
IDED13
IDED14
IDED15
IDEDRQ
IDEIOW_n
IDEIOR_n
IDEDACK_n
IDEINT
IDERDY
IDEA1
IDEA0IDEA2
IDECS3_nIDECS1_n
IDERST_n
C1230.1uF
RP37A 22x41 8
77
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Utility / JTAG Connectors
TRANSPORT 2
EJTAG
"Power LED"PWR / IDE LED"
Phobos
跳线2 X 7 跳线
D2
B
14 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
LED5
T3_DATA4
T3_DATA2
T3_DATA7T3_DATA6
T3_DATA0
T3_DATA3
T3_DATA5
LBUS_A[0:25]
LBUS_A0LBUS_A1LBUS_A2
LBUS_A4LBUS_A3
LBUS_A11
LBUS_A13LBUS_A14
LBUS_A19LBUS_A18
LBUS_A7
LBUS_A22
LBUS_A17
LBUS_A25
LBUS_A9
LBUS_A20
LBUS_A23
LBUS_A12
LBUS_A16
LBUS_A24
LBUS_A21
LBUS_A15
LBUS_A8
LBUS_A10
LBUS_A6LBUS_A5
T3_DATA[0:7]
T3_DATA1
RS232_R2
RS232_T2
LBUS_D[0:15]
LBUS_D3
LBUS_D14
LBUS_D10
LBUS_D4
LBUS_D15
LBUS_D0LBUS_D1
LBUS_D5
LBUS_D2
LBUS_D6
LBUS_D11
LBUS_D8
LBUS_D12
LBUS_D7
LBUS_D9
LBUS_D13
RS232_T2RS232_R2
MTXDMTXDMTXDMTXDMTXDMTXDMTXDMTXDMTXDMTXDMTXDMTXDMTXDMTXDMTXDMTXD
MRXDMRXDMRXDMRXDMRXDMRXD
LED5
LED3
LED5
LED2
LED4
LED6
T3_DATA[0:7]
LBUS_A[0:25]
TAPSEL
TRSTTDITDOTMSTCKHW_RST_n
T3_FRAMET3_VALID
T3_CLK
LBUS_D[0:15]
LAN_INT
LBUS_CS0_nLBUS_CS1_nLBUS_CS2_nLBUS_CS3_n
LBUS_RDY0
LBUS_AS_nLBUS_WRL_n
LBUS_RD_n
LBUS_WRH_n
LBUS_CS4_nLBUS_CS5_n
RST_SW
HW_RST_n
IDE_LED_n
UART1_RX
UART1_TX
UART2_RX
UART2_TX
PWR_SW+3.3V
+3.3V+3.3V
5VSB
+3.3V
+5V
+3.3V+3.3V
+12V
5VSB
CN14AMP 2-557000-5 _NS
123456789
1011121314151617181920212223242526272829303132333435363738394041424344454647484950
51525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100
J9
D-SUB9
594837261
232 XCVRU26
ST232
138
1110
1
3
4
52 6
129
147
16 15
R1INR2IN
T1INT2IN
C+
C1-
C2+
C2-V+ V-
R1OUTR2OUT
T1OUTT2OUT
VCC GND
R270 0
C2731.0uF
CN7
CON 2 X 7
1234567891011121314
D27
SSL-LX15IGC-RP-TR_NS
1
23
C2751.0uF
R26847K
J27
JMP_NS
1 2
R343 0
R34010KR34110K
C2741.0uF
RP411KX4
1 2 3 45678
C2761.0uF
R344 0
RP421KX4
1 2 3 45678
R3221K
D28
SSL-LX15YC-RP-TR_NS
1
2
3
R26933
R321220
R320220
78
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power and Ground 1
* Locate under ZR391055
* Locate under ZR391055
P11305CT-ND
* Locate under ZR391055
Note: Place 100pf caps within .6" of pin.
Note: Place 1000pf caps within 1.5" of pin.
Note: Place .01uF, .1uF, and 1uF caps within 2" of pin.
Phobos
* Locate under ZR391055
* Locate under ZR391055
D2
B
15 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
LCD_DIMM
+1.2V
+2.5V
+1.2V
+3.3V
+3.3V
+3.3V
D1.2V
+3.3V
+2.5V
+3.3V
+2.5V
1.2V
D1.2V
+1.2V
C1740.01uF
C1720.1uF
C1770.01uF
+ C159
33uF/16V
C1700.1uF
C1480.1uF
C1331000pF
C1550.1uF
C1970.01uF
C1260.1uF
L23
EXC-CL3225U
C1311000pF
+C195
33uF/16V
C1941.0uF
C1280.1uF
C1710.1uF
C1841.0uF
C1410.01uF
C2120.1uF
C1470.1uF
C1900.1uF
L21
EXC-CL3225U
C1850.1uF
C1321000pF
C2020.1uF
C1651000pF
C163100pF
C2110.01uF
C1250.1uF C191
0.1uF
C1860.1uF
ZR391055POWER & GROUND
U1N
ZR391055SH
F17
F18
F19
F20
E15E14
E16F16
J11J12J13
J15J14
J16K10K11K12K13K14K15K16K17L9L10
AA16AB16AB15AB14AB13
G19
H20
G20
W20
Y19
Y20
AA17
AA18
P11P12
P14P13
P15P16P17P18
R9
R10
R11
R12
AB12AB11
L11L12L13L14L15L16L17L18M9M10
M12M11
M13M14M15M16M17M18N9N10N11N12
N15N14
N16
AA11
N17N18
N13
P9
E1H4Y2W3AB1AB19AE23A23
P10
R13
R14
R15
R16
R17
R18
T9T10
T11
T12
T13
T14
T15
T16
T17
T18
U10
U11
U12
U13
U14
U15
U16
U17
V11
V12
V13
V14
V15
V16
AA19
AA20
U6
V6W6
W7
Y7Y8AA8
AA9
AA10
K6J6H6
H7
G7
G8
F8F9F10
T6T5R5P5N5M5L5L6
F11E11E12E13
H21J21K21L21T21U21V21
W21K22L22M22N22P22R22T22U22
E17
D17
A14B12C11E10
A10B13
B14
CVD
DC
VDD
CVD
DC
VDD
IVDDIVDD
IVDDIVDD
GNDGNDGND
GNDGND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
IVDDIVDDIVDDIVDDIVDD
CVD
D
CVD
DC
VDD
CVD
DC
VDD
CVD
DC
VDD
CVD
D
GNDGND
GNDGND
GNDGNDGNDGND
GN
DG
ND
GN
DG
ND
IVDDIVDD
GNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GNDGND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GNDGND
GND
IVDD
GNDGND
GND
GND
NC0NC1NC2NC3NC4NC5NC6NC7
GND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
CVD
DC
VDD
CVD
DC
VDD
CVD
DC
VDD
CVD
DC
VDD
CVD
DC
VDD
CVD
DC
VDD
CVD
DC
VDD
CVD
DC
VDD
CVD
DC
VDD
CVD
DC
VDD
IVDDIVDDIVDDIVDDIVDDIVDDIVDDIVDDIVDDIVDDIVDDIVDD
MVDDMVDDMVDDMVDDMVDDMVDDMVDDMVDDMVDDMVDDMVDDMVDDMVDDMVDDMVDDMVDD
PLLAVDD
PLLAVSS
DACAVDD[1]DACAVDD[2]DACAVDD[3]DACAVDD[4]
DACAVSS[2]DACAVSS[1]
DHVDD
C1920.1uF
C1730.1uF
+ C204
33uF/16V
C1881000pF
C1450.1uF
L22 EXC-CL3225U
C1930.1uF
C1490.1uF
+ C181
33uF/16V
C1270.1uF
+ C205
33uF/16V
C1780.1uF
C1290.1uF
C1790.1uF
C1300.1uF
L24
EXC-CL3225U
C1460.1uF
C1691.0uF
C1500.1uF
C164100pF
C1871000pF
C2131.0uF
C2030.1uF
+C18333uF/16V
79
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power and Ground 2
Supply Filters/Bypass, LVDS
Locate between DDR chips.Vref = 1.5V
Supply Bypass, DDR S0
Supply Bypass, Tuner Demodulator
Pin 5 Pin 9 Pin 22 Pin 37 Pin 53 Pin 69 Pin 86 Pin 78
Pin 17 Pin 30 Pin 46 Pin 62 Pin 74
Phobos
Pin 9 Pin 53 Pin 78
D2
B
16 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
LVDSVcc
PLLVcc
PLLVcc
LVDSVcc
+2.5V
VREF
+2.5V
+2.5V
VREF
+2.5V
+2.5V
+2.5V
+2.5V
+2.5V
+2.5V
+2.5V
VREF
A3.3V
1.8V
1.8V
A3.3V
A3.3V
1.8V
A3.3V 1.8V
+2.5V
+2.5V
+3.3V
+3.3V
+2.5V
1.8V
C5190.1uF
C151500pF
C5230.1uF
C5270.1uF
C5150.1uF
C5200.1uF
C235
0.1uF
C2371.0uF
C16560pF
C219
1.0uF
C5241000pF
C5161000pF
C218
1.0uF
C5210.1uF
L26
EXC-CL3225U
C220
1.0uF
L61BLM18AG601
C244
0.1uF
LVDS DRIVERPOWER
U8B
DS90C2501
99
97
70113100
676665
83
192085
8182757796119123125
3373747678798084
124
121127
120126128
8789
868890
9294
919395
105109
104108
101103107111
102106110112
118122
PD
BAL
RES2RES3RES4
PWMVSTALHIRQ
VREF
TST1TST2TST3
Vcc0Vcc1Vcc2Vcc3Vcc4Vcc5Vcc6Vcc7
GNDGNDGNDGNDGNDGNDGNDGND
GND
Vcc3VVcc3V
GND_3VGND_3VGND_3V
SPLLVccSPLLVcc
SPLLGNDSPLLGNDSPLLGND
PLLVccPLLVcc
PLLGNDPLLGNDPLLGND
LVDSVccLVDSVcc
LVDSGNDLVDSGND
LVDSVcc3VLVDSVcc3VLVDSVcc3VLVDSVcc3V
LVDSGND3VLVDSGND3VLVDSGND3VLVDSGND3V
GNDGND
+ C1110uF
DDR SDRAM(PWR)
U3B
K4H561638F-UC(L)/B3
49
3
6
34
1814
9
12
15
1
33
48
52
55
58
61
64
66
171925435053
VREF
VDDQ1
VSSQ1
VSS1
VDD2NC1
VDDQ2
VSSQ2
VDDQ3
VDD1
VDD3
VSS2
VSSQ3
VDDQ4
VSSQ4
VDDQ5
VSSQ5
VSS3
NC2NC3NC4NC5NC6NC7
C421.0uF
R2062K
+ C236220uF
C229
0.1uF
C2380.1uF R205
2K
C5141000pF
C3910.01uF
+C1410uF
C5250.1uF
C2390.1uF
C228
0.1uF
L60BLM18AG601
C232
1.0uF
C2160.1uF
C431.0uF
C2170.1uF
C233
0.1uF
C223
0.1uF
C121500pF
C5261000pF
C3950.01uF
C3901.0uF
C441.0uF
C234
0.1uF
C5170.1uF
L25
EXC-CL3225U
C13560pF
C245
0.1uF
C3941.0uF
C2140.1uF
OREN
U9B
Cascade-2
5
67
915
17
2223
30
33353745
46
535560
62
69
7073
74
75
7677
78
8182 83
84
85
8687
8891929598
99
3
Vcor
GNDGND
Vcor1GND
Vdd
Vcor2GND
Vdd
GNDGNDVcor3GND
Vdd
Vcor4GNDGND
Vdd
Vcor5
GNDGND
Vcc(A1)
VccLO
GNDGND
VccCLK
GNDVdd_OSC GND
AVdd_PLL
GND
Vcc_PLLVcc_ADC
GNDGNDGNDGNDGND
AVcc_ADC
TEST
C5181000pF
C230
1.0uFC2480.1uF
+ C246220uF
TP3
1
C222
0.1uF
DDR SDRAM(PWR)
U4B
K4H561638F-UC(L)/B3
49
3
6
34
1814
9
12
15
1
33
48
52
55
58
61
64
66
171925435053
VREF
VDDQ1
VSSQ1
VSS1
VDD2NC1
VDDQ2
VSSQ2
VDDQ3
VDD1
VDD3
VSS2
VSSQ3
VDDQ4
VSSQ4
VDDQ5
VSSQ5
VSS3
NC2NC3NC4NC5NC6NC7
C2490.1uF
C2471.0uF
C5281.0uF
C522
0.1uF
C2150.1uF
C221
0.1uF
C231
1.0uF
80
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power & Ground 3
Supply Bypass, Decoder
Phobos
Supply Bypass, HDMI Receiver
For IOVcc
For CVcc
D2
B
17 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
DEC_AVcc
DEC_PVcc
DEC_DVcc
DEC_AVcc
DEC_PVcc
DEC_DVcc
A3.3V
+1.8V
+1.8V
DEC_PVcc
A3.3V
A3.3V
A3.3V
+1.8V
+3.3V_HDMI
+1.8V
+1.8V
A3.3V
A3.3V
+3.3V_HDMI
A3.3V
C5551000pF
C6540.1uF
C750.1uF
C5380.1uF
C6690.1uF
C5601000pF
C5341000pF
C800.1uF
L71 MLF2012A4R7K
ADV7400(Power)
U7E
ADV7400A
70
59
666051
4950
11
4089
5
17
4748
63
123990
618
AGND6
NC
ANND5AGND4AGND3
AGND1AGND2
DGND2
DGND4DGND5
DGND1
DGND3
PVDD1PVDD2
AVDD1
DVDD1DVDD2DVDD3
DVDDIO1DVDDIO2
+C7110uF
C5361000pF
+
C66610uF
C5561000pF
U10B
SiI9011CLU
1224364581
112125
13253780113126
71931687798
107120
6183069789710611849
535761
52566064
47 46
82
83
66
65
8687
43
4888
CVcc1CVcc2CVcc3CVcc4CVcc5CVcc6CVcc7
CGNDCGNDCGNDCGNDCGNDCGND
IOVcc1IOVcc2IOVcc3IOVcc4IOVcc5IOVcc6IOVcc7IOVcc8
IOGNDIOGNDIOGNDIOGNDIOGNDIOGNDIOGNDIOGNDAVcc
AVccAVccAVcc
AGNDAGNDAGNDAGND
PVcc PGND
AUDVcc
AUDGND
DVcc
DGND
XVccRVcc
NC
RSVDRSVDL
C6711000pF
C820.1uF
C5390.1uF
C6591000pF
C5290.1uF
C6680.1uF
C5520.1uF
C5411000pF
C770.1uF
C810.1uF
C5320.1uF
C5530.1uF
C6670.1uF
L66MLF2012A4R7K
+
C54910uF
C6601000pF
C720.1uF
L8EXC-CL3225U
C5541000pF
C5571000pF
C5510.1uF
C6560.1uF
L65MLF2012A4R7K
C6570.1uF
+C7910uF
C5310.1uF
C780.1uF
C5611000pF
+
C65310uF
C6581000pF
C6721000pF
C5401000pF
C5500.1uF
C5351000pF
C5430.1uF
C730.1uF
L7EXC-CL3225U
C5591000pF
C5300.1uF
C740.1uF
C5440.01uF
L64MLF2012A4R7K
C6731000pF
+C53733uF/16V
L6EXC-CL3225U
+C7610uF
C5330.1uF
C5581000pF
81
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power & Ground 4
1.2V - 2A (2.8A MAX)
2.5V - 1.6A (2.6A MAX)
3.3V - 1.5A (2.3A MAX)
5.0V - 0.5A (1A MAX)
Phobos
T0-263
TO-252
TO-263
TO-263
(1.0A)
(2.0A)
(1.0A)
AP1122 1A 1.2VLDO
TO-252
TO-263
加大散热面积和过孔散热
(1.0A)
(1.0A)
TO-263
TO-263
D2
B
18 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
3.3V
D5V+2.5V
+12V D8VD12V
D6V
D5V +3.3V
+5VD5V
D6V 5V
D3.3V +1.2V
3.3VD3.3V D1.2V
D3.3V 3.3V1.2V
D6VA3.3V
L704
FB-3A:TI321611U121
L714
FB-3A:TI321611U121
L705
FB-3A:TI321611U121
U702AP1084K50A
3
1
2
4
VI
GN
D
VO
TAB
U711AP1084-3.3
3
1
2
4
VI
GN
D
VO
TAB
L723
FB-3A:TI321611U121
L707
FB-3A:TI321611U121
E718
100uF/16V
U704AP1122
31
2
4
VIG
ND
VO
TAB
L717
FB-3A:TI321611U121
C717
0.1uF
L724
FB-3A:TI321611U121
C703
0.1uF
U710AP1122
3
1
2
4
VI
GN
D
VO
TAB
L726
FB-3A:TI321611U121
L721
FB-3A:TI321611U121
E702
100uF/16V
R708 820
U705AP1084-ADJ
3
1
2
4
VI
GN
D
VO
TAB
L719
FB-3A:TI321611U121
E711
100uF/16V
C719
0.1uF
R712 150
R709 150
U701AP1084-ADJ
3
1
2
4
VI
GN
D
VO
TAB
R713 150
U703AP1084-3.3
3
1
2
4
VI
GN
D
VO
TAB
L718
FB-3A:TI321611U121
+E712
470uF/16V
L702
FB-3A:TI321611U121
U706AP1122
3
1
2
4
VI
GN
D
VO
TAB
U709AP1084K50A
3
1
2
4
VI
GN
D
VO
TAB
L725
FB-3A:TI321611U121
+E713
470uF/16V
C716
0.1uF
82
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.8V Linear RegulatorFROM LG PDPPSU
FROM LG PDPPSU
Phobos
FROM SDI PDPSMPS
Power & Ground 5
1.8V Linear Regulator for Oren
Grounded Mounting Holes, PCB
POWER TEST POINTS
STB PDC POWER CON
(1.0A)
TO-263
NOUSE
D2
B
19 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
RELAY-SW
VS-ONVS-ONVS-ONVS-ONVS-ONVS-ONVS-ONVS-ONVS-ONVS-ONVS-ONVS-ON
REL-SWREL-SW
+5VSB
REL-SW
STB5VSTB5VSTB5VSTB5VSTB5VSTB5VSTB5VSTB5VREL-SWRELAY-SW
VS-ON
PWR-ON
9V
STB5V
5VSC
9VSC
5VSC
+3.3V
+5V
D12V
D6VD12V
D3.3V
D6V
STB5V
STB5V
D12V
1.8V
+2.5V
+3.3V +1.8V
D5V
+1.2V +12V +1.5V
+3.3V +1.8V
+5VSB+5VSB
+5VSB
+5V
+5VSB
5VSB+5VD8V
TP16
1
PAD3Gnd_Mount_Pad
11
E708
100uF/16V
C651
0.1uF
TP14
1
L722FB-3A:TI321611U121
L713FB-3A:TI321611U121_NS
CN702
33P3278 7
1234567
U207AZ1117-1.8
3
1
2
4
VI
GN
D
VO
TAB
TP15
1
PAD1Gnd_Mount_Pad
11
R131 0_NS
Q4SST3904 BCE
TP7
1
C323
0.1uF
L716
FB-3A:TI321611U121_NS
E715
0.1uF_NS
CN703
33P3278 11
1234567891011
123456789
1011
C701
0.1uF
TP4
1C704
0.1uF
TP19
1
TP11
1
E716
100uF/16V_NS
L701FB-3A:TI321611U121
R128
3.3K
C156
0.1uF
R1263.3K
TP8
1
C707
0.1uF
Q5SST3904 BCE
L720
FB-3A:TI321611U121_NS
CN704
33P3278 5
12345
12345
C718
0.1uF_NS
TP1
1L712
FB-3A:TI321611U121_NS
C652
47uF/16V
12
C157
0.1uF
R125
3.3K
CN701
33P3278 9
123456789
R127
3.3K
C158
0.1uF
TP6
1
L706
FB-3A:TI321611U121_NS
C706
0.1uF
R132 0
TP12
1
CN706
33P3278 4
1234
C705
0.1uF
E717
100uF/16V_NS
TP13
1
PAD2Gnd_Mount_Pad
11
U208AZ1117-1.8
3
1
2
4
VI
GN
D
VO
TAB
TP9
1
C324
47uF/16V
12
TP17
1
PAD4Gnd_Mount_Pad
11
U707AP1084-5_NS
3
1
2
4
VI
GN
D
VO
TAB
U708AP1084K50A_NS
3
1
2
4
VI
GN
D
VO
TAB
TP18
1
L703 FB-3A:TI321611U121
CN705
33P3278 12
123456789101112
C702
0.1uF
83
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Phobos
I2C: 0x80
FQFP-64
D2
B
20 22Wednesday, April 13, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
AV-R
AV-L
EARPHONE_L
AUDMR
AUDAR
AVREF
EARPHONE_RAUDAL
SC3L
SC4RSC4L
SIF
AXTALIAXTALO
AUDIO-L
AUDIO-R
ANIM
ANI1
SC1L
SC3R
SC1R
CPM
AUDMLAUDML
AGNDC
SC2R
CPA
I2CCLK0
SC-R1
I2CDATA0
SC-L1SC2LAV-IN-L
AV-IN-R
RESETn
AUDIO-L
SIF
AV-R
I2CCLK0
AV-L
I2CDATA0
RESETn
AUDIO-R
AUDMRAUDML
EARPHONE_REARPHONE_L
AV-IN-L
AV-IN-R
HW_RST_n
5VSB 5VSB
VCCAUVCCAD V8AUD
VCCADVCCAU
V8AUDV8AUD
V8AUD
D8V
C2046
1nF_NS
C2029 56pF
C2040
18pF
E232 1uF/16V1 2
L216FB_1K_OHM_200MA
C22747uF/16V
12
C24147uF/16V
12
C676 0.33uF
U223
MSP3455G-QI-B8-V3
56P 593 2
12
3456
12
789
62
165363
4544434241403938373635
47
505251
5455
46
3230
11 48 33 27 19
56
1314152224585964
6061
57
28292526
1718
202123
34493110
SCLSDA
I2S_CLI2S_WSI2S_DOI2S_DI1I2S_DI2
ADR_DAADR_WSADR_CL
ADR_SEL
RESETnTESTENSTDBYn
SCI_IRSCI_ILASG1SC2_IRSC2_ILASG2SC3_IRSC3_ILASG3SC4_IRSC4_IL
MONO_IN
ANA_IN1pANA_IN2pANA_INm
XTALIXTALO
VREFTOP
CAPL_MCAPL_A
DVS
S
AVSS
1
AHVS
S1
VREF
1VR
EF2
TP
NC1NC2NC3NC4NC5NC6NC7NC8
DCTR_IO1DCTR_IO2
AUD_CLO
SC1_ORSC1_OLSC2_ORSC2_OL
DACA_RDACA_L
DACM_RDACM_L
DACM_SUB
AGN
DC
AVSU
P
AHVS
UP
DVS
UP1
C224 10uF/16V
1 2C2028
56pF
E226 1uF/16V1 2
R63 100
C225 10uF/16V
1 2
E227 1uF/16V
1 2
R64 100
L217FB_1K_OHM_200MA
C2033 0.33uF
Y20318.432MHz
1 2
C674
470pF
C24047uF/16V
12
C677 0.33uF
C675
0.1uF
C2038 0.33uF
C22647uF/16V
12
C2043
1nF_NS
C664
0.1uF
C663
470pF
C24247uF/16V
12
C2034 0.33uF
C655
0.1uF
C2035 0.33uF
C2037 0.33uF
R65 0_NS
C665
470pF
C661
0.1uF
C2039
18pF
C2044
1nF_NS
C670
0.1uF
C2045
1nF_NS
C2036 0.33uF
E231 1uF/16V1 2
L21810UH
84
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TO Earphone OUTPUT
Phobos
TA2024 OUTPUT GND AND INPUT GNDNEED TO BE CONNECTED BY ONE POINT.
(1) C634,C647,C649 NEAR TO THE PINS OF VDD AND PGND
(2) D630~D633 NEAR TO THE PINS OF OUTPUT AND PGND
(3) L630~L633 FAR TO THE PINS OF OUTPUT
D2
B
21 22Monday, April 18, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
EARPHONE_R
EARPHONE_L
AUD_DOWN
LOUT+
AUDML
LOUT-
AUDMR
LO+
12VAMP
COMLO-
COMRO-
RO+
MUTEMUTE
ROUT+
ROUT-
AUD_DOWN
EAR_R
EAR_L
PHONE-ON
PHONE-ONAUD_DOWN
AUDML
AUDMR
AUD_DOWN
EARPHONE_L
EARPHONE_R
12VAMP
STB5V
12VAMP
12VAMP
12VAMP
STB5V
24V
12V-AUDIO
12V-AUDIO
D3.3V
R1893.3K
D12
1N5822_NS
R639
10 1/4W
L634 33uH/2A1 21 2
J605
33P3278 4_NS
1234
E222
1uF/16V
12
C6460.47uF
R636 3.3K
E225
1uF/16V
12
C631
1.0uF
C696
0.1uF
C7080.1uF
R641 8.2K
L638 FB1 21 2
L636 FB1 21 2
R301 10K
R637 3.3K
R64010 1/4W
E224 1uF/16V1 2
L635 FB1 21 2
+
-
U602A
TL072CD
3
21
84
C715
100pF
L637 FB1 21 2
R638
1K
C711
0.47uF
J11
33P3278 5
12345
12345
R643 20K
+
-
U602B
TL072CD
5
67
84
C632
0.1uF
D633 MBRS130T312
J14
33P3278 5
12345
12345
R655
1K
Q631SST3904 BCE
C697
0.1uF
+
E1470uF/16V_NS
C641
0.47uF
R2143.3K
Q630SST3904 BCE
D630 MBRS130T312
E223 1uF/16V
1 2
C1660.1uF_NS
L633 10uH/3A1 21 2
D632 MBRS130T312
C700 1.0uF
L631 10uH/3A1 21 2
R65010K
C712
0.1uF
D631 MBRS130T312
C642
0.47uF
R644 20K
C698
0.1uF
R647 10K
C714
100pF
C6391000pF
R654 10K_NS
R635
3.3K
C643
0.1uF
U601
TA2024
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36+5GEN
DCAP1
DCAP2
V5D
AGND1
REF
OVERLOAD
AGND2
V5A
VP1
IN1
MUTE
NC
VP2
IN2
BIASCAP
AGND3
SLEEP FAULT
PGND2
NC
DGND
NC
OUTP2
VDD2
VDD2
OUTM2
OUTM1
VDD1
VDD1
OUTP1
NC
VDDA
NC
PGND1
CPUMP
L630 10uH/3A1 21 2
R642 20K
C644
1000pF
C710
0.47uF
+
E630
2.2uF/16V
C7131000pF
R648 10K
C699
0.1uF
U12
LM2596T-12_NS
1
2
3
4
5
Vin
Vout
GN
D
Feedback
ON
/OFF
R645 20K
+ E6321000uF/16V
J603
33P3278 6
123456
+
E631
2.2uF/16V
R646 10K
C695
0.1uF_NS
C7091000pF
R653 10K_NS
C6451000pF
R649 10K
C6400.47uF
L632 10uH/3A1 21 2
R651
10K_NS
R65210K
85
86
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
160 Audio Clock Freq. Sel bit 1 (Main)(see table p11)161ACS0 Audio Clock Freq. Sel bit 0 (Main)
ACS1
(see table p.05)12 AUDIO IN SelectAUD_SEL_A
1 = WR Enable, 0 = protected.3 NAND FLASH WR protectionWP~Active low.4 Tuner control / Setup errow
LED D3 Control
CH +Active low.5 Tuner control / Setup errow
LED D2 Control
CH -Active low.6 VOL control / Setup errow
AUD_DOWN
VOL +Active low.7 VOL control / Setup errow
HD_SYNC_SEL
VOL -
1 = off, 0 = lit
11
LED6 1 = off, 0 = lit
163
169
1 = off, 0 = litLED5
Function
168
1 = off, 0 = litLED4
ZR391055 GPIO #
167
1 = off, 0 = litLED3
Signal
166LED2
GPIO Pin Table
159
LED D6 ControlLED D5 ControlLED D4 Control
154 SPI EEPROM Wright protection. Active low.SPIEEPROM_WP_nActive high.LAN_INT 155 Ethernet IC Int.
GPOIs Table
Video_Input_Select 2 Composite - Y/C Video Input recognition.
Setting
1 = Composite, 0 = Y/C
(see table p11)
HDMI_INT 156 HDMI IC Int.
Active high.0 LCD backlight ON/OFF control.LCD_ON
(see table p.05)13 AUDIO IN SelectAUD_SEL_B
Active high.
AUD_DOWN MUTE
IDE_HSCBL_n
HD_DOWNACLK_SEL0ACLK_SEL1FMS_SEL
SLEEP_MODE_n
119
107108109110
123
CVmix_SEL 104
NAND_GPIO1_n 1
HD_SYNC_SEL(see table p11)162 Audio Clock Freq. Sel bit 2 (Main)ACS2
157 Subcarrier Frequency Lock FSC_LOCK158 LCD PWM Control.LCD_PWM
Allow to boot-up from NAND FLASH Active low.
ACLK select source - HDMI/CLK GEN Active low.Active low.ACLK select source - HDMI/CLK GEN
Active lowHead Phone MUTE
RGB out filter select HD/SD
Analog video composite summer
AIN_INT_n 120 Analog Decoder IC Int. Active low.Active low.
CEC 122 HDMI controlActive low.LOW PWR mode control
Phobos
HDMI_SCDT 112 HDMI Signal Detect Active high.
AUD_SEL_C 14 AUDIO IN Select (see table p.05)
TV_VIDEO 113 VIDEIO IN Select / FP SW Active low.
MENU
121 2 COMPONENT SIGNAL SW (see table p.07)HD_SEL
184 SEL / FP SW Active low.
12 DUAL Function
Setting
COLOR Function Active low.
FunctionDS90C2501 GPIO#
0 LVDS Control
Active high.
HDMI_VSYNC 125 SYNC signal control from HDMI sourse.
D2
B
22 22Monday, March 28, 2005
BOBCAT_D1_Plus.DSN
Title
Size Document
Rev
Date:
Sheet of
Drawn by: O. Marinovsky
87
EN 21.
Spare Parts List
Set Level 42MF130A/37
Various
0001 9965 000 29550 Plasma panel0002 9965 000 29551 Conductive filter0003 9965 000 29552 Key board0004 9965 000 29553 Image board0005 9965 000 29554 Control stand0006 9965 000 29555 Power switch board0007 9965 000 29556 PSPC0008 9965 000 29557 Front/side AV board0009 9965 000 29558 Stand assy0010 9965 000 29562 Front assy0011 9965 000 29563 Bear-cover-M0012 9965 000 29564 Bear cover low0013 9965 000 29565 Bear cover BKT0014 9965 000 29566 Internal sound box L0015 9965 000 29567 Internal sound box R0016 9965 000 29568 Handle0017 9965 000 29569 Image to panel LVDS0028 9965 000 29570 Power cord0030 9965 000 29571 Remote control0031 9965 000 29572 Manual
Boards Plasma Panel 42MF130A/37
Various
0034 9965 000 30132 Assy PCB buffer(E)0035 9965 000 30133 Assy PCB buffer(F)0036 9965 000 30134 Assy PCB buffer(G)0037 9965 000 30135 Assy PCB buffer(Y-up)0038 9965 000 30136 Assy PCB buffer(Y-low)0039 9965 000 30137 Assy PCB logic main0040 9965 000 30138 Assy PCB Y main0041 9965 000 30139 SMPS0042 9965 000 30140 SMPS-video0043 9965 000 30141 Assy PCB X main0044 9965 000 30142 Image board
Set Level 42MF230A/37
Various
0001� 9965 000 30175 Plasma panel0002 9965 000 29551 Conductive filter0003 9965 000 29552 Key board0004� 9965 000 30176 Image board0005 9965 000 29554 Control stand0006 9965 000 30177 PSPC0007 9965 000 30178 PSPC0008 9965 000 29557 Front/side AV board0009 9965 000 30179 Stand assy0011 9965 000 30180 Logo0012 9965 000 30181 BKT-main-power0013 9965 000 30182 Handle0014 9965 000 30183 PDP Internal sound box L0015 9965 000 30184 PDP Internal sound box R0016 9965 000 30185 Corner rubber0017 9965 000 30186 Al foil0018 9965 000 30187 Al foil0019 9965 000 30188 Foam 1000x10x20020 9965 000 30189 EMC Foam0021 9965 000 30190 EMC Foam0022 9965 000 30191 EMI sponge 110x10x20023 9965 000 30192 EMI sponge 110x10x60024 9965 000 30193 EMC Foam 90*W10*T80025 9965 000 30194 EMI sponge 80x10x20026 9965 000 30195 EMI sponge0029 9965 000 30196 EMI core0030 9965 000 30197 EMI filter0031 9965 000 30198 Wire harness0032 9965 000 30199 Wire0033 9965 000 30200 Wire harness0034 9965 000 30201 Wire harness0035 9965 000 30202 Wire harness0036 9965 000 30203 Wire harness0037 9965 000 30204 Wire harness0038 9965 000 30205 Wire harness0039 9965 000 30206 Wire harness0040 9965 000 30207 Wire harness0041 9965 000 30208 Shield-10042 9965 000 30209 BKT-shield520043 9965 000 30210 BKT-holder-50044 9965 000 30211 Front bottom
0045 9965 000 30212 Key press 7x0046 9965 000 30213 2005 lenss0047 9965 000 30214 Front assy0048 9965 000 30215 Dust proof sponge
950*100049 9965 000 30216 Dust proof sponge
550*100050 9965 000 30217 Conductive fabric/1000*0051 9965 000 30218 EMI sponge 620x10x40059 9965 000 30219 Rear cover M0060 9965 000 30220 Rear low cover0074 9965 000 29570 Power cord0077 9965 000 29571 Remote control
Boards Plasma Panel 42MF230A/37
Various
0087� 9965 000 30222 Assy PCB buffer(E)0088� 9965 000 30223 Assy PCB buffer(F)0089� 9965 000 30224 Assy PCB buffer(Y-up)0090� 9965 000 30225 Assy PCB buffer(Y-low)0091� 9965 000 30226 Assy PCB logic main0092� 9965 000 30227 Assy PCB Y main0093� 9965 000 30228 SMPS0094� 9965 000 30229 SMPS-video0095� 9965 000 30230 Assy PCB X main0096� 9965 000 30142 Image board
88
THESE DOCUMENTS ARE FOR REPAIR SERVICE INFORMATION ONLY. EVERY REASONABLE EFFORT HAS BEEN MADE TO ENSURE THE ACCURACY OF THIS MANUAL; WE CANNOT GUARANTEE THE ACCURACY OF THIS INFORMATION AFTER THE DATE OF PUBLICATION AND DISCLAIMS RELIABILITY FOR CHANGES, ERRORS OR OMISSIONS.
REVISION LIST3122 785 15690 First Release
3122 785 15691 Model 42MF230A/37 added, 42MFx30A/37 as mentioned in this manual,means both 42MF130A/37 and 42MF230A/37 sets.
89