Xilinx Training@MSCE

8/17/2019 Xilinx Training@MSCE

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CoreEL Technologies (I) Pvt. Ltd.#21, 7th Main, 1st Bloc, !ora"angalaBangalore $%%&', IndiaPhone *1+%+'1*7%'%% -*$$'2&*$a/ *1+%+&%72&$&

CoreEL 0niversit Progra"

Ma"idi aga 3a456ilin/ 88lication Engineer

".nagara459coreel.co"


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Customer Training

ON

Xilinx Design Flow Using ISE system Edition

Confidential


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Corporate Overview

Started in 1992, conceptualized IP Cores as a business proposition

Successfully developed IP cores for te !eleco"#$etwor%in& 'ar%et

Popularized te concept of (P)* !ecnolo&y in India and created te

"ar%et for Xilin+ and 'entor )rapics

C)-Core./ Pro&ra""able Solutions was launced in 1999 wit a uni0uebusiness "odel-istribution, /SI ."bedded esi&n !rainin& and esi&n

Services

Currently e"ploys over 245 people

Consistent revenue &rowt in all 6usiness Se&"ents

Privately eld, profitable, wit an e"ployee ownersip of over 247

8ena"ed as Core./ !ecnolo&ies in 255

Core.l confidential


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6usiness Portfolio

Core.l confidential

Products & ServicesTechnology Solutions Training & ManpowerDev.

EDA Tools

Silicon Products

Corporate

Academic

Staf

P!A

"#$Systems$PC%

Manuacturing

'ntellectual Property

Syner&etic S%ills

Silicon ProductsSilicon Products

SurveillanceProducts


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6uildin& Partnersips

Core.l confidential


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Our O8?S-'*!/*6

>I$ 8I.8-X >O8?S

i&ilent Inc


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AGENDA

(P)* *rcitecture

XI/I$X IS. esi&n (low

(P)* ebu&&in& flow- Cipscope Pro

SP esi&n (low-Syste" &enerator

."bedded esi&n flow- .? S?

Confidential


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>at is an (P)* A

Confidential

.

What is an FPGA?

• The acronym “FPGA” stands for Field Programmable Gate

rray!

• Field "rogrammable # t$e %un&tion is de%ined by t$e &ustomer'

and te device can be repro&ra""ed in situ Bin te fieldDE

• Gate array # t$e de(i&e is &om"rised o% logi& resour&es laid out

in a re&ular pattern

• FPGAs can be re"rogrammed as o%ten as desired # so t$ere isno &ost

associated wit can&in& te desi&n

• FPGAs are a $ig$ly "arallel resour&e &a"able o% o"erating at

$ig$

speed B)**+s o% ,-./0

• The architecture of FPGAs has eo!ed oer the years toincor"orate

arit$meti& and memory resour&es' and "eri"$eral inter%a&es0

• #endors offer deices aryin$ in s"eed and si.e' and wit$

di%%erent

"i+tures of logi& resour&es and %eatures0


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(P)*FCusto" Inte&rated Circuits

Confidential

(P)* intended to prototype *pplication-specificInte&rated Circuits B*SICsE!oday, used in 8econfi&urable Co"putin&(irst (P)* XC25;: introduced by Xilin+ Corp in

194

(P)*s vs *SICsG

(P)*s are "ore cost-effective

/ower speed in (P)*s(P)*s are less power efficient(P)* circuits can be "odified Bat start ti"e or even

at runti"eE


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(P)*G

Confidential

.

Field-programmable gate arrays: are con;ig5ra


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6asic (P)* *rcitecture

2 cip layout

Co"ponentsG C/6G Confi&urable /o&ic

6loc% i"ple"ents lo&ic

function

IO6G Input # Output 6loc% C'G i&ital Cloc% 'ana&er

Interconnect $etwor%

Sort distance lines

/on& distance lines Cloc%lines

Switc bo+esG pro&ra""able

switces

Confidential


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8outin& si&nals in an (P)*

Confidential


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Confi&urable /o&ic 6loc% BC/6E

Confidential


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*tlys SP; # irte+-4 Overview

Confidential

Slice

6LUT

6LUT

6LUT

6LUT


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*dditional =i&-level Pri"itives in iscrete Silicon

Si"plified irte+-4

XC4(X+++! floor plan (re0uently used i&-level

co"ponents are provided

in discrete silicon

6loc%8*'B68*'EGsetofbloc%s tat eac store up

3; %bits of data

SP: slicesG 24+1 bit

"ultipliers followed by a :bit accu"ulator

CP


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irte+ *rcitecture

irte+H-II arcitecturescore volta&eoperates at 14

%&' (!oc)s *%'(s+

,onfi$urab!e

-o$ic (!oc)s

*,-(s+

,!oc) ana$ement

*D,s/ (0FG01es+

(!oc)

2e!ect3A4

resource

Dedicated

mu!ti"!iers

Pro$rammab!e

interconnect

First FPGA Device to include embedded multipliers


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irte+-: *rcitecture

) Gb"s Sele&tIO1C$i"Syn&1 Sour&e syn&$'

XCITE &ti(e Termination

Smart 2,New blo&3 2,4FIFO

Xesium Clo&3ing

Te&$nology 5** ,-.

PowerPC1 6*5

wit$ PU Inter%a&e65* ,-.' 78* D,IPS

Tri#,ode

Et$ernet ,C )*4)**4)*** ,b"s

2o&3etIO1

,ulti#Gigabit

Trans&ei(ers799 ,b"s:)*0; Gb"s

XtremeDSP1

Te&$nology Sli&es957 )8x)8 G,Cs

d(an&ed C


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23 of X irte+-4 Overview Slide 23

*dvanced SP Solution =i&er SP Perfor"ance

SP Perfor"ance J )'*Cs K 6andwidtB'e"ory K IOE

Xtre"e SPH Slices .nable &reater parallelis" for faster

perfor"ance


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Pro&ra""in& (P)*s

Circuits are specified in=ardware escription

/an&ua&e B=/E or usin&

esi&n Sce"atics

Sce"atic desi&ns are easier

to visualize =/ desi&ns easier for lar&e

ierarcical desi&ns

=/G (or"al description

di&ital lo&ic circuits

=/, erilo&

#5D-6

=/ J =SIC =ardware

escription /an&ua&e =SIC J ery =i& Speed

Inte&rated Circuits

=SIC was a


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esi&n flow in /SI # (P)*

Specifications

Design Entry

Functional Verification

Synthesis

Post-Synthesis Verification

PAR

Post-PAR Verification

Bit-Format

Graphical

Simulation

Synthesizer

Post-syn simulation

Simulation

F P

G A

S p e c

i f i c

F l

o w

DF

Verification

!ayout

Fa"rication

Verification

AS#$ Specific

Flow

Physical Verification

Formal Verification

!ayout E%itor

Physical Verification

(P)* 8 i t


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(P)* 8e0uire"ents

(P)* Specifications

8!/ esi&n ocu"ent erification ocu"ent

esi&n Constraints8!/ Codin&

!estbenc

Si"ulation

Syntesize

I"ple"entation

!i"in& *nalysis

6I! (ile Pro&ra""in&

=ardware ebu&&in&


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Xilin+ IS. esi&n Suite

Slide :5

3T- Desi$n

2oft7are Dee!o"ment

Functiona! #erification 3T- 2ynthesis F!oor"!annin$

5W&2W ,o #erification

8rd "arty

5ard7are Desi$n3T'2

8rd "arties

P!ace 93oute

1i!in: P!atform 2tudio

(ase 2ystem (ui!der *(2(+

2oft7are Dee!o"ment ;it *2D;+

icro(!aect

Nai$ator

%2E 2imu!ator

or 8rd Party12T

or 8rd Party

P!anAhead %m"!ementation 1Po7er

%&' P!annin$

P!anAhead

Po7er Estimation

1i!in: Po7er

Estimator


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FPG .ebugging 4low! %hipscope Pro

Confidential


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ebu& and erification is Critical

N De(ug and veri)cation can

account or over *+, o anP!A design time

N Serial nature o de(ug andveri)cation can ma-e itdicult to optimi/e

N 'necient strategy mayresult in product launchdelay 0oss in mar-et share

0oss o )rst1to1mar-etadvantages

Final De(i&eFinal De(i&e

DesignDesign

Im"lementationIm"lementation

DesignDesign

S"e&i%i&ationS"e&i%i&ation

6*?6*?o%o%

DesignDesign

TimeTime

Design @eri%i&ationDesign @eri%i&ation

and Debug and Debug


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'2 Pads

' 2 P

a d s

' 2 P

a d s

'2 Pads

0ogic %'ST Memory %'ST Access

MemoryArray

CP3Core

'PCore

Custom %oundary Scan TAP Controller

Embedded 2ystem (usEmbedded 2ystem (us

Custom0ogic

CustomCore

Traditiona! Debu$

Challenges accessing internal signals

N Limited Internal Visibility– Ho do I access the

embedded system bus!

N Hard IP Cores– Can"t get internal access to!N Full #can Insertion

– Increases overhead!N It"s $oo Late Anyay%

– &e'spins are ()*&+*,#L-

e.pensiveN Co'Veri/cation– $ools are cumbersome and

slo– +odeling issues


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FPGA

Probepoints

E4ternal

0ogicAnaly/er

Pins

N 5e6uires E4tensive Dedicated '$2 or De(ug– Driving signals to e4ternal '$2 introduces

additional pro(lems

N 'n7e4i(le solution– Dicult or impossi(le to add additional

de(ug pins i needed

N 0imited visi(ility to on1chip activity


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Cipscope ebu&

'2 Pads

' 2 P

a d s

' 2 P

a d s

'2 Pads

%oundary Scan TAP Controller

Embedded 2ystem (usEmbedded 2ystem (us

MemoryArray

PPC*+8Core

'PCore

CustomCore

IC*)

ILA

ILA

ILA

I0ACustom0ogic

ILA

N FPGA (nables Full Internal Visibility– Chip#cope Pro Integrated Logic

Analy1erN Access Processor #ystem 0usses

– Chip#cope Pro Integrated 0us

Analy1erN Fle.ible *n'Chip Debug

– #mall2 e3cient cores access anynode or signal and can beremoved at any time

N It"s )ever $oo Late in an FPGA%

– Fi. problems during developmentA)D a4ter product deploymentN (nable Complete #ystem

Veri/cation– Debug systems in real'time– )o need to e.trapolate behavior

Chip#cope Pro tools provide complete on'chip access to interna


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Core>en

C?P Core >enerator

Core>en

C?P Core >enerator

Instantiate Cores into

?o5rce @AL

Instantiate Cores into

?o5rce @AL

Connect Internal ?ignals

to Core (in ?o5rce @AL)

Connect Internal ?ignals

to Core (in ?o5rce @AL)

?nthesie?nthesie

I"8le"entI"8le"ent

?nthesie?nthesie

Chi8?co8e Pro Core

Inserter (into netlist)

Chi8?co8e Pro Core

Inserter (into netlist)

Ao=nload and Ae


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.2P .esign Flow-2ystem generator

Confidential


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'erie7 of 2ystem Generator for D2PN !e industrys syste"-level desi&n environ"ent BI.E for

(P)*s

Inte&rated desi&n flow fro" te Si"ulin%

software to te6I! file

/evera&es e+istin& tecnolo&ies

N '*!/*6 , Si"ulin%

N =/ syntesis

N IP Core librariesN (P)* i"ple"entation tools

N Si"ulin% library of arit"etic, lo&ic operators, and SPfunctions BXilin+ bloc%setE

6I! and cycle-true to (P)* i"ple"entation

N *rit"etic abstraction *rbitrary precision fi+ed-point, includin& 0uantization and

overflow

Si"ulation of double precision as well as fi+ed point

2 G ( d D i F!


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2ysGen=(ased Desi$n F!o7

2imu!in) #erification

2ynthesis

%m"!ementation

Do7n!oad

Timin$ 2imu!ation

%n=,ircuit #erification

Functiona! 2imu!ation

2ystem Generator 2ystem #erification


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5D-2ystem Generator 2ystem #erification

2ynthesis

%m"!ementation

Do7n!oad

Timin$ 2imu!ation



iles 3sed5Con)guration )le

5"D05'P5Constraintsile


5D-=,o2im #erification


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5D-2ystem Generator

AT-A(&2imu!in)

2ystem #erification

iles 3sed5Con)guratio

n )le5"D05'P5Constraintsile

2ynthesis

%m"!ementation

Do7n!oad

Timin$ 2imu!ation




5W%- #erification


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."bedded evelop"ent ?it

>at is ."bedded evelop"ent ?it B.?EA

!e ."bedded evelop"ent ?it is te Xilin+ software suite fordesi&nin& co"plete e"bedded pro&ra""able syste"s

!e %it includes all te tools, docu"entation, and IP tat you re0uire

for desi&nin& syste"s wit e"bedded I6' PowerPCH ardprocessor cores, and#or Xilin+ 'icro6lazeH soft processor cores

It enables te inte&ration of bot ardware and softwareco"ponents of an e"bedded syste"


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4; of Xirte+-4 Overview

PowerPC Processor elivers

=i&est Syste" Perfor"ance

TCP/IP Throughput for Ethernet Po#erPC? 660 Processor

&iga:it thernet /e4erence Design

%nterru"t

,ontro!!er

%,&2P%

0A3T

GP%'

#irte:4=@ F1T FPGA

TAG

PL96

Ethernet

DD3

Net7or)in$ 2tac)

*#:Wor)s+

Debu$

emory

,ontro!!er

Gi$abit Ethernet A,

H-,*w-,e

Sy"te8

M-:

Th,/0'hp0t

Micro;laze onSpartan

60 M:ps

Micro;laze on

-irtex5 "@'

A0 M:ps

P/we,PC /nVi,te:(5 FT

;%& M!p"

B sing m:o=rames M' size E A000

Exam"le! Et$ernet Networ3ing A TCP4IP


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."bedded evelop"ent (low

ata2'.'

ownload Co"bined

I"a&e to (P)*

Co"piled ./( Co"piled 6I!

3T'2/ (oard 2u""ort Pac)a$e

."beddedevelop"ent ?it

%nstantiate the

B2ystem Net!istC

and %m"!ement

the FPGA

7

=/ .ntry

Si"ulation#Syntesis

I"ple"entation

ownload 6itstrea"

Into (P)*

Cipscope

Standard (P)*=> evelop"ent (low

=/ or erilo&

Syste" $etlist%nc!ude the (2P

and ,om"i!e the

2oft7are %ma$e

7

Code .ntry

C#CKK Cross Co"piler

/in%er

/oad Software

Into (/*S=

ebu&&er

Standard ."beddedS> evelop"ent (low

C Code

6oard Support

Pac%a&e

12 & Co"piled 6I!Co"piled ./(

Xilin+ Platfor" Studio BXPSE


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Xilin+ Platfor" Studio BXPSE

11

22

:: 44 ;;

33

@@

Detai!ed ED; Desi$n F!o7


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Detai!ed ED; Desi$n F!o7

Processor 'PMPD iles

system.uc

Create P!A Programming9system.(it:

M"S ilesystem.mhs

Plat!en

P!A 'mplementation9'SE$;7ow:

"ardware

Dataetlists

Source Code9?"D0$?erilog:

Synthesis

#tandard (mbedded Hardare Flo#tandard (mbedded#o4tare Flo


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(or any 0ueries please write to us

uptcoreelco"

mailto:[email protected]:[email protected]


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(a+G K91-5-35@23;3

!an% Rou

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Xilinx Training@MSCE