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Xilinx FPGA Development Environment Tutorial Eric MacDonald

xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

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Page 1: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Xilinx FPGA Development Environment

Tutorial

Eric MacDonald

Page 2: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Basic Flow

Verilog RTL files (.v)

User’s Constraint File (.ucf) pin assignment, timing

synthesis place route

Xilinx ISE

configure

rom fpga

USB to JTAG

Page 3: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Create “New Project”

Page 4: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Go to directory containing existing RTL and UCF files. I prefer to have subdirectory to this for the many Intermediate files generated by Xylinx – called “xylinx”

Page 5: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Select the correct device.

Page 6: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Add existing source files – including UCF and simulation files. Don’t “copy to project” unless you want the files moved to the xylinx sub-folder.

Page 7: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Constraints Files - *.ucf

  I prefer to use text based files, but it is also possible to use the “user’s constraints” gui.

  At a minimum, you need to specify pins to ports and a required speed.

Page 8: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Verify the added files.

Page 9: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Design Files

Implementation Process Steps

Output Log

Double click final synthesis step to start implementation

Page 10: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Synthesis in process

Page 11: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Synthesis complete With timing results And *.bit file for programming

Page 12: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Double click the step for configure device under “Generate Programming File”

Page 13: xilinx fpga development - · PDF fileXilinx FPGA Development Environment Tutorial Eric MacDonald . ... File->Open Proiect X Processes No flow available. P¶ocesses T cl Shell Find

Devices on the JTAG Boundary Scan chain self-identify. Some boards (i.e. BASYS) have proprietary software


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