Upgrading to SystemVerilog for FPGA Designs - FPGA Camp Bangalore, 2010

Upgrading to SystemVerilog for FPGA Designs

- Presented at FPGA Camp, Bangalore

Srinivasan VenkataramananChief Technology Officer

CVC Pvt. Ltd.www.cvcblr.com

CVC Copyright 2008www.cvcblr.com 2

Agenda

Introduction to SystemVerilog (SV) SV - RTL Design constructs SV Interface SV Assertions Success Stories SV-FPGA Ecosystem

About the presenterSrinivasan Venkataramanan, CTO, www.cvcblr.com http://www.linkedin.com/in/svenka3 Over 13 years of experience in VLSI Design & Verification Designed, verified and lead several multi-million ASICs in

image processing, networking and communication domain Worked at Philips, Intel, Synopsys in various

capacities. Co-authored leading books in the Verification domain. Presented papers, tutorials in various conferences,

publications and avenues. Conducted workshops and trainings on PSL, SVA, SV,

VMM, E, ABV, CDV and OOP for Verification Holds M.Tech in VLSI Design from prestigious IIT, Delhi.

CVC Copyright Protected Material, www.cvcblr.com3


What is SystemVerilog? Superset of Verilog-2001 IEEE 1800-2005 standard More information @ www.SystemVerilog.org Several books available:

SystemVerilog Assertions Handbook – Ajeetha, Ben Cohen, Srinivasan, www.systemverilog.us

A Pragmatic approach to VMM adoption – Ajeetha, Ben, Srinivasan

SystemVerilog for Designers, Stuart Sutherland


Verilog 2001

SystemVerilog - Evolution

Enhanced DesignConstructs, modeling

SV-Design

DPI – Quickly connect C/C++Very efficient and ease of use

Properties – capture temporal Behavior: Assertion,Assumption, Coverage

SVA

OOP based TestbenchConstraint driven randomizationFunctional CoverageInheritancePolymorphismVirtual InterfaceQueues,Associative& Dynamicarrays

ConstrainedRandom Data Generation

Covergroup, sampling

SemaphoresMailboxes

Classes, inheritance, polymorphism

DPI interface

Coverage & Assertion API

Sequential Regular Expressions

TemporalProperty Definitions

Enhanced programming(do while, break, continue, ++, --, +=. Etc.)

Strings

Data structuresenums

MDAs

Better logical blocks –always_comb, _ff, _latch


SystemVerilog - User view

Has 5 major parts:SVD – SystemVerilog for DesignSVA – SystemVerilog AssertionsSVTB – SystemVerilog TestbenchSV-DPI – Direct Programming Interfacefor better C/C++ interface

SV-API – Application Procedural Interface for Coverage, Assertion etc.

Reference Books

(7)

Source A Pragmatic Approach to VMM Adoption 2006 for Tutorial ISBN 0-9705394-9-5, http://www.systemverilog.usand Code

CVC Copyright 2009 www.cvcblr.com


SV Design-Data Types

Enhanced data types: 2-state (bit), logic

Potential memory & run time improvement (2-state)

High level models can avail 2-state Clearer descriptions: a Verilog reg is

NOT necessarily a “register”


SV Design – Data types

User Defined types Enums – local, typedef Strict type checking, typecast

Better modeling style, easy to read, maintain

State encoding - via language (not via tool scripts)

Ease of debug, waveform


SV Design – logic modeling Verilog RTL – only always block Combinatorial & Sequential Inference by sensitivity list One of the top 10 error prone usages – more for

newbie SV: Enhanced Modeling

always_comb always_ff always_latch


What logic is being modeled?

Modeling combinatorial logic?

Use always_comb

Modeling Sequential logic?

Use always_ff


What logic is being modeled?

Modeling Latch? Use always_latch Reduces Synthesis-

Simulation discrepancies Language captures design

intent (not pragmas, tool settings)


Abstract modeling - struct

C-like struct Well proven

data structure abstraction technique

Cut down # lines



Interfaces – bread-n-butter of modern SoCs

CVC Copyright 2009 www.cvcblr.com16

Interfaces – SPI, OCP


Old fashioned hook-up–Verilog description

Too verbose Highly error

prone Maintenance

head-ache Not easy to

reuse


Typical sub-systemAHB

Master1

AHB

Master2

AHB Slave2

AHB Slave1

SoC is built using IPs – lot of ReUse Individual blocks pre-verified in standaloneMost Bugs Occur Between Blocks A good number of “Wiring” Errors

Modeled using Verilog


Hookup various blocks – the old way

Mem

_Controller

Memory

din

dout

addr

wr_rd

module mem_controller (input clk, rst_n,[7:0] dout,output [3:0] addr, [7:0] din, wr_rd);

task write();addr <= ‘haa;din <= $random;wr_rd = 1’b1;@(posedge clk);wr_rd = 1’b0;

endtask : writeendmodule

module memory(output [7:0] dout,input clk, rst_n, [3:0] addr, [7:0] din, wr_rd);always @(posedge clk)

if (wr_rd)mem[addr] <= din;

endmodule : memory

module top();mem_controller mc (clk, rst_n, dout,

addr, din, wr_rd);memory mem0(clk,rst_n, addr, din,

wr_rd, dout);endmodule

top


Interface

interface simple_bus; // Define the interfacelogic req, gnt;logic [7:0] addr, data;logic [1:0] mode;logic start, rdy;endinterface: simple_bus

module memMod(simple_bus a, // Use the simple_bus interface

input bit clk);logic avail;// a.req is the req signal in the ’simple_bus’

interfacealways @(posedge clk) a.gnt <= a.req &

avail;endmodule

module cpuMod(simple_bus b, input bit clk);

...endmodule

module top;logic clk = 0;simple_bus sb_intf; // Instantiate the

interfacememMod mem(sb_intf, clk); cpuMod cpu(.b(sb_intf), .clk(clk));endmodule


Assertion-Based Verification It’s a verification technique Instruments requirements with assertions

Clarifies requirements with executable language Enables tools to preview assertion waveforms

Instruments design with assertions Added visibility White-box testing into its internal state Provision for functional coverage information


Applying ABV - Bus based SoC

Simulate

What happened during sim? Any protocol violation? How many RW? Was xfer interrupted?


Use assertions sparingly

Non-intrusive Works with any existing flow The more you add, the more you gain


Ross Video – SV verification for FPGAs The Ross Video team created a robust verification

environment utilizing the VMM's built-in: self-checking scenario generation transaction-level channels transactors and messaging services.

Extensive use of SystemVerilog assertions (SVA)


Advantages of interface customer success stories

Better design style Disambiguate the communication Forces to have a clear interface

specification upfront – takes little more time, but saves much more later on

Reduces integration time Add Assertions to interface, every block

using it shall have to comply with the protocol

26

Impact of Interfaceinterface utopia_i;wire soc; // start of cellwire en; // enablewire [7:0] data; // datawire clav; // cell availablewire clk; // ATM layer clock

endinterface

interface cpu_i(input bit rst);wire BusMode;logic [11:0] Addr;logic Sel;wire [ 7:0] Data;logic Rd_DS;logic Wr_RW;wire Rdy_Dtack;

endinterface

module netproc(utopia_i ux, cpu_i cpu,input bit clk);

endmoduleSystem

Verilog

- 3X more compact- Fewer wiring mistakes

Verilog95

module netproc (SX_ux_soc, SX_ux_en, SX_ux_data, SX_ux_clav, SX_ux_clk, SX_cpu_BusMode, SX_cpu_Addr, SX_cpu_Sel, SX_cpu_Data, SX_cpu_Rd_DS, SX_cpu_Wr_RW, SX_cpu_Rdy_Dtack, rst, clk);inout SX_ux_soc;inout SX_ux_en;inout [7:0] SX_ux_data;inout SX_ux_clav;inout SX_ux_clk;inout SX_cpu_BusMode;inout [11:0] SX_cpu_Addr;inout SX_cpu_Sel;inout [7:0] SX_cpu_Data;inout SX_cpu_Rd_DS;inout SX_cpu_Wr_RW;inout SX_cpu_Rdy_Dtack;input rst;input clk;wire SX_ux_soc;wire SX_ux_en;wire [7:0] SX_ux_data;wire SX_ux_clav;wire SX_ux_clk;wire SX_cpu_BusMode;wire [11:0] SX_cpu_Addr;wire SX_cpu_Sel;wire [7:0] SX_cpu_Data;wire SX_cpu_Rd_DS;wire SX_cpu_Wr_RW;wire SX_cpu_Rdy_Dtack;wire rst;wire clk;

endmodule

Ecosystem around SV-FPGA

All major EDA vendors support SV for Design (simulators)

Synthesis: Synplify, leonardo FPGA vendors – need more support

Latest update pending Books, tutorials – plenty:

www.aldec.com/Downloads Trainings: www.cvcblr.com/trainings


Aldec’s Active-HDL


Design-flow manager

SV & FPGA tool support Active-HDL

SV-Design, Assertions (SVA + PSL) Interface, Debug

Modelsim-DE SV-Design, SVA, PSL

Synplify SV-Design, synthesizable constructs

Leonardo Details awaited, call Mentor

Xilinx, Altera Unknown, call your vendor


SV & FPGA advanced technologies

With adoption of SV, modern design paradigms emerge

ASIC prototyping – EVE Design systems Jasper’s ActiveDesign is one such

technology Can create waveforms for AHB, AXI etc.

right from RTL No TB required, plain RTL + ActiveDesign


Jasper’s ActiveDesign

Capture “information” during RTL design phase:

Designer makes an assumption about the latency of output, FIFO size etc. “show me a proof/witness/waveform” for such

an occurrence Can we optimize the latency to say 5 What-if I change the FIFO size to 32 here etc.



CVC Trainings –www.cvcblr.com/trainings Verification Centric Course

Comprehensive Functional Verification (CFV) Language Course

IEEE 1800 SystemVerilog for Design (SVD) IEEE 1800 SystemVerilog Assertions (SVA) IEEE 1800 SystemVerilog for Verification (SVTB) IEEE 1850 Property Specification Language (PSL) IEEE 1647, E

Methodology VMM, OVM, AVM, CDV, ABV

Workshops Gate Level Simulation (GLS) ABV Beyond RTL (ABV) Coverage Driven Verification (CDV) OOP for functional Verification

33

CVC Publications, tutorials, workshops

•Quick start guides, Tutorials • SVA • PSL• VMM

•Workshops :•Gate Level Simulation•ABV beyond RTL•Coverage Driven Verification•OOP for Verification

34CVC Copyright Protected Material, www.cvcblr.com