Winter02

Yield ManagementYield ManagementYield Acceleration Strategies for the Semiconductor Industry

S O L U T I O N SYield Acceleration Strategies for the Semiconductor Industry

VOLUME 4 ISSUE 1 WINTER 2002 $5.00 US

S O L U T I O N S

15 COVER STORY —ANOTHER DAY, ANOTHER YIELD LEARNING CYCLE

8 VOIDS, PITS, AND COPPER

54 CMP: WHERE DOES IT END?

15 COVER STORY —ANOTHER DAY, ANOTHER YIELD LEARNING CYCLE

8 VOIDS, PITS, AND COPPER

54 CMP: WHERE DOES IT END?

SPECIAL ISSUE:A Focus on Cu/low-κSPECIAL ISSUE:A Focus on Cu/low-κ

Winter 2002 Yield Management Solutions2

C O N T E N T S

S p e c i a l F o c u s

C o v e r S t o r y

15 Another Day, Another Yield Learning Cycle

A revolutionary new approach to yield learning speeds technology innovation anddevelopment.

Cover image by Carlos Hueso, KLA-Tencor

8 Voids, Pits, and Copper

Achieving a void-free copper process flowrequires a tried and tested defect inspectionstrategy.

31 The Best Laid Plans of 300 mm Fabs

Insufficient yield management planning canhandicap your 300 mm initiative.

42 Time-to-Detect Frames the Integrated Debate

To integrate, or not to integrate? That is thequestion facing many 300 mm fab plannerstoday.

54 CMP: Where Does It End?

In-situ copper CMP endpoint detection shortensprocess development.

59 The Dollar Value of Accelerated Shrinks

In most cases, metrology-driven shrinks are the most economic and effective means forreducing die-cost in demand-limited DRAMmarkets.

Long thin area

Large open area

True process window

Winter 2002 Yield Management Solutions 3

W I N T E R 2 0 0 2

S e c t i o n s

4 Editorial: Copper—The TechnologyMarathon Enabler

6 Q & A: Talking Yield—An interview with G. Dan Hutcheson, CEO of VLSI Research Inc.

30 Spotlight on Lithography

53 Yield Management Seminar Series

58 KLA-Tencor Trade Show Calendar

65 Got a Litho Question? Ask the Experts

P r o d u c t N e w s

66 TeraStar SLF77 Reticle inspection system (die to database)

TeraPro HP All-in-one reticle pattern, contamination, and MBBborder inspection capability

Viper 2430300 mm automated macro-defect inspection system

67 Surfscan SP1 Backside InspectionAutomated, non-destructive backside inspection system

µLoopInline, non-contact, electrical inspection solution

Yield Management Solutions ispublished by KLA-Tencor

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For literature requests, call:800.450.5308

©2002 KLA-Tencor Corporation. All rights reserved. Material may not be

reproduced without permission from KLA-Tencor Corporation.

Products in this document are identified by trademarks of their respective

companies or organizations.

43 5733


EditorialS E C T I O N S

Like moths to a flame, humankind is irresistibly drawntoward technology. Its pull is so strong, yet so innate,that we often don’t even question why we push so hardat testing its limits. Take Moore’s Law, for example.Why has the semiconductor industry continued to keeppace with it, as if engaged in a marathon? Certainly, noone questions the benefits of device scaling. Smallerchip designs enable more—and more complex—ICs perwafer, which leads to increased profits for the devicemanufacturer. If we take the 30,000-foot view, morecomplex and better-performing devices lead to newtechnology innovations that literally reshape the worldwe live in—from exploring the furthest reaches of oursolar system or unlocking the secrets of the humangenome, to redefining how we communicate with ourfriends and family, or even view our role in the universe.

We test the limits of technology because the pros faroutweigh the cons. Technology is THE driving factorin improving our lives. Faster and lower power-con-suming chips will one day, very soon, help replace thegas-guzzling automobile with the environmentallyfriendly electric car. Supercomputers that were devel-oped for military and defense purposes are used todayto develop advanced drugs that will help impede theprogress of ravaging diseases. In the not-too-distantfuture, microfluid biochips will be used for clinicaldiagnoses, and the list goes on.

Without continued technology investments, however,many such futuristic advances may remain embryonicideas. Let’s look at how this perspective applies to thetechnology trends we’re seeing today in advanced semi-

Copper—The Technology Marathon Enabler

conductor fabrication. If you look at chip manufacturing,you can essentially break it down into two segments:front-end-of-line, or FEOL (the transistor), and back-end-of-line, or BEOL (the interconnect). Within these,two key technology inflections are occurring. In thefront end, Intel’s newly announced depleted substratetransistors (DSTs) or silicon-on-insulator (SOI) materialsare being introduced that promise to enable faster,lower-power switching. In the back end, however, noamount of innovation can improve device performance– it can only minimize any losses that you might have. Allthe improvement you’ve achieved in the front end canbe lost in the back end, and what’s the point of havinga faster-switching transistor that consumes less power if you have a poorly performing interconnect? That’s why copper and low-κ materials are so important tosemiconductor innovation: because they help to mini-mize your losses in the back end so you can reap theperformance gains of the front end.

While copper has revolutionized chip manufacturing,it has also placed incredible challenges and pitfalls infront of us. For example, we’re hearing people talkabout void-free copper fill and deposition, but what dothey mean? The reality is that there is no such thingas “void-free”; we need to know what’s statisticallyacceptable to achieve this designation. It is not enoughjust to make decisions about what accelerants and suppressants to use and hope to achieve a “void-free”copper fill. We need to ask ourselves many otherimportant questions as well. What aspect ratios areinvolved, and at what design rules? What are thedefect density requirements? Can we have one bad via


S O L U T I O N SYield Management

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EDITOR-IN-CHIEFUma Subramaniam

MANAGING EDITORSiiri Hage

CONTRIBUTING EDITORSAparjot DehalIndira Rangarajan

ART DIRECTOR AND

PRODUCTION MANAGERCarlos Hueso

DESIGN CONSULTANTMichael Garnica

COPY EDITORDave Hattorimanabe

CIRCULATION EDITORNancy Williams

KLA-Tencor Worldwide

Yield ManagementS O L U T I O N S

per thousand vias, or only one per trillion? It’s not enough to just have a hypothesis.We need a basis from which we can accurately and rapidly measure the success inimproving our copper processes, so that we can say with 95-percent certainty that thecopper fill is statistically healthy or robust enough to meet our manufacturing require-ments. No longer can we wait until BEOL—we now need to conduct root-causeanalysis at FEOL or else place our investments at risk, stall our efforts to advance ourprocesses from development to maturity, and fail to achieve manufacturing success.

With this perspective in mind, I think our YMS Magazine readers will truly enjoy thearticles featured in this issue, including our cover story on µLoop, which represents afundamental change in how one can statistically evaluate the meaning of “void-free”copper fill. As you go through these articles in your quest to successfully face the“Brave New World” of copper/low-κ, remember that technology sets high goals forus that we may not always achieve, but will always strive to reach. And, in the end,we become all the wiser because of it. We’ve set ourselves on this path, and havingdone so, we’re loath to stray and risk losing the advancements and benefits we’vecome to take for granted.

Peter D. NunanVice PresidentYield Technology Solutions Group

Peter Nunan graduated from Lehigh University with a B.S. inEngineering Physics and a M.S. in Electrical Engineering. He beganhis career in 1979 working on DRAM process development atAT&T (currently Lucent Technologies). He has been involved in allaspects of process integration during his career while working atSiemens (currently Infineon), Sematech, and ST Microelectronics. Hecame to KLA-Tencor in 1998 to direct strategic alliance activitiesfocused on copper and low-κ. Peter is currently vice president ofthe Yield Technology Solutions group at KLA-Tencor.


YMS: In today’s fab, then,how important is faster yieldlearning, or time to yield?

DH: It’s very important, simplybecause fabs are so expensive now.Chipmakers are spending billions ofdollars for these new 300 mm fabs,the time to market is critical, technol-ogy must be brought online quickly,designs have to come to market fast– everything has to happen in amuch tighter time frame. A goodillustration of this is the loss experi-enced by one of our clients, a chipproducer. A yield problem in one oftheir fabs caused a six-month delay,costing them the entire profit poten-tial for one of their products.

Any senior manager at a chip manu-facturer today should understand theimportance of yield because if you’renot focused on yield learning, you’renot competitive. At the end of theday, that’s what determines whereyour costs lie. There is no such thingas constant yield anymore – it’s allabout how fast you can get there andhow you go about improving it. We

&AQTo help assess the impact that KLA-Tencor’s new µLoop technology willhave on the semiconductor industry,Yield Management Solutions sat downfor a one-on-one discussion with oneof the industry’s most well-known and respected independent analysts,G. Dan Hutcheson, CEO of VLSIResearch Inc. The following Q&A elucidates some of the key issueschipmakers face with respect to yieldmanagement and the yield learningcycle, which µLoop was created toaddress.

YMS: Dan, let’s start at thebeginning. What are some ofthe market and competitivepressures driving the acceler-ation of key technology transitions in the industry?

DH: One of the chief issues facingchip manufacturers today is the factthat cycle times are becomingextremely short. At the same time, thecost of bringing new technologies tomarket, like copper interconnect and300 mm wafers, has become muchgreater than ever before.

Furthermore, to fully leverage yourinvestment, you have to get product tomarket faster – today, if you miss themarket by six months, you can easilylose all the product’s profitability.

YMS: What impact does theconvergence of copper inter-connect, 300-mm, and sub-wavelength lithography haveon yield?

DH: The impact of all these newtechnologies on yield has truly beento change the whole ball game. Notonly are you no longer looking forsurface defects, since many of themare now sub-surface, but the numberof true killer defects is incredibly smalltoday. While we used to look atdefect densities of five to 10 persquare inch, per layer, we are nowdealing with small fractions. The factis, in contrast to 10 years ago, theindustry is not chasing particles but,rather, actual process problems. It’ssomewhat analogous to looking for aneedle in a haystack, within anotherhaystack.

Talking Yield with Dan Hutcheson

Dan is president and CEO of VLSI Research Inc. He is a recognized authority andwell-known visionary for the semiconductor industry, whose career experience spans morethan twenty years.


the lower cost to your customersdirectly, allowing them to satisfy theircustomers faster. Either way, you winin the marketplace because it makesyou more competitive, and makesyour customers more competitive.

YMS: How would you rankµLoop against the variousyield-management advancesyou’ve seen over the lastcouple of decades, based onits potential?

DH: The last big thing in yieldmanagement was yield management.Chipmakers went from looking atwafers with microscopes to automatingdefect inspection and classification.µLoop is really the next big stepbecause it’s a new paradigm forimproving learning and yield in thefab. It’s really an interesting new wayof doing things. Instead of looking atan optical image, which has beendone before, you’re looking at aSEM-based voltage contrast image.The difference is that when you lookat it electrically, it tells you whether aproduct is good or bad, or if adefect is really a killer. That hasalways been the promise of e-beamprobing in this space, but the problemwith e-beam is that it is classically tooslow. That’s the big challenge thathas to be overcome – and that’s really the promise of µLoop. It’s moresignificant than a lot of the otherthings we have seen in the pastbecause at the end of day, yield iseverything.

often talk about cost of ownership,cost of producing the wafer, but if youyield nothing, you have no revenues tooffset that cost. The fact is, profits comefrom the yield part of the equation.

YMS: In your opinion, howdoes KLA-Tencor’s new µLooptechnology stack up againsttoday’s existing technologiesaimed at yield learning?

DH: Clearly, µLoop technology isthe next step in yield improvementand yield learning because, for thefirst time, we’re breaking away fromvisual inspection in the fab and cannow do electrical testing in the fab.The technology brings all of theadvantages that you get with electricaltest, of identifying true killer defects,inside the fab, so you don’t have towait until the wafers are out to per-form electrical test. That’s not only arevolution in yield management andyield learning – it’s a revolution in getting yield cycle times down.

YMS: Why is that so significant?

DH: If you can’t do that, your fabis going to have a yield learning dis-order. Currently, it takes weeks ormonths to get wafers out and to elec-trical testing. Ten to 20 years ago, noone would have ever have acceptedthe notion of test as a means ofimproving yield in the fab. Yet now,senior executives in chip companies,all the way up to the CEO level, are talking about how they’re using

S P E C I A L F O C U S

electrical test as a way to drive fabyields because electrical test is theonly way to sort killer defects fromdefects that don’t affect your fab. Youdon’t want to spend a lot of moneyand waste a lot of engineering effortto find defects in the wafer that don’tcause a problem, that don’t kill theyield – that really don’t matter, eitherto you or to your customer.

YMS: What’s the disadvan-tage of waiting until electricaltest to identify yield problems?

DH: It’s simple: time is money ina fab. For example, suppose you’rea chipmaker running wafers at therate of 7,500 per week, and youwait six weeks for those wafers. Bythe time a yield loss is detected,45,000 wafers will have alreadybeen processed. If there is a yieldproblem, you must bring the fix intothe loop, then wait another six weeksto see if the problem is solved. Now,you’re up to almost a hundred thou-sand wafers processed – if you lost,say, $10 per wafer, you’ve lost over$1 million. We’re talking aboutpotential losses of hundreds of millionsof dollars if you extrapolate that outacross all of the products and productlines.

So, if you can shrink these long cycletimes that cost you hundreds of millionsof dollars by using µLoop technology,you can save those costs and expensesby simply bringing those revenuestreams back in. Or, you can transfer


The introduction of copper dual damasceneprocessing into integrated circuits hasbrought about a host of new defectivityissues, especially those related to voidingand pitting. These defects must be under-stood and eliminated to achieve competi-tive manufacturing yields and assure devicereliability.

Void characterization in copperprocessesAs part of a joint development copper pro-gram to develop 100 nm logic processes,KLA-Tencor and Texas Instruments workedtogether to develop new defect inspectionstrategies.

The most important yield limiting defecttypes with copper are voids. Almost natu-rally, copper voids seemed to group intotwo distinct categories: optically detectablevoids that are on the surface of the copperlayer, and sub-surface voids, which aredetectable using e-beam voltage contrastinspection (Figure 1).

Voids, Pits, and Copper

Judy B Shaw, Richard L. Guldi, Jeffrey Ritchison, Texas Instruments IncorporatedSteve Oestreich, Kara Davis, Robert Fiordalice, KLA-Tencor Corporation

As circuit features have scaled below 0.25 micron, the resistivity of aluminum has become an obstacle to integration. Withforty percent higher conductivity than aluminum – and far more resistance to electromigration—copper holds the key to dra-matic improvements in circuit density, speed and reliability. Integrating copper into the IC manufacturing process, howev-er, is extremely challenging. Copper can diffuse into silicon and dielectrics, causing shorts or leakage, which can impactdevice performance and yield.

Cu/low κS P E C I A L F O C U S

Surface pit

Sub-surface void

Figure 1. The most critical copper voids can be grouped into two cat-

egories—optically detectable pits/voids on the surface of the copper,

and sub-surface voids not observable from the surface, but detectable

using e-beam voltage contrast inspection.


Void formation may stem from electroplating, annealing,or polishing steps. It is important to identify appropriateinspection tools to characterize the process stepsresponsible for void generation in order to quicklydetermine root causes and optimize process capability,process control, and tool maintenance.

An advanced 0.13-micron, copper dual damascene processwas used at Texas Instruments’ Kilby DevelopmentCenter (KFAB) to generate the samples in this paper.The gallery of defects generated by this type of process(Figure 2), shows some embedded and surface particles,but primarily voids or pits dominating the defect Pareto.

Micropartioning strategies determineroot causeAt the time that Texas Instruments and KLA-Tencorundertook the studies of copper defects, the process ofrecord had brightfield inspection as part of the processloop, and this was done after copper CMP. Althoughbrightfield inspection revealed many defects—some yieldlimiting and some less important—the sheer numbers ofdefects and the presence of patterning and underlyingdefects made surface void source partitioning difficult.

To partition the source of these defects, a darkfieldinspection was carried out using a KLA-Tencor AIT III,and the first inspection was performed after CMP.Immediately, a high defect count and an obvious swirlpattern of voids were noted. The defect Pareto revealedthe highest two categories to be voids and long pits,

which are essentially another form ofvoids. Together, these two categoriesaccounted for well over 70 percent ofthe Pareto. Based on knowledge of theprocess and the process tool, the voidformation appeared to show a CMP sig-nature (Figure 3). The first step in mov-ing towards understanding the voidswas inspection after electrochemicaldeposition (ECD). Post ECD inspectionshowed the swirl pattern to be subtler;voids and pits were also present, albeitsmaller and shallower than after CMP.The next step was to overlay ECD andCMP defects on the wafer map usinganalysis software. Defect overlay con-firmed that the post-CMP voids in theswirl pattern had their root cause in theECD, and were enlarged and revealed bypolishing and post-CMP clean (Figure 4).

In this and other examples we haveseen that darkfield inspection is quitesuccessful for rapid and focused engi-neering analysis in the copper loops.This is because oblique illuminationminimizes the detection of previous


Copper Defect Gallery

Process StepILD Dep (5 Step)

ILD CMP (Optional)

Via Photo

Via Etch

Trench Photo

Trench Etch(BARC, Trench, Etch Stop)

Barrier/Cu Seed Dep

Cu EP

Cu Anneal

Cu CMP

OpticalImages

SEMImages

Void

Void

Void/Rip Out

DefectiveVia

EmbeddedParticle

BARCUnder-Etch

Seam FromTopography

Figure 2. This figure shows a gallery of typical defects generated during copper dual

damascene processing. Voids or pits dominate the defect Pareto, although a few other

sur face-type defects are present at a lower level.

Post

-CM

P Pa

reto

Void

Long

Pit

Part

icle

Scra

tch

Othe

r

Mis

sing

Mat

eria

l

70%60%50%40%30%20%10%

0

Post-ECD Post-CMP

ECD Void

ECD Void ECD Void

Void Long Pit

Figure 3. Darkfield inspection implemented post-ECD and post-CMP,

using KLA-Tencor’s AIT III, was utilized to partition the source of patterning

and underlying defects.


RandomMode Logic

Array ModeSRAM

Array ModeDD Test CHIP

Physical (non V.C.)

Physical (non V.C.)

Figure 5. Sub-surface voids have many potential causes and are

electrical in nature. These sub-surface voids were detected using the

eS20XP’s voltage contrast methodology.

layer issues, as well as other inspection “noise,” so thatwe effectively focus just on the current layer.

Eliminating sub-surface copper voidsThe second type of copper void is very different. It is asub-surface void and, generally, these types of defectsare related to materials or process integration issues. It isabsolutely essential, during the technology develop-ment phase, to have a tool that finds these sub-surfacevoids, enabling screening experiments and quick elimi-nation of these voids. This is critical to ramping a cop-per damascene process, because voids must be eliminat-ed before the process flow is set, and before it is quali-fied. If the metal lines contain copper voids, they standthe risk of becoming opens, resulting in device failure.In order to capture these voids at this very importantjuncture, KFAB used KLA-Tencor’s eS20XP e-beaminspection tool (Figure 5).

Random or array mode: when it worksThere are a number of techniques for implementing e-beam inspection to inspect sub-surface voids. The firstoption is random mode inspection of the logic areas onthe product chip. This inspection is very useful to per-form, as it provides considerable information. However,

due to the random nature of the pattern, it is quite dif-ficult to perform an effective analysis of root cause. Itwould be quite time-consuming for a failure analyst totake this information and determine the defect thatcaused the electrical opens.

The next option in implementing e-beam inspection isto utilize the array mode to inspect the memory areasof an SRAM chip. Array mode analysis is easier thanrandom mode, because the defects of interest readilystand out in a voltage contrast SEM, but failure analysisis still non-trivial because of slight variation in SRAMdesign among different products or different technologygeneration, requiring considerable skill and time toperform the failure analysis. The most useful analyticaltechnique is array mode inspection of defect densitytest die, which affords straightforward failure analysis,since the analyst can e-beam scan the defective chainalong its length to precisely locate the electrical failuresand then port those locations to a focused ion beam(FIB) microscope for cross-sectioning (Figure 6).

The work shown in the remainder of this paper isfocused on the array mode inspection of a defect testchip. The test chip is grounded using a contact mask asthe first pattern. This method makes it very easy to seewhere the defective via is. In the normal case, when thee-beam inspector scans the wafer, the grounded struc-ture will appear bright due to the secondary electronemission. However, if a via void is present, the sec-ondary electrons are effectively extinguished and thatportion of the chain will appear dark. The inspectionsystem’s extraction field attracts the secondary electrons.


Stepchart

Post-ECD

Post-CMP

Common defects show"swirl" pattern Same Defect

Missing Count1448

1142

Total True Defects: 306Displayed Total Defects: 2431Displayed True Defects: 306 6052M1PL JDP_M1CMP_SW

1644 1644 32883288

306/2978

Adder Count

Figure 4. Defect overlay confirmed that the post-CMP voids in the swirl

pattern had their root cause in ECD and were simply being enlarged by

polishing and post-clean. Darkfield inspection is quite successful for

rapid engineering analysis in the copper loops, because oblique illumi-

nation minimizes the detection of previous layer issues and other

“noise,” enabling effective focus on current layer problems.


They are replaced from ground in the grounded structureand the floating structure charges positively. Secondaryelectrons from the floating structure have a lower netenergy and are attracted to the positive surface charge,limiting the number that make it to the detector.Hence, these defects look dark (Figure 7). In the case of Figure 8, a surface SEM detected nothing physicallywrong, but voltage contrast imaging suggested thatthere was an electrical open below the surface. That isexactly what the FIB cross-section revealed—a void inthe previous layer metal, the via landing pad.

Screening ExperimentsAfter the practicality of e-beam inspection was estab-lished, this technique was applied to two experimentalproblems. The first experiment investigated the effectof ECD seed conditions, pre-ECD rinse, and post-plat-ing anneal on voids, while the second examined theeffect of seed thickness and post-plating anneal.

Experiment 1 – Evaluating via integrity at the wafer levelExperiment 1 was conducted to evaluate via integrityat the wafer level using the eS20XP under variousinterconnect process conditions. Three process variableswere screened: the ECD seed conditioning, the pre-ECDrinse conditioning, and the post-ECD anneal. Theexperiment was designed for 0.13 µm dual damascenecopper/low-κ via structures. Wafers were inspectedusing the eS20XP. The outcome clearly showed thatthe same result could be achieved with the eS20XPinspection that otherwise would have only been detectedwith electrical via resistance testing at final test (Figure 9).

The experimental data show that the post-ECD annealconditions drove the experimental results. Anneal Bhad several times as many defects as anneal A. Theother two process variables—the ECD seed conditionand the pre-ECD rinse condition—had negligibleeffect on the defect counts. Another valuable piece of


VC DefectsElectrical Opens

Figure 6. Utilizing a defect density test chip in conjunction with the

eS20XP’s voltage contrast methodology enables easy detection of

defective vias.

Metal 2

Void in Landing Pad

Metal 1

Figure 7. In this example, top surface inspection showed nothing

physically wrong; however voltage contrast e-beam inspection and

subsequent FIB revealed the presence of a high-resistance, sub-surface

connection due to a void in the previous layer metal at the landing pad.

Figure 8. This figure shows types of electrical disconnections. The

image on the left shows a problem arising from a stopped via etch or

under etch; the image on the right shows a blocked trench etch at the

previous metal level.

Under-etched Via

Metal 3

Metal 2 Metal 2

Blocked etch, previous layer

Total Defect Count

eS20XP Defect Scan Summary

Anneal "A"

Anneal "B"

Wafer Map

Figure 9. This summarizes the results of the first experiment, which

compared the effect of ECD pre-conditioning anneal, pre-ECD rinse,

and post-ECD anneal on copper voids. The vast majority of defects

found by the eS20XP were voltage defects as opposed to surface or

particle defects.


information was also found in this data—a strong across-wafer radial dependency of the defect counts. The vastmajority of the defects were at the edge of the wafer.

The next step with these same wafers was to probe thevia chains; these results were consistent with voltagecontrast data. The via chain cumulative percentage plotshowed fall-out under anneal B conditions. Anneal Ahad a relatively healthy, robust distribution of via resis-tance, whereas anneal B’s distribution was poor, withmany outliers. This probing revealed the same sort ofvoids as seen before. Anneal B had either voided viaplugs or voids in the underlay landing pad (Figure 10).

Experiment 2 – Evaluating via integrity under thermal stressExperiment 2 was conducted to evaluate via integrityunder thermal stress using the eS20XP. The experimentwas again set up on 0.13 µm dual damascene copper/low-κ via structures. The wafers were exposed to fourthermal cycles post CMP. An eS20XP inspection wasperformed after each of these cycles. In this screeningexperiment there was only one process variable—theECD Cu seed thickness (Figure 11).

A number of results were found in this experiment.First, there was a strong wafer-to-wafer effect. The samespatial effect of center to edge found in Experiment 1was seen again. Seed thickness A produced lower defectcounts. The defective vias were again confirmed to havesubsurface voids. Seed Thickness A wafers have the mostconsistent counts as well as the lowest defect countsafter four anneals. Seed thickness B wafers had muchwafer-to-wafer variability, generally with higher counts.One seed thickness B wafer, wafer 5, had very highcounts. Counts increased greatly with the number ofanneal cycles. Wafer 5 was then taken to the FIB tool(Figure 12) and, for the third time, it was demonstratedthat voids were induced by anneals, both in the plug aswell as in the underlying pad.

ConclusionBoth optical and e-beam inspection methodologieshave proven useful for copper void detection. AIT IIIinspection, with its oblique angle of incidence, is veryeffective in detecting surface voids, helping to charac-terize the ECD process, which is responsible for gener-ating most of the voids. Voltage contrast inspection ofdefect density test chips using eS20XP has a unique andcomplementary application: to detect subsurface voids.The combination of optical and e-beam inspectiontools enables faster detection and analysis of coppervoids, leading to accelerated learning cycles.


100%

70%

50%

30%

00 4 8 10

(Ω/Via)

Anneal Condition A

Anneal Condition B

Anneal B

Anneal B

Figure 10. Electrical probing confirmed the e-beam inspection results,

with anneal B giving a high resistance fail in the via chain cumulative

percent fail, compared to the relatively healthy via fail distribution for

anneal A.

Defe

ct C

ount

Time

0 1x 2x 3x 4x

wfr 1 A

wfr 3 A

wfr 2 B

wfr 4 B

wfr 5 B

wfr 6 B

Thickness

eS20XP Via Void Evaluation

Figure 11. The two wafers having thickness A maintained a low via

fail rate throughout the entire annealing sequence.

Moderate VoidModerate Void

Extensive VoidVoltage Contrast

Example

Figure 12. This figure shows FIB cross-sections of three dif ferent volt-

age contrast voids after the fourth anneal. It was found that intermedi-

ate temperature annealing leads to moderate void formation at the

bottom of vias, resulting in voids that are not as fully developed as

those arising from higher temperature anneal. However, a few exten-

sive void developments were also seen, as shown in the lower right

corner of this figure.

©2001 KLA-Tencor Corporation

InLine Electrical Inspection • Non-Contact • Killer Defect Identification

Accelerating Yield

The Switch Is On.

www.kla-tencor.com/microloopVisit our site for a µLoop webcast presentation.

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a y ,a n o t h e r y i e l d

l e a r ni n

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TMI nt r o d u c i n g µ L o o p.


15Winter 2002 Yield Management Solutions

Defect Management for300 mm and 130 nmTechnologies

Part 3: Another Day, Another Yield Learning Cycle

Kurt Weiner, Todd Henry, Akella Satya, Gaurav Verma, Richard Wu, KLA-Tencor Corporation

Oliver Patterson, Brian Crevasse, Kris Cauffman, William Cauffman, Agere Systems

The back-end-of-line (BEOL) interconnect process increasingly poses a formidablechallenge for yield groups striving to attain high yields and profitability intoday’s competitive market. The combination of smaller design rules and vastlymore complex processes highlights the need for a radically new approach to yield learning. This article, the third in a series focused on effective defect management, discusses a revolutionary new methodology for yield learning thatsignificantly shortens the yield learning cycle and offers the ability to exclusivelycapture yield limiting defects. Through its special design, the method combinesnon-contact electrical test with inline physical defect inspection, significantlyreducing the engineering resources required to identify the problematic defect typeand establish root cause, and the time it takes to validate a successful fix. Thisnew methodology, which enables unprecedented breakthroughs in yield learning,gives manufacturers tremendous advantages in productivity and substantial cost savings, ultimately speeding the development of future integrated circuitinnovations.

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16 Winter 2002 Yield Management Solutions

IntroductionSeveral years ago KLA-Tencor recog-nized a critical gap in a fab’s ability tominimize the time-to-market for a newtechnology: the speed and effective-ness of the yield learning methodologyfor the back-end-of-line. In response,KLA-Tencor developed a new approachbased on its powerful e-beam inspec-tion and defect review technologies.

KLA-Tencor’s µLoop technology,which enables faster yield learning,leverages existing engineeringresources to allow earlier technologyintroduction at significantly higheryields. Effective use of this technologyalso results in an accelerated yield rampand higher, mature technology yields.This earlier introduction of technol-ogy, coupled with an accelerated yieldramp, results in increased profitability,as semiconductor manufacturers areable to take advantage of the highermargins that are available early in thelife of new leading edge technologies.

What are the underlying market andtechnology factors driving the tran-sition to this new method?

The Value of Accelerated YieldLearningIn Figure 1, a typical BEOL inter-connect for quarter-micron technolo-gies is compared with a sub-180 nmprocess to show the qualitative dif-ference in the number of vital con-nections necessary to produce aworking product. The number ofinterconnect levels—as well as thedesign complexities—within thesub-180 nm node increases signifi-cantly. Compounding the problem,each successive technology genera-tion requires faster time-to-yield toremain profitable. The value ofaccelerated yield learning is clear: athree-month reduction in the time-to-yield of a process means hundredsof millions of dollars in increasedprofitability, with the added benefitof the higher selling prices associated

by speeding the yield learningprocess, especially in the criticaldevelopment and early ramp phases.For IC manufacturers and their cus-tomers, time-to-market and time-to-profit are limited by the yieldlearning cycle time and quality ofelectrical defect data as reflected inits ability to drive learning.

BEOL Challenges at Sub-180 nmTechnology NodesThe problem of speeding time-to-yield is non-trivial. In current andfuture deep-submicrometer technol-ogy nodes, kilometers of wiring arerequired at each metal level to inter-connect the millions of transistors inan advanced integrated circuitdesign. For acceptable yields, anelectrical defect density (D0) of lessthan 0.15 defects/cm2 is required.Achieving and maintaining this D0necessitates the capture, analysis,and understanding of virtually everyyield limiting defect type in theprocess line. Unfortunately, the crit-ical size of killer defects is decreasing(scaling with the CD of the process)and reaching the size of materialsdefects such as metal grains and lineedge roughness. Finding and elimi-nating the electrical “short” and“open” defects while ignoring thenon-relevant defects induced bymaterial anomalies is particularly

with leading-edge product versustrailing-edge product. In compari-son, the same improvement in yieldlearning applied to the manufactur-ing phase equates to only millions ofdollars. This difference reflects thephilosophy of basic quality improve-ment processes: namely, trying to fixthe defects during the designphase—where it is more cost-effec-tive—rather than waiting to doingthis in the production phase. Greatercomplexity combined with fastertime-to-yield can only be achieved

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Voltage Contrast Inspection

PhysicalCharacterization

Figure 2. Critical subsurface via defects such as this can be detected using e-beam inspection.

Figure 1. The number and complexity of inter-

connects increases significantly in a sub-0.18 µm

process compared to a 0.25 µm process.


at which engineers can negotiatethrough the various sections of thispath will directly impact how quicklyyield problems can be solved.

Step 1: Yield Limiting DefectIdentificationIn this step, a Pareto of the defecttypes contributing to the yield prob-lem is established. This Pareto ofyield limiting defects is used to prioritize yield improvement effortsto insure resources are placed wherethey will have maximum impact onimproving yield performance.

Step 2: EngagementAs soon as the yield limiting defectPareto has been established, the key tosuccess will now hinge on developinga solution that will eliminate theproblematic defect type from the over-all population. Process and/or inte-gration engineers must be “engaged”in the activity of developing ideasfor changes to fix the problem.

Step 3: Hypothesis TestingThe impact of the proposed changesare then evaluated through carefullycontrolled studies designed to assessif the independent variables, whichcould be process or integrationchanges, quantitatively reduce theyield limiting defect type and/orimprove the electrical performance.In total, the elimination of the yield-detracting defect requires at least twoiterations of these hypothesis-testingexperiments (cycles of learning).

Step 4: ImplementationTimely introduction of the newprocess or integration fix is also

necessary to accelerate the yieldimprovement rate.

Current yield learningmethods Currently, three methods dominatethe industry for BEOL yield learn-ing: the product loop, the memory(or SRAM) loop, and the short loop.These are typically applied in steps 1and 3 of the yield learning cycle.

Product LoopThe advantage of using real productfor the yield learning cycle is thatthe output statistic is the one that isof most interest. Engineers want tounderstand if the proposed changeswill result in improved yield perfor-mance. Using product for yieldlearning has several obvious disad-vantages: long learning cycle times;difficulty in isolating the yield lim-iting defect types; and, the fact thatlarge sample sizes are necessary toassess the impact of the processchange on improving the productyield. Creation of an accurate yieldloss Pareto on product wafers is adifficult and time-consuming—ifnot impossible—task on logic tech-nologies. First, electrical testing toevaluate the experiment cannotoccur until the product is complete,which can take several months,depending on the complexity of theprocess. Fault identification, whichis much more difficult on non-bitmappable devices, is extremelytime consuming and may not resultin an accurate yield loss Pareto.

Aside from difficulties with faultisolation, product yield performancedoes not provide an ideal metric forhypothesis testing. While the yieldmetric is the one that ultimately isneeded to validate improvedprocesses, it often does not providethe level of granularity that is neededto assess the effectiveness of pro-posed process changes. Yield distrib-utions tend to be highly variable,

difficult in the BEOL, and yet essen-tial to attaining profitable produc-tion yields in a semiconductor man-ufacturing line.

A second and equally daunting chal-lenge concerns the 10s to 100s ofmillions of vias that provide connec-tions between each level of metalinterconnect. The vast majority ofthese vias are not redundant, result-ing in a dramatic hit to yield if morethan a few vias per billion are elec-trically defective within a givenlayer. Some via failures are caused bysurface defects that can be detectedusing conventional inspection tech-niques. However, a rapidly increasingnumber are subsurface, as shown inFigure 2, and can only be detectedeffectively using electrical measure-ments. Capturing this buried type ofvia defect has been a major driver forthe implementation of e-beaminspection in recent years.

These new challenges place a burdenon the yield and process groups toimplement the fastest and mosteffective BEOL yield learningmethod possible.

The yield learning cycleToday, as in the past, all defect issuesare resolved through yield improve-ment methods organized in repeti-tive sets of steps or yield learning“cycles.” The start of the cycle istypically triggered when yields arerunning below a target goal. Themethodology to resolve most yieldproblems follows a common path,which includes identification,engagement, hypothesis testing, andimplementation (Figure 3). The rate

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Low Problem Engagement Hypothesis Implementationyields identification of processing testing of solution

“what to fix” & integration

Figure 3. A typical yield learning cycle.


2. Separating the yield limitingdefects from the total defect pop-ulation; and,

3. Capturing both the random andsystematic defects that are createdwhen the full process flow is run.

KLA-Tencor’s µLoop methodologyaddresses all of these issues by com-bining non-contact electrical test withinline physical defect inspection toproduce the fastest root-cause analysismethod available in the industry today.This new approach represents an inte-grated turnkey solution to electricalinspection that increases the speedand effectiveness of root-cause analysisby detecting and imaging electricaldefects quickly, while minimizing theengineering resources required togather and assimilate the root-causedata.

The components and overall processThe integrated approach comprisesthese components:

1. Proprietary test chip designs

2. eS20XP e-beam inspection system

3. µLoop Controller integrateddefect characterization, analysis,and reporting system

The patented test structures for thechip are designed to meet the cus-tomer’s design rule and chip sizerequirements. Through close inter-action with the customer’s design,module, integration, yield, and testengineers, the test chip can be madeto address many defect issues relatedto product layout, as well as specificprocess-related problems and processwindow limitations. As a result, thelayout and composition of the chip istailored to the types and densities ofrandom and systematic defect mech-anisms of interest to the customer.The chip can then be included asdesired on either test wafers or prod-uct wafers, and may be as large as anentire die or small enough to fitwithin the scribe lines.

due to the impact of many differentfactors; the influence of the indepen-dent variable under test on yield isoften hidden by the “noise” created byall these other environmental factors.The large variation in the distributionnecessitates the use of larger samplesizes to validate a quantitative dif-ference between defect populations.

Memory LoopThe memory or SRAM cycle func-tions in a similar manner as theproduct cycle, except that a chip withbitmappable memory structures isused. The advantage of this cycle isthat it provides an approximate loca-tion for each of the electrical defects.The yield limiting defects can beisolated to a specific layer with classicde-processing techniques. Accurateyield loss Paretos can be developedusing this procedure if given enoughtime. Engineers can use this infor-mation to “identify” what defecttypes need to be reduced to improveyield performance.

However, the bitmap information,while useful in problem identifica-tion, cannot be used effectively togauge statistical differences betweenpopulations in hypothesis testingexperiments. The labor-intensivenature of the de-processing makes itimpractical for assessment of hypoth-esis testing experiments. Therefore,memory loop improvement experi-ments use yield as the dependentmetric to assess improvement, andsuffer the same sample size problemsand long time to solution as theproduct loop.

Short LoopShort loops, in contrast, do notinclude front-end processing and, so,require only 1 to 2 weeks of process-ing before reaching electrical test.These loops use defectivity test chipsinstead of product devices and aretypically limited to three lithographylayers (two interconnect and one via).The learning cycle time is much better

than what can be obtained fromproduct wafers (2 to 3 weeks versus30 to 60 days). Here as with thebitmap loop, the electrical test datamay be overlaid with inspection dataso that images of potential killerdefects may be collected with a SEMreview tool. The effectiveness of thisprocess is limited by the sensitivityof the inline inspection tools to cap-ture the yield limiting defect types.If the spatial correlation between theinline inspection and electrical datais good, an accurate yield loss Paretocan be developed to drive yieldimprovement efforts and quantita-tively assess the improvement at theyield limiting defect level inhypothesis-testing experiments. Ifthe correlation is poor, the techniquedoes not provide the needed infor-mation to determine what needs tobe fixed. The second problem withthis approach is that the short loopprocess does not capture all problemsthat arise during the full flow process.Finally, if the short loop vehicles arenot designed with product-likestructures, many of the systematicdefect mechanisms that are relatedto layout will not be captured.

A new method for yieldlearning Several years ago, KLA-Tencorbegan design of a new methodologyto address many of the issues thatlimit the efficacy of the commonlyused yield learning methods. In par-ticular, the R&D group focused ondeveloping a much faster systemthat would quickly identify andquantify the killer defects, allowingmore time to be spent on fixing theproblem than trying to find thesource. The following underlyingproblems were the key drivers:

1. Obtaining the inspection toolsensitivity necessary to capturesub minimum space and highaspect ratio defects;

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of test structures optimized for per-formance and speed-of-inspectionusing KLA-Tencor’s e-beam technol-ogy (see the sidebar on voltage con-trast inspection). By using a set ofproprietary Area-Accelerated™ teststructures, throughput enhancementsof 10 to 25 times that of standardarea-based e-beam inspections areavailable. A simplified example ofthis new class of test structure isshown in Figure 5. In this structure,

which addresses interconnect opensand shorts, grounded and floating tinesare inter-digitated similar to a comb.Leveraging the properties of voltagecontrast inspection discussed in thesidebar, these new test structuresrequire inspection of only a smallregion at the bottom of the teststructure. Electrical defects presentalong the length of the tine are trans-mitted down the tine and sensedthrough a large voltage contrast defectthat appears as a deviation in thenormal alternating grounded/floatingtine pattern. Through this patenteddesign both shorts and opens can bedetected. The CD of the process setsthe minimum sensitivity of the teststructure measurement. Therefore,the test structures provide highthroughput (through sampling) athigh sensitivity (through voltagecontrast defect amplification).

Grounded via chains are an alternatetype of test structure that includelarge numbers of individual vias,offering a quantitative measurementof any systematic issue that causes aburied open in the via structure (alsosee the sidebar on random and sys-tematic defect types). These structuresare advantageous in that probing ofeach individual via is not required;again a voltage contrast defect willbe detected at the bottom of the teststructure if any via is open.

Figure 4 shows a general schematicof the µLoop cycle. The test chips aremanufactured with the standard BEOLwafer processing. Upon completion ofthe fabrication of each interconnectlayer, the eS20XP e-beam inspectionsystem first captures the criticaldefects, and then the µLoop Con-troller characterizes the defects andprovides customized defect and yieldsummary reports. These reports eitherhelp identify what defect problemneeds to be fixed, or help assess theeffectiveness of a process and/or inte-gration change on eliminating theproblematic defect type (steps 1 and 3in the yield learning cycle describedearlier). Experiments using the µLoopvehicle continue until the yieldproblem is resolved. Upon resolutionof the current problem, resources arerefocused on the next item on thePareto.

The test structures and e-beaminspectionThe µLoop solution is based on theconcept of voltage contrast inspection

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Figure 4. µLoop uses custom test structures, e-beam inspection and an integrated defect charac-

terization and yield analysis system to complete the yield learning cycle.

Intralayer Shorts/OpensInterlayer Shorts Via Opens (chains) Via Opens (single)

Figure 5. This new class of test structure takes advantage of the properties inherent to voltage

contrast inspection.

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Another key advantage of thismethodology is that it is non-con-tact. Because there is no need foractual probing, there is less risk ofcontamination induced by the mea-surement, and thus the same wafercan be probed at all levels of theinterconnect process.

µLoop Inspection MethodologyThe complete µLoop inspection usesa three-step process:

1. Assess

2. Identify

3. Classify

Winter 2002 Yield Management Solutions

Step 1) AssessThe assess step is an Area-Accelerated e-beam inspection thatquickly identifies the electrical defectsacross the entire wafer. The through-put of this inspection is maximizedthrough the design of the test chip;due to the nature of voltage contrast,a high-sensitivity inspection is notrequired, and all of the VC signa-tures for a particular type of struc-ture can be seen by sampling a smallarea of the chip. Because the teststructure is divided into thousandsof individual tines, rather than alarge-area comb, the exact locationof the defect in one dimension can bequickly identified. During this scan,both electrical and any type of phys-ical defect in the inspected area aredetected. Because physical defects areconsidered non-relevant in this stepof the µLoop methodology, they arefiltered out by the µLoop Controller,and the final result is a list of theelectrical defects and their locations.

Step 2) IdentifyThe identify step finds the associatedphysical defects (see Figure 6). Theprevious step provided the x-coordi-nate of the physical defect, andalthough the y-location is not exact, itis bounded by the test structure height.Using this information, a customrecipe is automatically generated foreach wafer that is assessed. To facilitatethe identify inspection, the wafer isrotated 90 degrees. This custom recipeprovides an inspection test plan thatincludes only a small region aroundeach defect detected during theassessment scan. Because the numberof electrical defects is usually quitelow, the total area inspected is verysmall (typically much less than 1percent of the total wafer). The smallinspected area helps to offset theimpact on the throughput of thehigher sensitivity conditionsrequired for determining the exactlocation of the physical defects causingthe critical electrical failures.

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Voltage contrast inspection Voltage contrast is inherent to all e-beam inspection technologies, but is onlycreated under specific kinds of conditions. During inspection, a conductivematerial is exposed to a beam of electrons, and a number of the incidentelectrons collide with the atoms of the metal. A certain fraction of the collisions (depending on the type of metal) produce “secondary” electrons,which are re-emitted from the surface of the conductor at a much lowerenergy than that of the incident beam. This fraction of secondary electrons isalso a function of the incident or “landing” energy of the primary electronbeam and can be controlled to be less than or greater than one. If the con-ductor is isolated or “floating,” the difference in secondary electrons emittedversus primary electrons absorbed produces a net charge over the entireconducting node. When the landing energy is set so that the charge accu-mulated on the floating conductor is positive (more secondary electronsemitted than primary electrons absorbed), the node builds up a charge untilthe potential is large enough to inhibit the emission of more secondaryelectrons, and the node attains a static voltage. Secondary electrons cancomprise up to 80 percent of the imaged electrons so, in this situation, thenode can appear dark when imaged. In contrast, if the node is connected toa source of electrons (such as a grounded substrate), electrons from thesource can flow to neutralize the charge build-up. This “grounded” nodenever builds a positive potential and so appears brighter than the floatingnode when imaged. This brightness difference between adjacent nodes canbe used to indicate the relative voltage difference between the nodes, andcan indicate the presence of an electrical defect.

Typically, voltage contrast detection is used to complement physical defectdetection in an e-beam inspector by providing some electrical informationon the product defectivity. Use of voltage contrast defect detection alone toanalyze overall product electrical yield is a complex process. However, voltagecontrast can be used effectively with specially designed test structures topreferentially detect electrical defects, while rejecting physical defects that donot cause electrical failures. In this mode, voltage contrast defect detectionhas two important advantages: first, the presence of voltage contrast is anaccurate indicator of an electrical failure on the node, providing a means forelectrical inspection. Second, because a conductive node assumes the samepotential across the entire node very quickly, regardless of size, voltage contrast can be used to both amplify very small physical defects into verylarge voltage contrast defects and to transmit the defect signature to a common region within the test structure. Using the defect amplificationand transmission traits of voltage contrast, a class of test structures that ishighly optimized for throughput and sensitivity can be designed.


Step 3) ClassifyThe classify step uses the informa-tion from the previous two steps forconfirmation and classification of theelectrical and physical defects. The

µLoop Controller takes images ofeach defect, and the user classifies thedefects using an image gallery. Allthe data is stored and tracked by theµLoop Controller, enabling various

types of analyses that quantify theyield killers.

µLoop enables the generation of use-ful Pareto information in a muchshorter time than with the conven-tional loops. The methodology alsoidentifies and classifies 100 percentof the electrical defects on the testwafers. Obtaining comparable infor-mation would take prohibitivelylong using the standard loops andrequired failure analysis.

Integrated Analysis and ReportingCritical to the success of any yieldlearning cycle is the ability to quick-ly generate useful information forimproving yield. Upon completionof the assess, identify, and classifysteps, the µLoop Controller automat-ically generates a defect Pareto anddata reports. In this way, the criticaldefect types and their quantitative

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Outputs

Inputs

LW=0.24/LS=0.72

251.00 248.00

15.00 13.00

LW=0.24/LS=0.48

Figure 6. µLoop finds the physical defect associated with the electrical failure.

Process Margin

Linespace (µm)

100

CD0

Stru

ctur

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(%)

Yield Summaries

18

12

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01 2 3 4 6 7 8 9 10 11 15 16 17 18 19 21 22 23 24 25

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of D

efec

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0 Type 1 Type 2 Type 3 Type 4 Type 5 Type 6 Type 7 Type 8 Type 9

Defect Mechanism

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01.16 2.12 3.08 4.04 5.0 5.96 6.92 7.88 8.84 9.8

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Defe

ct C

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Defect SizeDistributions

Defect Paretos

Defect Type 1Defect Type 2Defect Type 3Defect Type 4

Summaries by Wafer

Wafer Map

Figure 7. Various yield analyses provide information to characterize the defect and determine its root cause.

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contributions to yield loss are imme-diately known, eliminating days, oreven months, from the standardyield learning cycle. Analyses are alsoprepared based on the data stored bythe system, including yield sum-maries, defect densities, defectimages, defect size distributions,wafer maps (for spatial signaturestudy), and defect type summariesfor multiple wafers (see Figure 7).These reports are configurable andcan be automatically e-mailed to adistribution list if desired.

Application to yieldimprovement effortsHow should a fab use the powerfuldata provided by µLoop?

Providing FocusA typical problem less-experiencedyield groups run into is having toomuch data and not being sure whichproblems to focus on in order tomaximize the rate of yield improve-ment. Other groups become ineffec-tive when they try to resolve all yieldproblems. The data from µLoop canbe used to bring a more systematicand structured approach to yieldimprovement problems. This newmethodology results in a defect typeyield loss Pareto that quantifies thelargest contributors to yield loss.The best way to proceed is to use theinformation and systematically focuson the defects that are causing the

greatest percentage of yield loss. Asproblems are resolved, the engineerrefocuses on the next largest contrib-utors on the yield loss Pareto.

Yield LearningThe main use for µLoop (and the oneprimarily discussed in this article) isthe yield learning application, wherethe goal is to rapidly identify and fixproblems. Here, all three steps (assess,identify, classify) are used, along witha full report including the D0, Pareto,images, etc. The case studies in thesubsequent sections of this articleare all examples of using µLoop forthe yield learning application.

Yield MonitoringInline yield monitoring is anotherapplication of µLoop. The othershort loop methods do not provideinline electrical testing information;their testing comes at the end of theline, when processing is complete.The non-contact nature of µLoopallows electrical testing after eachcomplete interconnect level. In thisapplication, the three-step method-ology is abbreviated to only the firststep—the assess step—which givesthe density of electrical failures. Ifthis density is below a certain value,no further action is needed, and asimple inline monitoring report isgenerated. If there is an excursion ofelectrical failures, then the other twosteps can be completed, generatingthe full set of information, with a


Pareto and images to help find thesource of the excursion.

Providing Evidence to Help EngageProcess GroupsThe yield group can use the infor-mation from µLoop to thoroughlycharacterize the primary killer defecttype, with the ultimate goal of per-suading the appropriate processand/or integration group(s) to engageand dedicate resources to fix theproblem. The difficulty of convincingthe process groups to assist should notbe underestimated as a potential hurdlein the yield improvement process.Often, the only way to accomplish itis to have thorough and quantitativecharacterization data showing specif-ically what percentage of the yield-limiting defects came from thatgroup’s process or equipment. Themain results from the µLoopmethodology (number of physicaldefects causing electrical failure, anda Pareto of those defect types) pro-vide the convincing evidence needed.

Tuning Inline InspectionsAnother use for the uLoop data is toevaluate inline optical inspectionrecipes for their ability to captureyield-limiting defects. The defects,captured with inline optical andlaser inspections can be character-ized and compared with the yieldlimiting defects captured with theµLoop process. Inspection recipes canbe optimized for use on productwafers to maximize the capture oftop yield limiting defects capturewith the µLoop process.

(See the sidebar on root cause analy-sis for further information about theintegration of µLoop with inlineinspection techniques.)

Comparison of the newmethod to previous methodsAgere Systems in Orlando, Florida,participated in a joint development

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Root-cause analysis In some situations, images of a defect are all that are required to know itssource. Some yield and process groups have built up expertise over a periodof time that allows them to determine root cause accurately based only on adefect Pareto. But in many situations, particularly with new processes andprocessing equipment, that luxury is not available.

Using the µLoop methodology in conjunction with inline inspections canaccurately identify the specific layer at which the killer physical defects occur.All critical layers of the test wafer are inspected with KLA-Tencor opticaland/or e-beam tools, and then µLoop defect locations are overlaid with theinline inspection defect locations to determine the root cause.


project with KLA-Tencor to helpdevelop the µLoop technology. Thework was initiated because of thelong cycle times the yield group hadexperienced with the standard meth-ods it had used for BEOL yieldlearning.1 These methods included:

• Product wafers used with bitmap-ping and failure analysis de-pro-cessing

• Short loop comb and serpentinestructures used with electricaltesting, manual SEM review tolocate the defects, and failureanalysis de-processing

• Short loop zone tester vehicleswith combs and stitch test struc-tures where killer defects wereidentified by overlaying electricaltest and inspection data

Two goals of the development pro-ject were to selectively capture onlythe yield limiting defects, and tominimize the yield learning cycletime. The first goal would speed thecreation of an accurate defect Paretopointing to the areas that need work,and the second goal would speed thehypothesis testing time, allowing forfaster implementation of a fix.

Table 1 summarizes how effective eachof the methods were in the identifi-cation of what problem to fix and theamount of time that was required togenerate the information. The pre-µLoop methods required anywherefrom 16 days to over two months todevelop the initial Pareto due to de-processing or data analysis timerequirements. For some of the longerand more labor-intensive methods,the Pareto was built using only oneor two wafers. The fastest of the pre-µLoop methods based the Pareto ona much larger sample of 25 wafers,but only captured 5–60 percent of theyield limiting defect population. Incontrast, the µLoop method requiredonly four days to create the yield loss

Pareto on 25 wafers. Because ofµLoop’s use of e-beam inspection andvoltage contrast techniques, 95–100percent of all the yield limitingdefects on the wafers were captured.

Further comparison of the differentmethods can be seen in Table 2, wherethe goal was minimizing the cycletime for the hypothesis-testing loop.

The use of product for hypothesistesting was the worst option.Product cycle times are relativelyshort but, by the time probing andtesting are factored in and results arefed back to the engineer, can resultin a 60-day cycle of learning andonly provide probe yield results as ametric. The other methods provided

Random versus systematic defects Random defects are caused by the environment—the people and the processing equipment. A systematic defect, however, occurs because theprocess window is too small or isn’t centered correctly. Certain features willbe the first to show a systematic layout marginality, so when the problemoccurs it will show up in the same place. Historically, these problems havebeen hard to create and measure on anything but product, but now theycan be captured by turning these features into test structures on the µLooptest chip. These systematic or “instance-based” test structures include manyindividually measurable replications of the feature. The advantage withµLoop is that these large areas of repeated features (for example, an array ofvias or line/space features) are not limited in their layout by probe pads.

Another example of a systematic feature is a repetitive SRAM metallizationstructure. SRAM test vehicles are commonly used by fabs to assess back-end-of-line process problems because they provide word and bit address locationsof the electrical failures through bit mapping. The disadvantage of theseBEOL test vehicles is that they require full processing of the front-endlogic to support the bitmap testing. The advantage of using KLA-Tencor’snew methodology is that the same BEOL SRAM metallization structurescan be designed into the µLoop test chip and then tested for systematic orrandom electrical failures without the need for the front-end-of-line (FEOL)processing, significantly reducing the time needed to get results. This ispowerful, particularly in development, because often the SRAM vehiclesexperience FEOL-related yield problems, defeating their usefulness forassessing BEOL yield issues.

The systematic features on the µLoop test chip are beneficial for both currentproduction processes and processes in development. If a current process isexperiencing a systematic problem, the test chip features can be designedto simulate that issue. To speed development of a new process, the µLoopsystematic structures can be used to project the effect of a design rulechange on a worst-case feature set, testing the process window boundaries.This testing can be made easier with the help of KLA-Tencor’s lithographysimulation experts and software (PROLITH™). Utilizing this expertise inconjunction with the µLoop methodology simplifies the complex process ofdeveloping a high-yielding process integration module. Simulations allowinvestigations of the effects of process parameter settings and process errorson CD-limited yield, while the µLoop short loop methodology provides fastyield verification of the simulated results.

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metrics more relevant to the defectunder study in the form of defectdensities and short/open informa-tion. The µLoop methodology’sthroughput was again far better thanthat of the other methods, and it wasthe only method to provide informa-tion on 95-100 percent of the defectscausing electrical failures.

Overall, the µLoop method providedthe capability that was desired andthat was deficient in the previously-used techniques. The µLoop methodenables rapid construction of a yieldlimiting defect Pareto based on alarge sample size and containing vir-tually all the killer electrical defectson the test chip. This technologyalso enables faster hypothesis test-ing, and provides a superior quanti-tative yield limiting defect metricthat can be used to assess the successor failure of hypothesis testing studies.

Case studiesEarly versions of µLoop have beenused to great advantage in over a yearof practical application at AgereSystems. Three case studies of howµLoop was used for yield learning atAgere Systems follow.

Case study 1: Hypothesis testing onan aluminum processIntroduction: One of Agere’s alu-minum processes was yielding belowthe track goal. The problem wasisolated to the BEOL using electricaltester data. The tester data, whileindicating that the problem waslocalized to the interconnect level,did not provide information on theyield limiting defects contributingto the overall yield loss.

Problem Identification: One lot ofµLoop test wafers were run throughthe metal 2 process. At the comple-tion of the process sequence, e-beaminspection scans using the eS20XP


were performed, and the µLoopController was used to characterizethe yield limiting defects. Theresulting yield loss Pareto, shown inFigure 8a, indicated that two primarydefect types—“particles with extra”and “metal stack defects”—wereresponsible for the majority of the teststructure shorts. Several additionalrepetitions were made with the µLoopprocess and the true dominant killerdefect—“particle with extra”—wassingled out. The defect character-ization information, including defectimages, composition information,and spatial correlation with inlineinspection data, pointed to the metaletch process.

Engagement: The quantity of yieldlimiting defect data, coupled withthe characterization information(images and compositional analysis),provided the evidence needed toengage the appropriate metal etchmodule process engineer.

Hypothesis Testing: This engineerproposed studying the effect of a newtype of tool clean on the level of the“particle with extra” yield-limitingdefect type. The µLoop data was usedto provide the dependent metric forthe studies.

An experiment was designed com-paring the process of record, which

Yieldproblem

Yieldlearningdefectidentification

Engagementof processing& integration

Hypothesistesting

Implementationof solution

What needs to be fixed?Time to DevelopPareto

70 days

60 days

16 days

4 days

Approach

Bitmap

Electrical Comb/Serp Testers

Zone Tester Overlay

µLoop

Sample Size forPareto Development

1 wafer

1-2 wafers

25 wafers

25 wafers

% of Yield LimitersIsolated

90%

90%

5-60%

95-100%

Yieldproblem

Yieldlearningdefectidentification

Engagementof processing& integration

Hypothesistesting

Implementationof solution

Minimize cycle of learning time

Learning Cycle

60 days

10 days

10 days

4 days

Vehicle

Product

Short loop (electrical)

Short loop (electrical/overlay)

µLoop

Output Test Data

% yield

D0, Shorts, Opens

D0, Shorts, Opens

D0, Shorts, Opens

Yield LimiterDefect Stats

No

No

Yes (5-60%)

Yes (100%)

Ability to Root CauseDefect Types

No

No

Yes

Yes

Table 1. Comparison of the performance of various yield learning cycles for creating the initial

killer defect Pareto.

Table 2. Comparison of the performance of the various yield learning cycles for hypothesis testing.

C O V E R S T O R Y


ran on tool A, with the new “in-situ”cleaning process, which ran on toolB. The metric for quantifying theresults was the density of “particlewith extra” defects on the µLoop testchips. Initially, one lot was split,with the wafer processing spread outover a period of time to evaluate theeffect of “chamber time since lastmajor tool clean” on the level ofyield limiting “particle with extra”defects.

The results in Figure 8b showeddegradation in the standard cleantool as more wafers were processedthrough it, leading to an increase in the“particle with extra” defect density.

In contrast, the tool with the exper-imental new clean did not show anyincrease over time. The same lot wasused again with the µLoop method-ology at the next metal layer; and, theadditional data confirmed the initialresults. Paretos were generated usingµLoop before and after this processchange was implemented. Figure 8cshows how the density killer defectschanged over this time period. Theimprovement was very clear.

Subsequently, “particles with extra”were still the dominant killer defecttype on the Pareto, though at a muchlower level, but now only a few wafersper lot showed high counts of thisdefect type. Additional µLoop exper-iments led to the discovery of astrong correlation between a certain

process variable and the “particlewith extra” defect count as illustratedin Figure 8d. Note, that for the datashown in Figure 8d, the correlationbetween the total number of killerdefects and this process variable wasnot significant because of an excur-sion of tungsten puddles; thisdemonstrates the value of being ableto break down the yield loss bydefect type. A process adjustment tokeep the level of this certain processvariable down was devised andproven in using µLoop.

Implementation: The decision wasmade to modify the process of recordto include the in-situ clean basedprimarily on the results obtained usingthe uLoop technology. At the time ofthe change, the results from productdata were inconclusive. µLoop greatlyaccelerated the implementation phasefor this first process change. The second change did not require boardapproval and was implemented soonafter the compelling results fromµLoop were obtained.

Summary: µLoop was used to quan-tify the contributions of the variousdefect types to the overall yield lossand to pinpoint the area needing themost work. Next, it was used to testseveral process improvements and theirability to reduce the level of yieldlimiting defects, and to track theireffectiveness over time. This studyhighlights how the use of the µLoopprocess offers a cycle of learning at

Defe

ct D

ensi

ty (

cm2 )

Defect Class

ParticleWithExtra

Stack Extra WPuddle

NotFound

Figure 8a. Results from µLoop showing the initial yield loss Pareto.

Part

icle

wit

h Ex

tra

Dens

ity

Wafer Count0 100 200 300

In-situ CleanNo Clean

Figure 8b. Results from µLoop showing the

degradation of the standard clean process

compared with the new clean.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

April/May June/JulyLot

No In-situ Clean In-situ Clean

0.2

0.18

0.16

0.14

0.12

0.1

0.08

0.06

0.04

0.02

0

Defe

ct D

ensi

ty (

cm2 )

Etch Particle With Extra*W puddlesDeep or Litho Particle With ExtraStackOther * Defect of Interest

Figure 8c. Results from µLoop showing the

decrease in the critical killer defect type after

the implementation of the new clean.

Proc

ess

Vari

able

X (

Wat

t)

eS20

Par

ticl

e w

ith

Extr

a (P

WE)

300

250

200

150

100

50

0

18

15

12

9

6

3

00 2 4 6 8 10 12

Wafer # (Etch Sequence)

Process Variable XPWE's

Figure 8d. By-wafer correlation between

“particles with extra” and a process variable.

C O V E R S T O R Y

26

each interconnect level for a particu-lar lot. It led to a 4x improvement inthe time needed to implement theseprocess changes. With µLoop, thesechanges were implemented in onlyone and a half months; using theconventional methods they wouldhave taken at least six months.

Case study 2: Capture of a system-atic problem on an aluminum processIntroduction: The practice of peri-odically running µLoops for a numberof technologies to track and charac-terize the BEOL yield loss Pareto wasinstituted early in 2001 at AgereSystems. Often, these same wafers arealso used for hypothesis testingexperiments. The ability of the µLoopmethodology to break down yieldloss by defect type allows the same lotof data to be used for both purposes.

In this example, a systematic problemwas detected on the outer peripheryof the wafers in an aluminum processfor the latter metal levels.

Problem Identification: The initialfull flow µLoop lots for this technol-ogy detected significant yield loss atthe wafer edge for the metal 4 inter-connect level. A wide line, mini-mum space comb test structure hadbeen placed on the chip in order totest the extreme limits of the designrules. All metal lines tended to bewider at the wafer edge and this par-ticular structure was shorting inwhat appeared to be random places inthis zone. Soon after this discovery,significant product yield drop-outwas observed at the wafer edge.Routine inline inspection of producthad not provided evidence of anytype of problem; many of theseshorts were very difficult to pick upeven with a SEM. Cross-section andother characterization work indicatedthat there was a large variation in thewafer topography around the outeredge of the wafer. This variation,coupled with the limited lithography

depth-of-focus, was enough to causea printing problem and subsequentmetal line shorts.

Engagement: The wafer topographyproblem could be caused by one ormore process steps used to completethe interconnect process. A team wasformed, including process and inte-gration engineers, to develop a solu-tion to the problem.

Hypothesis Testing Experiments:The team ran several studies to min-imize the topography variationacross the wafer surface. The µLoopmethodology was made available forhypothesis testing and was utilizedto evaluate one idea. The ultimatesolution was not initially tested withthe µLoop methodology since directmeasurements of the wafer topogra-phy were more appropriate. Once theteam had developed an acceptablesolution, the µLoop wafer resultsindicated that the problem of metalline shorts no longer existed aroundthe outer periphery of the wafer.

Implementation: The processchange, which was a CMP hardwaremodification, was implemented.The ensuing yield data from µLoopwas one of a number of validationsthat the outer edge systematic yieldproblem was eliminated.


Summary: In summary, µLoop pro-vided an inline vehicle to capture aproblem that was not captured withinline defect inspection tools and thatwould typically require time-inten-sive failure analysis techniques tocharacterize. The issue was a systematicproblem captured with a systematictest structure specifically included totest for it. The only reason this prob-lem had not been detected earlierwith µLoop was that the µLoop testchip had only recently been developed.Secondly, the µLoop wafers, whichwere processed with the entireprocess sequence, captured a problemthat would not have been capturedon a short loop (1- or 2-level) processsequence. The problem also would nothave been captured on the normal,nominal line and space test struc-tures. The problem was confined tothe wide line/narrow space structures.

Case study 3: Early yield learningon a copper processIntroduction: Yield learning on newtechnologies is especially challengingdue to the large number of defectspresent on wafers as new processes arebeing developed. Attacking all of thedifferent defect types at the same timediffuses the available resources andresults in slow yield improvement.The key to success is to obtain a yield

Defe

ct D

ensi

ty (

cm-2

)

Outer edge spatial signature

Defect Class

Narrowing W Puddle Particle withExtra

Extra

Figure 9. Results from µLoop showing the narrowing space defect and signature.

C O V E R S T O R Y


loss Pareto that allows one to focusimprovement efforts on the defecttypes that contribute the most to yieldloss. In this example, a yield loss Paretowas developed for wafers processedearly in the development phase.

Problem Identification: A shortloop tester containing the µLoop testchip was processed through themetal 1 copper interconnect process.The µLoop structures were scanned onthe eS20XP and the defects werecharacterized using the µLoopController. The Pareto showed that themajority of the wafers had moreshorts than opens—an unexpectedresult—and the most common defectswere distortions of the oxide trenches,photo resist bubbles, and flakes.

Based on this information, the yieldgroup was able to prioritize theirfuture improvement efforts to maxi-mize yield learning.

Here the µLoop methodology wasused to overcome the common prob-lem of defect noise in the develop-ment phase, and enabled the fastseparation of the yield killers fromthe general defect population.

µLoop SummaryFast yield learning for the back-end-of-line has become even more challengingand essential with the introductionof increasingly complex interconnectprocesses and smaller design rules.The efficiency of the BEOL yield

learning process has improved sig-nificantly with the introduction ofµLoop, which enables (1) a reductionin the time to complete a learningcycle from weeks or months down todays; (2) multiple cycles of learningto be obtained from each µLoop lot;(3) the construction of a yield limit-ing defect Pareto that provides aquantitative assessment of the yield-loss contributors; (4) characteriza-tion of the yield limiting defect withcompositional analysis; and (5) thecapture and identification of system-atic defects that are created by inte-gration issues or are exacerbated bymulti-layer topography.

Yield groups can take advantage ofKLA-Tencor’s expertise and revolu-tionary BEOL yield managementtechnology, requiring them to investfewer resources and less time andmoney in the complex and difficultprocess of developing BEOL testchips and yield learning methods.The benefits they receive in returnare tremendous: reaching yield goalsfaster, getting to market faster, andreaping potentially hundreds of mil-lions of dollars in increased profit.

References1. Henry, Todd, “Application of eD0 to

Accelerate BEOL Yield ImprovementActivities,” KLA-Tencor Yield Man-agement Seminar, October 2001.

Coun

t

9876543210

Defect Class

Distortion PR Bubble Flake Not Found Extra Smudge Scratch FallingWalls

Particle RemovedDielectricParticle

MissingCopper

Figure 10. Results from µLoop showing the yield loss Pareto for the copper process in development.

C O V E R S T O R Y

in optimizing your manufacturing process. All strategically

formulated to enhance your bottom line. And put you on

the most efficient road to yield. For more information,

please visit us on the Web

at www.kla-tencor.com,

or call 1-800-450-5308.Accelerating Yield


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But these days, only the fastest route will do. That’s

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YIELD

29

On October 30, 2001,Semiconductor International’s SeniorWest Coast Editor, Alex Braun, pre-sented KLA-Tencor with the prestigiousGrand Award for its eS20XP scanninge-beam wafer inspection system.Established in 1989, SemiconductorInternational magazine’s Editors’Choice Best Product Awards program,recognizes 20 products used in semi-conductor and related manufacturing.This year, KLA-Tencor’s eS20XP systemwas singled out as the Grand Awardwinner in recognition of its contribu-tions to the industry in accelerating thedevelopment and production ramp ofnew semiconductor processes, includ-ing copper and low-κ dielectrics.Customers cited the eS20XP’s industry-

leading throughput and sensitivity askey to enabling them to significantlyreduce their electrical defectivity andyield-learning cycle times on their lat-est-generation devices.

“The Editors’ Choice Best Products pro-gram differs from other awards in thatproducts must be nominated by users,not by people who make or sell them.A product that receives this award hasbeen verified to demonstrate superiorand proven production capabilitiesthat advance semiconductor innova-tion and manufacturing,” noted PeterSinger, Semiconductor Internationaleditor-in-chief. “This was most clearlythe case with KLA-Tencor’s eS20XP e-beam wafer inspection system, which


led our editorial team to select it asthe Grand Award winner out of thisyear’s 20 winners.”

The eS20XP detects electrical defectsduring front-end-of-line (FEOL) process-ing at speeds unmatched in the indus-try. Using state-of-the-art voltage con-trast capability, it detects electricaldefects during front-end processing,inspecting an entire wafer in little morethan an hour compared with daysrequired by previous-generation andcompetitive e-beam systems. Because itenables fab engineers to find electricaldefects at the source layer instead ofat back-end-of-line (BEOL) electricaltest, the tool dramatically reduces therisk of weeks or months of work inprogress (WIP) to exposure to theseyield-killing defects.

The eS20XP also detects physicaldefects as small as 50 nm, as well asdefects in high-aspect-ratio structures,which are extremely hard to detectusing other inspection techniques.

“It’s truly an honor for us to havereceived this award,” stated RickWallace, executive vice president ofKLA-Tencor’s Wafer Inspection Group.“The eS20XP represents one of themost successful product introductions inKLA-Tencor’s history. It is the most widelyadopted e-beam inspection system onthe market, with the vast majority ofleading logic, DRAM and foundrymanufacturers having purchased it foruse in their advanced design rule pro-duction lines. This proves, once again,that customer satisfaction is the greatesttestament of all to our success.”

eS20XPReceives

Semiconductor International’s2001 Editors’ Choice

Grand Award

S E C T I O N S


S P O T L I G H T O N L I T H O G R A P H Y

Using the Feature Modelto Define CDIn the last edition of this column I described thefeature model, a simple mathematical shape with asmall number of parameters that is used to approxi-mate a much more complicated real feature cross-section. Figure 1 shows the most common featuremodel used for extracting critical dimensions (CDs),the trapezoidal feature model. As I mentioned lasttime, the necessary use of an overly-simplified featuremodel to extract a single CD value from a complexresist profile has two fundamental error sources(independent of any measurement error): error inthe use of a simplified feature model and errors associated with the method of finding the “best fit”of the model to the actual feature.

Since the choice of the feature model is based bothon relevance and convenience, and since the trapezoidis so commonly used for CD metrology, the impactof the feature model choice will not be discussed here.When fitting the feature model to the data, thereare many possible methods. For example, one couldfind a best fit straight line through the sidewall ofthe profile, possibly excluding data near the top andbottom of the profile. Alternately, one could forcethe trapezoid to always match the actual profile atsome point of interest, for example at the bottom.Whenever the shape of the actual profile deviatessignificantly from the idealized feature model, themethod of fitting can have a large impact on theresults.

For example, as a lithographyprocess goes out of focus, theresist profile and the resultingfeature size will change. Butbecause the shape of the resistprofile is deviating from atrapezoid quite substantiallyat the extremes of focus, CD can be a strong functionof how the data was fit. Figure 2 compares the mea-sured CD through focus (as simulated with PROLITH)for two different feature model fitting schemes: abest fit line through the sidewall and fitting thetrapezoid to match the actual profile at a set threshold(height above the substrate). Near best focus the twomethods give essentially the same value since theresist profile is very close to a trapezoid. However, outof focus there can be a significant difference in the CDvalues (>5%) based only on the fitting method used.

In real metrology systems the actual resist profile isnever known. Instead, some signal (secondary electronsversus position, scattered light intensity versus wave-length) is measured that can be related to the shapeof the resist profile. This signal is then fit to somemodel, which ultimately relates to the feature sizebeing measured. Although a bit more complicated,the same principles still apply. Both the featuremodel and how that model is fit to the data willaffect the accuracy of the results.

Figure 2. Using resist profiles at the extremes of focus as an

example, the resulting measured feature size is a function of how

the feature model is fit to the profile.

Figure 1. Typical photoresist cross-section profile and its corre-

sponding "best fit" trapezoidal feature model.

Chris A. Mack, KLA-Tencor


The move to 0.13 µm, and the introduction of new materials and processing methods such as copper, low-κ materials, andphase shift reticles, are byproducts of the demand for more powerful ICs. As a result, the yield management challenges aredifficult, but somewhat anticipated for a move to a smaller design rule. Some of the associated defect samples planningaspects, such as employing e-beam inspection in addition to optical techniques, have been explored 3. For the first time in recent memory, the semiconductor industry is witnessing the convergence of shrinking design rules, the transition to 300 mm, and implementation of new materials in the interconnect scheme such as copper and low-κ dielectrics. The factthat the 300 mm transition is taking place, along with other transitions, creates unique challenges and opportunities inyield management that warrant a new focus in defect sample planning.


The Best Laid Plans of 300 mm Fabs

Anantha Sethuraman, Sagar A. Kekare, Raman Nurani, and Dadi Gudmundsson, KLA-Tencor Corporation

Although the transition to new materialsand smaller design rules are definitely technology-enabling endeavors, such effortsare not without their characteristic yieldmanagement challenges. However, many ofthese challenges would have been encoun-tered without the 300 mm transition takingplace simultaneously. Supposing no 300 mmtransition were taking place, previouslyestablished sample planning exercises couldbe performed effectively, with only moderatechanges in focus, to establish effective yieldmanagement strategies. This paper hasbeen organized to reflect those challengesand provide some insights to surmountingthem. The first half of the paper covers indetail some of the 300 mm process-inducedchallenges, while the second half covers the classical defect inspection samplingproblem from a 300 mm standpoint. Thedetailed discussion of 300 mm process-induced challenges provides a guideline towhere new defect inspection points mayemerge. Besides suggesting the incorpora-tion of these potential inspection pointsinto 300 mm sampling plans, the latterhalf of the paper addresses how sampleplanning in 300 mm fabs needs to takeplace alongside layout and automationplans for optimal effect.

300 mm technological & process-induced challengesFilms ModuleFilms processes are generally viewed as two somewhatseparate categories: planar films stacked on a substrate,and films targeted towards optimal gap-fill to avoidtranslation of topography. The planar film-stacks suchas STI nitride, gate poly-silicon, or refractory metal forsilicidation are mostly affected by defects like particles,flakes, pinholes and voids. In addition to these defects,the gap-fill films may have other unique defects whenthey fail to achieve their primary function of filling agap between features. Many times such unique defectsmay not be captured right after deposition, as they stayhidden deep into the folds of these films. Examples ofthese films are STI HDP oxide, spacer nitride, PMDdoped silica glass, IMD doped silica glass for Al inter-connects, etc.

With advent of copper dual damascene technology, amuch larger fraction of films in modern fabs have gap-fill function as their prime objective. Absorptionand adhesion between each of the films within a desiredfilm stack is a prime factor that controls the continuityand conformity of such film stacks. Electrochemicallydeposited copper is especially sensitive to the existenceof a sputtered seed layer during the nucleation stage forthe copper film. Voids are almost the predominant defectin copper films due to this tendency. New methods in


processing bring about a new set of defects to a module.The circular motion of the wafer in a non-optimal electrochemical bath may result in concentric swirlpatterns in deposition.

Variations in film deposition rate would be magnifiedwith 300 mm wafers. Larger area coverage would accelerate film stress related failures like warping andcracking. Stresses could induce stacking fault typedefects at the silicon-STI interfaces near the edges ofthe wafer.

Litho Module Lithography is clearly the most complex process modulein modern fabs. Along with the quantum leaps inexposure tools and ancillary systems, this module faces a rapid introduction of new consumables and film substrates. These conditions, combined with radicallynew mask technologies, present a significant challengefor defect control and yield entitlement.

Resist backsplash, developer spots, focus hot-spots,missing pattern, resist collapse, etc. are some of the mostcommon defects encountered in the litho module. Theintegration of the new tools, materials and consumablesis a formidable task for litho module optimization.Photo-resist poisoning from inorganic ARC, thin patternlines broken due to micro bubbles, CD variation acrossthe chip due to grid snap, OPC errors during maskmaking, and partial printing of sub resolution assist fea-tures are only a few examples of the current defectivitythat stem from the integration challenges in the lithomodule. Process development efforts that combine theparametric and defectivity aspects of module optimiza-tion will achieve early yield.

Bake-oven temperature non-uniformity and variationin the focus offset across the wafer are two principlecauses for across-wafer CD variation. With the 300 mmwafer size, the oven-related variation should contributea much larger fraction of CD variation across the wafer.When combined with sensitive techniques like OPCand phase shift reticles, such variations may become theroot cause for a significant portion of litho defectivity.

Etch ModuleEtching is controlled removal of part of a film stackusing exposed photo-resist pattern as the maskinglayer. Hence many of the defects from lithography willpotentially be carried through the etch step. In additionto these defects, etch tools may flake off the passivationlayer condensed on the chamber walls. Loss of selectivity

may result in damage to the substrate, which may beintolerable. Non-uniformity in removal rate may leavebehind under-etch residues and stringers.

High aspect ratio features are ubiquitous with theincreasing adoption of copper dual damascene technology.Shrinking design rules combined with high aspect ratioallows for small process drifts to result in gross defectivitysuch as through under-etch or distorted features.Difficulty in removal of passivating etch byproductsfrom the high aspect ratio features is another source ofdefectivity.

Etch chamber design has evolved from the baseline 200 mm configuration into the 300 mm configuration.Gas flow, plasma induction, and location of the exhaustport contribute to the non-uniformity of etch action.With a larger wafer area, these issues can be expectedto remain important, if not grow in significance.

CMP ModuleChemical mechanical planarization was introduced torecover a planar wafer surface through removal of undesirable topographic features. The dielectric layerswere amenable to this technique, with tungsten plugsbeing mostly defined by CMP in the last few device generations. Due to the unique combination of chemicaldissolution and mechanical abrasion, the defects gener-ated during CMP were quite unique in themselves.The defects ranged from the simple residual slurry andscratches to more complex interactions like delayedcorrosion and coring of interconnects. Additionally,CMP also brought to light the film defects caused byinefficient gap-fill.

Copper dual damascene technology has shifted thefocus of process development from dielectric CMP tometal CMP. Copper CMP is being brought to high volume IC manufacturing for the very first time. Thisshift in the objectives of BEOL CMP from planarizationto full-fledged interconnect definition brings about aslew of defectivity and process control issues. All filmsin the copper module belong to the gap-fill category.Moreover the dual damascene features have higher aspectratios than previously encountered in IC processing.This gives rise to seams and folds forming along thefeature during deposition. CMP exposes these hiddendefects in the form of co-axial voids. CMP may alsogenerate voids through the copper grain rip-out phenome-non. Any unbalanced chemistry of the slurry compoundmay result in delayed corrosion of the copper features.



When polishing a larger area, however, the preliminaryreports seem to suggest that removal rates become moreuniform across the wafer. Since multiple techniques ofCMP are still in the evaluation phase, it will be difficultto state this observation to be universally applicable.

Emerging defect inspection pointsN/P Well LithographyThe N/P well region masks contain extremes in featuresize. In the memory regions, where the wells are placedvery close to each other in a very regular array, the maskfeatures are long lines under 2 microns wide, whereas inthe peripheral control logic, the mask may feature largerrectangles tens of microns wide on both sides. Typically,the process development for this layer is low priorityand a nominal process window is decided with a singledata point collected per field from a focus exposurematrix wafer using a CD SEM. Since this data collectionpoint does not truly represent the process windows forthe entire range of features on the mask, there is alwaysa risk of some feature falling out of the usable processwindow with a minimal drift in focus offset. However,with shrinking minimum allowable dimensions of welllayer, this risk has assumed a greater significance.

This risk can be mitigated early on during the processdevelopment phase. An approach that looks at both, theparametric as well as the defectivity performance of agiven process is the correct way to provide early miti-gation of this risk.

Older 200 mm-stepper platform designs will be ready toprocess 300 mm non-critical layers with some addition-al modifications of the chuck and auto-focus systems.However, these systems may have a greater challenge inmaintaining across wafer focus offset as compared to the

state of the art stepper/scanner platforms. This validatesthe need for following the dual-pronged approach toearly process development and characterization on thewell layers (refer to Figures 1 and 2).

Gate Dielectric DepositionAs the operating voltages scale down, power consumptionspecifications tighten and performance requirementsshoot up, and the gate dielectric quality becomesextremely important for the device. The inspection atpre-gate dielectric growth/deposition should focus main-ly on the physical phenomenon that affect the dielectricquality. These are crystal-originated pits (COPs),scratches from STI CMP, and any other surface contami-nation. Although 300 mm wafers handling will be fullyautomated, the transition from 200 mm to 300 mm

N-well maskN-well mask

1-2 µm

Figure 1. Typical SRAM cell showing opened N-well region between two P-well regions masked with photo-resist.

Long thin area

Large open area

True process window

Figure 2. Schematic of process window for two distinct features on a

given reticle, indicating the overlap region as the true usable process

window.




may inherently cause the wafer to possess more COPstype of defects as incoming material. Scratches thattranslate through the STI nitride into the substrate silicon are known to affect the device characteristicsadversely. This log point will serve to weed out defectivewafers at an early stage in the process, thereby savingconsiderable processing costs (refer to Figure 3.)

N+ / P+ Implant Lithography Similar to the N/P Well masks, these two masks alsocontain a large range of feature size. A region ofbutting implants may not get silicided if each implantis pulled back due to the litho CD widening. Similarlyresistance to junction breakdown may suffer if the lithoCD is shrunk. An early optimization of process windowthrough a defectivity and parametric characterizationwill prove extremely beneficial in avoiding these inte-gration roadblocks (refer to Figure 4).

Silicide RTP 2Cobalt silicidation is extremely sensitive to the presenceof any oxide on silicon. However, any native oxidationarising from rinse dry spots, etc., is not detectable priorto silicidation. Similarly any remaining inorganic ARCon top of the gate poly-silicon is not detectable prior tosilicidation. Yet, these may result in a population ofunsilicided sections, each as large as the smallest designrule gate CD. Unsilicided regions usually have high

contact resistance levels. An inspection log point atSilicide RTP 2 will capture the evolution of such defectsfor an early root cause analysis8 (refer to Figure 5).

The above sections have outlined emerging 300 mmprocessing issues that may point to the need for amendedor expanded defect inspection plans in 300 mm process-ing. Being aware of those issues is one part of the puzzle

Proc

ess

Win

dow

Tighter process windowswarrant stringentprocess centering

0.25µm

0.18µm

0.13µm

Figure 4. A schematic of shrinking process margins, indicating an

ever-increasing challenge for parametric process control as the design

rules shrink fur ther.

Weak sitespossibly dueto COPs

Figure 3. a) A cumulative probability plot of a highly defective gate dielectric indicating unacceptable proportion of weak sites. b) An AFM

rendering of crystal-originated pit type defects.


in creating an effective sample plan in a 300 mm fab.Combining these emerging issues with known inspectionpoints in 200 mm processing, the space of inspectionpoints can be defined (to the extent it is possible withoutextensive actual 300 mm processing data). Now a largerscale methodology needs to be applied to identify capableinspection equipment, calculate inspection capacityrequired, and allocate it effectively across the fab. Thefollowing paragraphs address these issues.

Defect detection challenges in 300 mmA variety of new challenges to defect detection areintroduced during the move from 200 mm to 300 mm.First, there is the need for detection over a larger surfacearea. This requires modification of existing hardware.Second, and more importantly, is the use of new mate-rials. This will change both the composition and type ofdefects encountered, requiring new techniques for theircapture and automatic classification. Third, the size of“killer” defects decreases with the move to a smallerdesign rule, requiring an increase in tool sensitivity.Fourth, new inspection requirements, such as waferbackside inspection, become important, prompting theredesign of inspection tools. Finally, from a broaderperspective, there are issues such as the need for seam-less information exchange between defect detection andreview tools, processing of greater amounts of data, andthe need for automation of the defect sampling process,in keeping with the overall fab-automation initiative.

In addition to the above, it is expected, and initialpilot line/ramp experiences confirm, that excursionrates can be higher. To some degree this is merely thefact that excursion frequency is measured in wafers. Ifone were to measure the frequency in number of diesbetween excursions, then the rates may be somewhat

similar. However, we are not producing one die at atime and, therefore, excursions will occur at shorterintervals then in 200 mm processing. This may requireevery lot to be sampled at some layers, where that wasnot justified in 200 mm processing.

The yield management industry is well on its way inproviding the tools and techniques necessary to dealwith the above-mentioned challenges, but this capabilityneeds to be deployed correctly. With major 300 mmfabs in the planning stages, a unique challenge andopportunity in yield management arises. By includingyield management in the planning stage a fab can bepredisposed to deliver superior yields. Further empha-sizing the need to include yield management in theplanning process is the fact that 300 mm fabs will haveprocessing and inspection tools bound together withvarious automated material handling systems. Thiswill, inherently, make fab layouts and material flow lessflexible, and emphasizes the need for setting the fab upcorrectly the first time. Towards that goal, the followingsections address the concepts and methods that shouldbe employed to effectively include defect sample plan-ning in the fab planning stage.

Process integration-induced defectivityin copper interconnectsSpin-on and CVD low-κ dielectric films are replacingthe PECVD doped silicate glass films for BEOL inter-layer isolation. These new films possess characteristicsthat make their integration markedly different. Thesefilms do not fulfill a gap-fill role. They are planar filmsthat are patterned with trenches and holes later to befilled with electroplated copper. The patterning is donewith DUV process, with alignment of subsequentphoto steps gaining critical importance. Electroplatedcopper is highly sensitive to surface conditions andneeds a high quality seed layer of copper for uniformfilm growth. Copper being a deep level impurity, athorough encapsulation of all interconnects is necessaryto prevent the copper from diffusing into the silicon.Tantalum nitride or tantalum barrier films are depositedprior to the seed layer to achieve this objective. Oncefilled with copper, the etched pattern is redefined byplanarizing the excess copper through use of CMP.

The process steps mentioned above are complex in them-selves. In addition to that, they need to be optimizedfor their combined process margin. One element of thisoptimization is the need to eliminate possible defectgeneration through interaction of these processing steps.

Shee

t Re

s. O

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Figure 5. a) Silicide sheet resistance as a function of over etch in wet

clean step, indicating a threshold for removal of oxide residue from top

of gate pattern. b) A SEM image of residual oxide on polysilicon gate

pattern, where silicide formation was inhibited.


A few striking examples of how killer defects are gen-erated through such interactions are discussed belowwith schematics in Figure 6 (a) through (i).

Photoresist poisoningfrom PECVD low-κdielectric films

In the dual damascenescheme of etching, thesecond patterningstep is exposed to thedielectric film with-out a capping layer.The amine radicalsfrom the nitrogen containing film alter the developmentreaction of the DUV photoresist. This leads to curiousdefects such as mushroomed or missing vias.

Film discontinuity due to etch profilenon-ideality

An overhanging orbarreled via profileleads to shadowingin the path of sput-tered barrier and seedlayer films. Absenceof seed layer will leadto incomplete filling of copper into via holes. Such avoid will remain hidden from optical inspection andwill prove to be a truly silent killer defect.

Pattern densitydependence of copperpolish rate in CMP

Dense regions tendto demonstrate apropensity for slowerpolish rate. Slowerpolishing increasesthe probability ofcopper puddles orresidues between adense array of lines, which may lead to bridging shortsand circuit failure.

Translation of previous layer topography into the current layer

Variation in metal polish rates due to pattern density



Figure 6a. Missing via.

dependence may leadto flatness variation inthe next inter-metaldielectric layer. Suchvariations could provefatal for the alreadyshrinking processwindows for DUVlithography. Itbecomes imperativeto implement dielec-tric surface polish steps to bring the overall flatnesswithin an acceptable range. A scratch from such dielec-tric CMP may get filled with ECP copper and act as astringer or a bridging short.

Defects from metaldeposition processexposed during CMP

Electrochemical plat-ing of copper isextremely sensitiveto hindrances tonucleation andgrowth. These hin-drances could benon-uniformity ofseed layer or it could be residues from SEM review ofseed layer due to carbon condensation. A void may getembedded in electroplated films, where the copper failedto adhere and nucleate. Such embedded voids can beexposed during polishing of copper. Some electroplatingconditions are prone to bread-loafing, and generate a seamalong the axis of trench in which copper is deposited.Such a seam shows up after CMP as a row of voidsalong the center of a copper line.

Corrosion and materialnon-compatibility

The CMP process hasa large chemical aspectto it. Copper CMPtypically proceeds inan acidic environ-ment. Nearing theendpoint, the acidicelectrolyte is now incontact with both the barrier layer and the copper line.This leads to the formation of a galvanic cell, resultingin corrosion of copper lines along the barrier interfaces.

Figure 6d. Scratch filled with copper.

Figure 6e. Voids and seams in copper.

Figure 6b. Barreled via profile leads to

a hidden void in copper.

Figure 6c. Copper puddles.

Figure 6f. Corrosion in copper.


Corrosion attacks may also take place along the triplepoints in the copper microstructure, leaving distinctpitting type defects behind.

Impact of annealingconditions and timingin the integrationsequence

Electroplated copperfilms are polycrys-talline. An annealingtreatment is necessaryto optimize the grainsize and stresses incopper films. However,the thermal energyavailable from theannealing is utilizedfor void growth andcoalescence. Such voidgrowth may seek lowfree-energy sites suchas grain boundaries orinterfaces for conden-sation into large voids.If the annealing isdone prior to CMP,then these condensedlarge void regionsgive rise to defectssuch as rip-outs, voidsalong the line edgesand broken lines. Ifthe annealing is donepost-CMP, sub-surfacevoiding may resultfrom condensation ofvoids along the bottom of the via or the side of the trench.

Economies of scale and yield managementThe fundamental premise of the 300 mm initiative iseconomy of scale, i.e., to decrease the manufacturing costper square centimeter of silicon. It is estimated that themanufacturing cost per square centimeter of silicon willbe about 30 percent lower. As one would expect, thepressure on improving yield management to producemore good dies at a lower cost is increased. It is, however,simplistic to enforce the same cost performance on yieldmanagement needs without considering the whole picture. Using the guiding principle of reducing inspec-tion cost per square centimeter of silicon by 30 percent

is not the correct metric in which to base the amount ofinspection capacity needed. Instead, one should seek tomaximize the profitability of the fab and employ theinspection capacity needed to reach that goal. Whencalculating that capacity, fabs need to pay attention toseveral factors that collectively are embodied in a yieldmanagement strategy. A fundamental analysis of processtool, material handling, andinspection/metrologycapacity planning is required. Furthermore, the impactof inspection on yield and cycle-time needs to be under-stood to provide a return on investment (ROI) that isoptimal. Strategies will then vary depending on the fab(development or production), device (memory, logic ormixed) and segment (captive or foundry).

The transition to 300 mm has a larger impact on theeconomic aspect of wafer manufacture. Transferringprocesses with low baseline yield into the ramp phaselacks economic viability or, worse still, will become fiscal disasters. This further reinforces the value of a highyield learning rate being present early. Preliminaryanalysis shows orders of magnitude difference in thevalue of yield learning for 300 mm processing. Table 1contains some of the parameters used and Figure 7 showsthe results. It can be observed that there is a much greaterreturn per yield learning percent increase in 300 mmprocessing than in 200 mm processing. Although a highyield learning rate is not only dependent on the availableinspection capacity, a lack of inspection capacity cancertainly be the limiting factor in the yield learningprocess and would most definitely be the differentiatorin the long run between leading-edge companies.

Table 1. Parameters in yield learning rate analysis1.

After the ramp-up phase is finished, the excursion con-trol mode of yield management takes over for the fullproduction phase. Again the 300 mm fab is faced withthe dilemma that while the initiative provides consid-erable economies of scale in chip production, eachwafer is much more valuable and that greater amountsof material are at risk to excursions than in 200 mmproduction. Calculating the relative value of 300 mmyield losses relative to 200 mm yield losses in the fullproduction phase is much simpler than for the ramp-up


Figure 6g. Cross section schematic.

Figure 6h. Triple point voids in copper.

Figure 6i. Condensed voids in copper.

ASP/cm2 of silicon $40 Wafer starts per week 1000 Die size 1.5 cm2

Starting D0 0.65/cm2

Fault learning rate per month 4%

Grains



phase. Utilizing the applicable inputs from Table 1, andassuming that the wafers starts per week are 4,000 inthis phase, we can calculate the value of lost materialseach month relative to the same in 200 mm processing(see Figure 8). Numerous results in sample planninganalysis2, 3, 7 have shown that the amount of inspectioncapacity to be used should be based on the value of the materials that can be saved. Given the vast valuedifference shown in Figure 8 it is expected that greater

inspection capacity will be needed for the full productionphase in 300 mm processing. KLA-Tencor has a well-established methodology to do sample planning for boththe full production and ramp up phase of the fab. Thismethodology has the capability to address the 300 mmdefect sample planning challenges. The following para-graphs address this methodology and its application tofab planning.

300 mm defect sample planning It has become well accepted that defect inspection toolsplay an important role in a fab’s yield managementstrategy. While few manufacturers currently operatewithout some type of defect inspection, many IC man-ufacturers tend to view inspection as non-value-added

300 mm200 mm

Fault Learning Rate Delta Per Month1% 3% 5% 7% 10%

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Figure 7. Comparison of opportunity gained in 200 mm and 300 mm

processing for a range of increased yield learning rates. The insert ex-

plains the definition of an increased yield learning rate, a traditional yield

learning rate is in blue and an increased yield learning rate in purple.

300 mm200 mm

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Figure 8. Examples of the value of yield losses to excursions for 200

mm and 300 mm processes during the full production phase.

InspectionLayers?

InspectionMethod?

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WafersPer Lot?

% Area/# of Sites

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ess

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Per Wafer

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Figure 9. Typical questions posed in a sample planning analysis.



and are overly conservative when planning inspectioncapacity. It is here that the sample planning problemarises: what types of inspections to perform; where tolocate them in the process; and how frequently to per-form the inspections. To answer these questions, aneffective method involves the trade-off between thecost of inspection operations, both fixed and variable,and the cost and/or risk of yield loss due to undetectedyield-limiting defects and process excursions.

The main decision parameters are:

• Placement of the inspections (which process steps/process tools)

• Type of inspections (test wafer, product, or in-situ inspections)

• Inspection frequency (percent lots to sample, numberof wafers per lot, area per wafer)

• Inspection sensitivity to use

• Which parameters to track and respond to (Statistical Process Control scheme),

• The fraction of defects to review

• Inspection tool capacity

All these parameters are inter-related, and each one givesrise to a set of variables that need to be understood.KLA-Tencor’s Sample Planner 3 (SP3) cost model provides the framework and tools to analyze critical fabparameters to develop an optimal inspection strategywith reasonable effort. By combining it with analysisperformed during fab planning, the fab plan can bedevised to have inherent advantages in yield management.

In its simplest form, the cost model methodology isbased around a recurring in- and out-of-control cycleoccurring at each step in the process. A cycle startswhere each step in the process is assumed to have anin-control mode of operation, which delivers a highyield. After a random length of time, an excursion takesplace, causing lower yields. At this point, the inspectionsampling strategy determines how quickly the excur-sion is caught and fixed, restarting the in- and out-of-control cycle. It is sought to minimize financial loss bycatching the excursions quickly, i.e., minimizing the timebetween excursion start and detection. It is here thataccounting for yield management during fab planning isrelevant. A significant portion of the delay to excursiondetection is simply the time to get lots to the inspectiontools. If a fab has badly placed tools and/or automatedmaterial handling systems that cannot accommodate

the extra handling loads due to yield management,detection delays can be unnecessarily long and costly.Planning to prevent this type of problems is simply aclassic sample planning problem with a greater focus onmaterial handling and cycle-time modeling to providethe data needed that characterize a fab layout. Therefore,outputs of material handling and cycle-time modelingperformed during fab planning need to be made availableto sample planning analysts who, in turn, can give feed-back on the current fab plan strengths and weaknessesin excursion detection. The importance of having shortdetection delays to achieve the accelerated, and veryvaluable, yield learning rates should also be noted.

Fab planning with sample planner 3Involving SP3 in fab planning requires the fab to providegood models for material-handling and cycle-time estimation. Then, by combining the outputs of thesemodels with pilot line or applicable 200 mm data tocharacterize process variance and defect/excursionbehavior, SP3 can quantify the yield losses to excursions.

Typical analysis may involve the comparison of farm andhybrid layouts. A farm layout is where all the metrologytools are kept in a separate bay, while a hybrid layouthas the metrology tools in the same bay as the processtools they are monitoring. A good materials handlingmodel will be able to provide the travel times as afunction of the track layouts, number of stockers, number of automated vehicles, the load on the system,etc. Joining that with a cycle-time model that accountsfor processing and queuing times, a comprehensiveestimation of how long it will take lots to reach theirinspections is realized for both the farm and hybridlayout. SP3 can than use these results to quantifywhich layout will cause greater yield loss to excursions.Assuming that the material handling system and thenumber of inspection tools used is the same for bothlayouts considered, the differentiation comes down tothe losses due to excursions. The analysis can clearlyinvolve greater complexity where the cost of differentmaterial handling options and inspection tool capacityneeds to be accounted for as well.

Initial 300 mm work and past experience have high-lighted the following as the main drivers for inspectioncapacity:

• Fab output (square centimeters of silicon/week)

• ASP/product

• Excursion frequency, types, magnitude, & yield impact

• Tool capability/sensitivity

• Material handling in fab/distance to inspection tools

• Inspection tool throughput/queuing

ConclusionThe economies of scale that are achieved with the 300 mm initiative have a flipside when it comes to yieldmanagement. The value of the material on each waferis greater and more sensitive to excursions than everbefore, calling for a much more careful planning anddeployment of inspection capacity. Of concern is thepossible emergence of new inspection points that aredetailed in this paper. This is particularly relevant giventhe level of automation that is planned for 300 mmfabs that make it harder to alter layouts after the fact.Unless a fab correctly accounts for yield managementduring fab planning, there is risk of giving a fab aninherent handicap in yield management and losingconsiderable amounts of material to excursions. Thoselosses can significantly affect the gains foreseen from theeconomies of scale that drive the 300 mm initiative.

References1. Chatterjee, A. Personal Communication, Nov-Dec 2000,

KLA-Tencor, San Jose, CA.

2. R. Elliott, R. K. Nurani, S. Lee, L. Ortiz, M. Preil, G.Shanthikumar, T. Riley, and G. Goodwin, “Sampling planoptimization for detection of lithography and etch CDprocess excursions,” in proceedings of SPIE Metrology, In-spection, and Process Control for Microlithography XIV, vol.3998, pages 527-536, 2000.

3. Nurani, R., Gudmundsson, D., Preil, M., Nasongkhla, R.,Shanthikumar, G. Critical dimension sample planning forsub-0.25 micron processes. Proceedings of the 10th An-nual IEEE/SEMI Advanced Semiconductor Manufactur-ing Conference and Workshop, September 8 - 10, 1999.

4. Nurani, R.K., Gudmundsson, D., Stoller, M., Shanthikumar,G. Intelligent Sampling Strategies for Combined Opti-cal/E-beam inspection. Yield Management Solutions, Vol2, Issue 2, Spring 2000, p 28.

5. Wright, R. et al., “300 mm Factory Layout and AutomatedMaterial Handling”, Solid State Technology, December1999.

6. Campbell, E. et al., “Simulation Modeling for 300 mmSemiconductor Factories”, Solid State Technology, Octo-ber 2000.

7. Wil l iams, R.R., Gudmundsson, D., Monahan, K., Nurani, R., Stoller, M., Shanthikumar, G. Optimized SamplePlanning for Wafer Defect Inspection. IEEE InternationalSymposium on Semiconductor Manufacturing, Santa Clara,California, October 11-13, 1999.

8. S. A. Kekare, et al. “Integration issues in effective removalof SiON anti reflective coating used in deep sub-micronCMOS gate layer definition.” MRS meeting-Spring 2000.

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significantly, making it vital to forecast such variablesthrough several design rules before deciding on a strat-egy. When all of these considerations are taken intoaccount, our analysis shows that the fact that particledetection can be integrated to a process tool does notnecessarily make it the most cost effective strategy for300 mm fabs.

Trends affecting the decisionIn order to determine whether or not an integratedinspection strategy makes sense for the fab, it is impor-tant to understand the variables that drive yield losses,and how technology trends are affecting these variables.

Cu/low κTime-to-Detect Frames the Integrated Debate

Ralph Spicer, Dadi Gudmundsson, and Raman Nurani, KLA-Tencor Corporation

Is integrated defect inspection really the wave of the future? Analysis shows that a simple particle detection strategy isunlikely to be more cost effective than a comprehensive excursion inspection strategy, even if the particle detection can be integrated to a process tool.


The decision whether or not to integratedefect inspection onto process tools is one ofthe most important decisions facing 300 mmfab planners. This decision impacts every-thing from capital procurement strategies,to automation, to floor-planning, to datasystems integration. And, once made, thisdecision is expensive, if not impossible, tochange as the fab approaches first silicon.Therefore, it is important to understand thereal variables behind this decision, movingbeyond surface arguments that would appearto point strongly in favor of integration.This article discusses the relevant issues thatmust be analyzed when making decisionsregarding the deployment of integratedversus non-integrated defect inspection in a new 300 mm fab.

The decision to integrateRecent arguments for integration citeequipment productivity as the driving variable upon which the decision should bebased. While this is an important factor, itis also important to consider variables thatdrive yield, such as process tool excursionfrequencies, defect kill probabilities, and thedetection capability of the integrated andnon-integrated systems being considered, as illustrated in Figure 1. Furthermore,while productivity-related variables remainrelatively constant through design rule generations, the yield-related variables scale

Figure 1. A multitude of factors must be considered when deciding on

an inspection strategy for a 300 mm fab. These include productivity

factors such as cycle time and process tool output, and yield factors

such as step yield, process development, and the capabilities of the

inspection technology.

InspectionStrategyDecision

Fastest RampHighest Yard

Minimum Cycle Time

InspectorDetectionCapability

FloorSpace

Reliability

Orocess ToolProductivity

Layout CueueTimes

Automation

ExcursionFrequencies

KillProbabilities

DefectTypes

Yield LearningSupport

Design RuleExtendabilty

ExcursionTime toDecision

FalseAlarmRate

INSPECTIONTECHNOLOGY

PROCESS TOOLOUTPUT

CYCLE TIMESTEP YIELD

PROCESSDEVELOPMENT


The industry has extensive experience in optimizing fabyield and productivity through the use of standaloneinspectors. In the paragraphs that follow, we will reviewsome of this experience, and focus on the issues that anintegrated inspection approach can introduce to a fab.

Defect typesA robust excursion control strategy must be capable offinding the defect types expected in today’s aggressivedesign rules, and must be adaptable to find the newtypes that are certain to occur in the future. Simpleparticle detectors are suited to find one particulardefect type (large particles), but provide no capabilityin detecting other killer defects. True wafer inspectioncaptures both process-induced and tool-induced defecttypes with a high probability of detection (pd).Examples of these defect types for Cu CMP are shownin Figure 2. Particles, of course, are captured as well,making additional particle detection inspectionsunnecessary.

New processes and advanced design rulesAt advanced design rules, defect densities must decreaseto achieve viable yield1. As defect densities fall, thedefinition of an excursion becomes tighter, meaningthat the inspection system must be able to detectsmaller and smaller amplitude excursions without anundue increase in false alarms. The choice of appropriateinspection equipment typically includes a requirementfor multiple-design-rule reuse; this is not supported bysimple particle detection technologies.

While it could be argued that particle detection technol-ogy is likely to improve in the future, such technologywill remain behind the need as advanced design rulesand new materials like copper and low-κ dielectrics areintroduced. As design rules shrink, fewer excursions arecaused by people and process tool contamination, making

The two primary yield-related variables are:

Defect types: Does the inspection strategy have a highprobability of detection (pd) for the defect types thatcause yield loss? Will it keep up with the (as yetunknown) defect types that will occur as design rulesshrink and new processes such as copper dual damascene,low-κ dielectrics, DUV resists and SOI are introduced?Will it be able to adapt as yield learning in the fabproceeds?

Time to detection: Does the approach minimize thetime to detect the excursion? Can much of the benefit ofintegration be achieved through well-planned productflow and automation instead?

With probability of detection and time to detection asthe two main variables, a summary question arises: Is itbetter to detect a larger variety of excursions with somedelay, or detect a subset of excursions with little delay?We studied this question as a part of a comprehensivestudy of integrated inspection technology. The resultsof this study led to the following key observations:

• The excursion detection capability of a robust, com-prehensive inspection strategy appears to outweighthe time-to-detect (td) benefits of integration.

• Significant time-to-detect (td) benefits may be achiev-able through optimized automation and fab layoutwithout the loss of flexibility and added capital costassociated with integration. Integration per se haslittle incremental benefit once automation and fablayout are optimized.

• The choice of inspection strategy must include provi-sions for future trends, such as new copper and low-κdefect types, and the growing importance of processmargins and systematics as a source of excursions.


Figure 2. A comprehensive defect inspection strategy must detect the wide range of defect types that can cause yield loss. Many of these defect

types, such as these Cu CMP defects, cannot be captured by simple particle detectors.

Metal Residue Micro ScratchCorrosion Slurry Residue Cu Flake Scratch Particles Voids (from EP)


particles a less important part of the picture relative toprocess-induced defects. This is due to the fact thatenvironmental and equipment-induced particle sourcesare steadily being reduced and do not scale with designrule to the same extent as margins and systematics thatare continually being pushed at each successive designrule generation, making such issues more likely at eachsuccessive design rule generation2.

Inspection’s role in fast rampThe ability of a fab to quickly ramp new processes is amajor contributor to profitability. The faster the ramp,the faster the time to market, the higher the averagedevice ASP.

The choice of inspection approach can have a majorimpact on the fab’s ability to ramp quickly. This isbecause the problems being solved during ramp are ofa very different nature than those being solved duringhigh volume production. During development andramp, problems tend to be unpredictable; that is, new,


unexpected problems tend to dominate. An inspectionstrategy that is to be effective during ramp must be ableto capture defect types that cannot be predicted a priori.

In contrast, once the fab reaches entitlement yield, it isless likely that new defect types will occur, makingdefect inspection much more predictable. This mightlead to one asking whether the fab should invest insensitive inspectors for ramp and development, andthen switch to particle monitoring equipment duringproduction, even though non-particle defects wouldstill be present to some degree.

Two important trends indicate that more sensitive toolsare needed throughout the fab’s life, as shown in Figure 3.First, the yield “hurdle” that a process must pass priorto moving into ramp and production is moving everhigher, with a faster ramp. This means that there is lessand less time to qualify lesser-capability inspectionequipment to check that it finds the defect types iden-tified during development. Secondly, the time periodbetween process changes is decreasing, meaning that

Yiel

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• Most problems UNPREDICTABLE• New rocess-induced defect types

• Highest priority: YIELD LEARNING• High sensitivity/high capture• Accurate classification/quick sourcing

• Most problems PREDICTABLE• Defect types as determined during

development/ramp• Highest priority: EXCURSION CONTROL

• Fast time to detection• False alarm supression

• Development and Ramp

Figure 3. Development and ramp drive fab profitability: the faster the ramp, the faster the fab can profit from higher ASPs. Most fabs are always in

the development and ramp states, even after years of time, as new processes and shrinks replace older, lower ASP production products.


the typical fab is always in a development/ramp state.The net result is that today’s fab requires ever-more-capable excursion inspection capability to detect ever-changing defect types.

These observations imply that a robust tool monitordefect inspection approach must incorporate the learn-ing from higher-sensitivity line monitor inspectors, asdepicted in Figure 4. This allows the tool monitorinspectors to be tuned for new excursion types that arecertain to be introduced by process changes or designrule shrinks. Experience suggests that without thisvital feedback loop, it is impossible to sustain yieldlearning over time. While state-of-the-art standalonedefect inspectors are able to adapt via this feedback,simple particle detectors cannot. Thus, a key elementof excursion control would be eliminated were an inte-grated particle detector strategy to be chosen.

Operational aspects of integrationThe decision to integrate has major operational impactsto the fab:

• One inspector is required for each process tool orcluster, meaning that there are more inspectors in the fab

• Each inspector is tied to its process tool, meaningthat a given inspector can only inspect wafers fromits process tool.

Obviously, capital cost is a major consideration. Typicalstandalone implementations utilize a ratio of anywherefrom 4:1 to 10:1 (that is, 4 to 10 process tools perinspector). Unless the integrated particle detectors aresignificantly less expensive than the standalone defectinspectors, the increased quantity of inspectors leads toa higher capital investment cost for the fab. Also, inte-grated inspectors add to each process tool’s footprint,reducing product output per unit area.

False alarming is also a major consideration. Operatorsand engineers must respond to each report of an excur-sion as it occurs. As the simple technologies employedby particle detectors are readily confused by process-induced pattern variation on product wafers, they risk ahigher incidence of false alarms than defect inspectorsthat incorporate technologies developed specifically tosuppress such pattern variation. It is easy to see how alarger number of particle detectors, each false alarmingmore often, would lead to an intolerable distraction onprocess operations, or, worse yet, lead to process opera-tions which either ignore alarms or “dumb down” therecipes to prevent them. These are situations thatwould completely negate the benefits of integration.

Reliability is also a concern. With the particle detectordedicated to the process tool, a failure in the detectorleads to a downed process tool (leading to lost produc-tivity), or skipped inspections (leading to a possibilityof an undetected excursion). Unless MTBFs andMTTRs of the particle detectors can be raised to levelsmany times better than that which is achievable today,


Process Flow

Films Bay CMP Bay Litho Bay Etch Bay

High-Volume Inspections Tool Monitoring for Excursion Control

Drives which excursiontypes to monitor

Line Monitoring for Yield Correlation

DSA/Correlation

• Decide process tool go/no-go based on SPC• Data Customer = Process Engineering• Must be able to detect newly identified types

• Identify yield limiting defect types• Data customer = Yield Engineering

High-Sensitivity Inspections

E-test

Figure 4. A robust process tool monitoring approach includes the ability to feed back learning from more sensitive line monitoring inspectors.

Without this feedback, it is dif ficult to control new excursion types introduced by new processes or design rule shrinks.


the sheer number of inspectors in the fab implies that atleast one inspector will be down nearly all of the time,along with its associated process tool. A standaloneapproach, on the other hand, allows lots to be routedaround downed inspectors in a way that is difficultwith integration.

Past studies of excursion control in 200 mm fabs indi-cate that the average time between lot processing andexcursion detection in a typical fab can be eight hoursor more3. This means that the average excursion affectsyield across several lots of wafers before the source ofthe excursion is identified and action taken. One of theprimary perceived benefits of integrated inspection isthat this time is reduced significantly, since wafers can beinspected soon after processing. But, integration of theinspector to the process tool is only one way to reducethis time. For example, reducing queue and transporttime from eight hours to two hours via efficient layoutand inspector utilization would gain much of the benefitof integration while retaining the flexibility of a stand-alone inspection strategy. Such 300 mm automationconcepts as multilevel transport and intrabay shuttleshold promise in making this feasible.

We plan further modeling studies to quantify howthese operational variables feed into the decision of anoptimized excursion detection strategy.

Modeling integrated versus standalonestrategiesGiven that there is significant industry effort towardintegrating particle detectors, we set out to answer thequestion: which approach minimizes excursion losses inthe fab: (1) a simple particle detector integrated to eachprocess tool, or (2) a comprehensive defect inspectionstrategy implemented in a standalone fashion? Ourpreliminary results are that the second approach is theoptimal strategy for the process steps we studied.

Using KLA-Tencor’s Sample Planner™ software4, wewere able to model the effects of defect type captureand inspection delay (such as that caused by transit,queueing, and inspection times) on the overall yieldloss for various process steps. An example of the resultsof this study for Metal 3 etch are shown in Figure 5.The two curves show the value of inspection at Metal 3etch for a 5000 wspw, 300 mm logic fab relative toperforming no inspection at this step. As one wouldexpect, the value increases as time to detection (td)decreases, since excursions are caught sooner. However,

this increase in value is much more pronounced when acomprehensive defect inspection strategy is used, sincethe particle detection approach misses many excursionsentirely, negating the benefit of decreased td. In fact, thecost of missed excursions is so substantial that, even withan eight-hour td, the standalone inspection approach pro-vides a 30 percent yield benefit over an integrated particledetection approach ($1.3 m/year versus $1.0 m/year).

The cost of the inspection tools has to be consideredwhen comparing the value curves in Figure 5. Whenlarge scale integrated defect inspection was first con-ceptualized, it was clear from the start that each inte-grated inspector would have to cost considerably lessthan a standalone tool. This is clear from the fact thatstandalone tools are serving anywhere from four to tenprocess tools and an integrated inspector would serveonly one tool. For this analysis, whether standalone orintegrated inspection is used, it can be assumed thatthe overall inspection expenditure is the same. Thisarises from the observation that the price of integratedtools for our example are about a third of the stand-alone tool price. In addition, this particular examplerequired slightly less than a third of a standalone’s toolcapacity to serve one M3 etcher. That same etcherwould require a single integrated inspector for itself,demonstrating the approximate cost equivalence. Thisfollows the trend that to make integrated tools feasiblethey have to be cheaper; unfortunately, that can only berealized at the expense of detection capability.

This analysis only quantifies the value of excursion control. The benefits of fast ramping due to accelerated


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$3.5

$3.0

$2.5

$2.0

$1.5

$1.0

$0.5

$0.00 1 2 3 4 5 6 7 8 9 10

Detection Delay td (Hours)

Valu

e of

Im

prov

ed Y

ield

($m

/yea

r, re

lati

ve t

o in

spec

tion

)

Sum of material handing (transit + queueing) and inspection times

Large Particle DetectorComprehensive Inspector

Loss Due toUndetectedExcursions

Integrated Particle Detector

Comprehensive -Standalone

(Unoptimized MH)

Comprehensive -Standalone

(Optimized MH)

Figure 5. Particle detectors risk a substantial loss at M3 etch for a

5,000 wspw, 300 mm fab due to missed excursions, when comparing

an integrated particle detector to a 2-hour-td comprehensive standalone

approach. Even with an unoptimized material handling time of eight

hours, the comprehensive standalone approach shows a benefit over

the integrated particle detector.


yield learning are harder to model, but experienceshows that these benefits would further tilt the resultsin favor of comprehensive standalone inspectors.

These results indicate that substantial benefit can bederived through effective material handling time

reduction when using comprehensive standaloneinspectors.

We now explain in more detail the key variables thatdrive excursion-related yield losses, and how these wereanalyzed to produce the values in the above figure.

What is an excursion?An excursion is defined as an out of control conditionat a single process step which impacts yield until theexcursion is corrected. As shown in Figure 6, a fab’sbaseline yield rises over time as yield learning isachieved. Excursions represent temporary dips in thisyield, corresponding to a loss of profit. The goal of acomprehensive yield management program is one thatraises baseline yields as high as possible as quickly aspossible (hitting the “sweet spot” of high device ASPs),coupled with an effective strategy for preventing andminimizing the impact of excursions during volumeproduction.

In order to determine the best strategy for minimizingthe financial losses from excursions, it is important tounderstand in greater detail where these losses comefrom. Figure 7 shows a more detailed timeline of anexcursion and its losses for two situations: when the

Yiel

d %

Baseline Yield

Excursions

Time

Yiel

dLe

ar

ning

Figure 6. The baseline yield of the fab drives its baseline profitability.

Excursions represent temporary drops in yield, resulting in lost profit

for the fab.


Yield Loss (Ly) - missed excursionCy

Cy

td

td

ttp

Ctp

Ctp

ttp

Scrap Product

Process Tool Productivity Loss (Ltp)

Process Tool Productivity Loss (Ltp)

Yield Loss (Ltp)caught

excursion

Scrap Product Good ProductGood Product

Good Product Good Product

Event OccursChamber Down

Chamber DownEvent Occurs

Chamber Up

Chamber Up

XXX

missed excursion

Figure 7: The financial loss due to an excursion consists of two primary elements: yield loss due to wafer scrap and/or die yield impact, and loss

due to reduced productive tool time. An excursion that is not detected by the defect inspector increases yield loss dramatically.


defect inspector detects the excursion (upper half of fig-ure), and when it does not (lower half of figure). Threepoints in time define the timeline: (1) the time that theexcursion event occurs, (2) the time that the chamber(e.g. deposition chamber or polishing head) is takendown, and (3) the time that the chamber is returned toproduction.

Before the excursion event occurs, production lots arebeing processed normally. When the event occurs (forexample, a problem with one etch chamber), productcontinues to move through that chamber, causing lotsthat will have to be partially or completely scrapped.This occurs until the event is detected and confirmed,and the chamber is taken down. Then, the tool is ser-viced, during which time no product is being processedby the chamber. Finally, the chamber is confirmedfixed, and processing resumes.

The shaded regions of the figure depict the losses thatoccur. First is the yield loss (Ly). This is defined as thetime to detect the excursion (td) times the cost of theyield loss (cy) per hour. Second is the process tool pro-ductivity loss (Ltp). This is the number of hours it takesto repair the chamber and bring it back into produc-tion (ttp) times the capital cost of the tool per hour. Togive some sense of scale to the timeline, our experiencein 200 mm fabs indicates that an average number for td

is approximately eight hours, and for ttp 16 hours, incases where the excursion is caught.

The cost of yield loss (cy) is driven by two variables:excursion yield impact, and die ASP. Yield impact isthe probability that a given excursion type will causean electrical failure in a given die. For example, amicro excursion might cause sparse defects that kill, on average, 25 percent of the die on the wafer (yieldimpact = 0.25), whereas a macro excursion might impactevery die on the wafer (yield impact = 1), leading tocomplete wafer scrap.

For the case where the yield impact is less than 1, onemight expect cy to scale with the yield impact; that is,a yield impact 0.5 excursion would lead to a cy of halfof the yield impact 1 value. However, wafers will stillbe scrapped completely if the number of failed dieexceeds a threshold beyond which the cost of continu-ing the wafers’ processing does not justify the smallernumber of good die that will result.

One immediate observation is that the cost of excur-sions is influenced heavily by product and yield-related

variables. So, while it may appear that an obvious inte-grated strategy would be to set a capital cost target forprocess tools’ integrated inspector (say, 20 percent of theprocess tool’s cost), this is likely not the cost-minimizingapproach. The cost-minimizing approach takes intoaccount the cost of yield loss for the process step. Forexample, benchmarking studies indicate that the typicalinspection investment is higher for early metal layersthan for later metal layers, due the tighter design rulesand higher defectivity encountered there, even thoughthe exact same process tools are being used. One sideeffect of integrating inspection into the process tool isthe absence of this kind of investment flexibility. For acomplete discussion of this topic, see reference5.

Another observation is that great leverage can beobtained by reducing td by reducing the time it takesto make a tool up/down decision. By removing the possibility of incurring queue time at standaloneinspection, td can be reduced dramatically. This is theobvious attractiveness of integrated inspection.

However, past experience indicates that a missed excursion is usually not detected until days later, whenthe lot is inspected by a more sensitive line monitorinspection, by the next step’s tool monitor inspection,or worse, by back end final electrical test. Most fabshave had the painful experience of an extensive “yieldbust” because of a defect type that was not detected bythe inspection equipment.

A higher probability of excursion (pe), combined with alower probability of detection (pd), make this undesir-able scenario more likely. Another way of looking atthe same issue is to use a weighted value for the timeto detect,

Td(effective) = td(caught) * pd + td(missed) * (1-pd)

Given the potentially immense losses associated withmissed excursions, it is dangerous to choose an inspec-tion strategy without analyzing pd.

To analyze pd, we utilized a historical root cause data-base and benchmarking data, combined with a surveyof process experts to create an exhaustive list of thedefect types and frequencies typically encountered atvarious process steps. We then assessed the capabilityof various inspection and particle detection approachesagainst these defect types. A subset of this assessmentis shown in Figure 8. Here, the frequencies of excur-sion are multiplied by the pd for that excursion type to



generate the results we showed earlier (see Figure 5).The comprehensive standalone approach indicatedgreater benefit than the integrated particle detectionapproach. Again, these results do not include the bene-fit of fast yield learning, a benefit that experience showsto be substantial.

obtain an event-weighted pd for the process step forvarious types of product wafers. These are then com-bined to obtain a die-weighted pd. Of course, thisanalysis is not static. As process tools mature anddesign rules shrink, we expect a decrease in the fre-quency of particle excursions, and an increase in thefrequency of process-induced excursions.

We found that simple particle detectors missed a sig-nificant number of the excursion events at state-of-the-art process rules, reducing pd considerably when com-pared to today’s standalone tool monitor inspectors.This, combined with the comparable effective through-put of darkfield inspectors and particle detectors (dueto real-world factors such as wafer handling and align-ment time), leads to a summary of average pd vsthroughput for various inspection technologies such asthat shown in Figure 9.

We then loaded the resulting probabilities of detection(pd) and throughputs into the Sample Planner™ model,which allowed us to more accurately model the interac-tion between the probabilities of detection, excursionfrequency, sampling strategy, integration approach, andreal-world issues such as transit and queue times.

We modeled a range of td, from the historical averageof eight hours of td, to an optimized standalone td oftwo hours, and on to an integrated td of 15 minutes to

Examples FailureMechanism

ArcingDeposits as a result ofgrounding failur l.e.

arching

Aluminum ballsshards on

wafer surface

Flakes/particleson wafersurface

Surfaceparticles

0.25 events/month:Increases with

MWBC and RF time


MWBC and RF time

2 events/month:Increases with

MWBC and RF time


MWBC and RF time

Firstoccurance

on particularchamber

Firstoccurance

on particularchamber

SPC based(2 out of 3consecutivelots O.O.C.)

SPC based(2 out of 3consecutivelots O.O.C.)

Deep scratch ina line on wafer

map

Polymer (organic andinorganic) deposit fromelectrode degradation,

chamber walls and partssuch as o-rings

Mechanical failure- usually wafer handling

Polymer buildup on thewafer from the process

Particles

MechanicalScratches

Residues

Root Cause Appearance Frequency Tool-DownCriteria

ParticleDetector

2 0 0 2 2 2 2 2 2

2 0 0 2 2 2 2 2 2

2 2 2 2 2 2 2 2 2

2 0 0 2 2 2 2 2 2

Open

Arra

y

Logi

c

Open

Arra

y

Logi

c

Open

Arra

y

Logi

c

0 = low pd, 1 = medium pd, 2 = high pd

BrightfieldInspector

DarkfieldInspector

Figure 8. Defectivity benchmark and defect root cause data were used to evaluate pd for various inspection technologies.

Prob

abili

ty o

f De

tect

ion

(pd)

1

0

Low HighThroughput (Wafers/Hour)

E-beamInspection

BrightfieldInspection

ParticleDetection

DarkfieldInspection

Figure 9. The pd for particle detectors is significantly lower than

currently available darkfield, brightfield, and e-beam inspectors, with

effective throughputs comparable to darkfield inspectors. This is in

direct relation to the lower cost of integrated inspectors.


On the application front, metrology is applicable toadvanced process control concepts such as feedforward(e.g. modifying the etcher recipe based on film thicknessmeasurements) and feedback (e.g. modifying depositiontool parameters based on measured results from previouswafers). Defect inspection, on the other hand, does notlend itself to such applications: what would one adjuston an etcher were an excursion to be detected by thedefect inspector?

One proposed compromise solution for defect inspectionis the particle detector, which performs a type of defectinspection, but is able to capture only one type of defect(large particles). As we showed earlier in this article,capturing large particles is insufficient to prevent costlyyield busts due to lengthy out-of-control conditions.This is why particle detection does not lead to an optimal solution, even if it is integrated to the processtool.

ConclusionsOur conclusion is that a particle detection strategy isnot likely to provide benefit over a comprehensivestandalone inspection approach, even if particle detec-tion can be integrated to process tools.

This conclusion was driven by these observations:

• The excursion detection capability of a robust, com-prehensive inspection strategy appears to outweighthe time-to-detect (td) benefits of integration.

• Significant time-to-detect (td) benefits may be achiev-able through optimized automation and fab layout

Process control considerationsOne obvious question that arises is: if the economics ofintegrated inspection do not appear favorable, why isthere so much activity revolving around integratedtechnologies? The answer lies in the fact that three verydifferent classes of integrated technologies are beingpursued: integrated metrology, integrated particledetection, and integrated defect inspection. The differ-ences among these applications are significant (as shownin Figure 10), and so it is vital to analyze each separately.It is important not to confuse the technology andapplications of integrated metrology with those ofdefect inspection.

On the technology front, the nature of the items to bemeasured (the targets) are known with certainty. There-fore, once a technology has shown an ability to measuretargets with the required accuracy (for example, spectro-scopic ellipsometry’s ability to measure film thicknesson multilayer stacks to 0.5 percent) in a form factorwhich supports integration, there is higher confidencethat integration may be an appropriate path.

In contrast, defect inspection must take into accountthe added complexity of full-wafer scanning, whichimplies a highly variable background signal (the pattern)which reduces the signal-to-noise ratio of the inspection.The complex image acquisition and processing algorithmsrequired to achieve a useful signal-to-noise ratio are notcurrently available in an integrated form factor. In fact,because this problem becomes more difficult as designrules shrink, it is a distinct possibility that adequatewafer inspection performance may never be available inan integrated form factor.


Figure 10. The applicability of metrology to process control applications means that the decisions regarding the optimal

approach for metrology are very dif ferent from those for defect inspection.

Supported Fab Applications Technology

Tool Wafer Pass/ Tool Process Target/ Technology Go/No Go Scrap/ Feedforward/ Development Area Maturity vs.

Rework Feedback Feedback Standalone

Metrology Yes Yes Yes Yes Target Medium (CD, FilmThickness,Overlay)

Defect Yes Yes No No Full LowInspection Wafer

Particle Limited Limited No No Full Low Detection Wafer

without the loss of flexibility and added capital costassociated with integration. Integration per se haslittle incremental benefit once automation and fablayout are optimized.

• The choice of inspection strategy must include provi-sions for future trends, such as new Cu and low-κdefect types, and the growing importance of processmargins and systematics as a source of excursions.

These observations suggest that integrated particledetection may not necessarily be the future trend thatconventional wisdom might suggest. Integration ofinspection will only become viable when integratedinspection technology is comparable to standalonetechnologies, and today’s candidate integrated particledetection approaches are not near this point. Even inthe long run, the fact that inspection requirementsscale with the design rule suggest that the crossoverpoint at which integrated inspection becomes viablemay be a long way off, if it appears at all.


The authors would like to acknowledge the contribu-tions of Wayne McMillan, Anantha Sethuraman, PaulMarella, and Sanjay Tandon to the study.

References1. Stapper, C.H., Fact and Fiction in Yield Modeling.

Microelectronics Journal, vol. 20, no. 1-2, 1989,p.129-151

2. Jensen, D. State of the Industry Address, 1995.3. Esposito, T. et al. Automatic Defect Classification: A

Productivity Improvement Tool. Conference proceedingsIEEE/SEMI Advanced Semiconductor ManufacturingConference and Workshop, p. 269-276.

4. Williams, R.R., Gudmundsson, D., Nurani, R.K., Stoller,M., Chatterjee, A., Seshadri, S., Shanthikumar, J.G.“Challenging the Paradigm of Monitor Reduction toAchieve Lower Product Costs”. The 10th AnnualIEEE/SEMI Advanced Semiconductor ManufacturingConference and Workshop, September 8 - 10, 1999.

5. Williams, R., Gudmundsson, D., Monahan, K., Nurani,R., Stoller, M., Shanthikumar, G. Optimized SamplePlanning for Wafer Defect Inspection. IEEE InternationalSymposium on Semiconductor Manufacturing, SantaClara, California, October 11-13, 1999.

Order your copy of Chris Mack’sLithography Expert Booklet today! Log on to:

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Yield ManagementSeminar

A valuable venue for innovative ideasKLA-Tencor’s Yield Management Seminars (YMS) focus on value-added, integrated processmodule control solutions for defect reduction, process parametric control and yield management.Key topics include navigating the transition to the sub-0.13 µm technology node, with specialemphasis on copper/low-κ interconnect, sub-wavelength lithography, and the 300 mm wafer.

To register online for the upcoming YMS, please visit us at: http://www.kla-tencor.com/seminar

Date: Wednesday, January 30, 2002Time: 1:00 pm – 6:00 pm Location: Shanghai, China

Call for future papersPapers should focus on using KLA-Tencor tools and solutions to enhance yield throughincreased productivity and performance. If you are interested in presenting a paper at oneof our upcoming yield management seminars, please submit a one-page abstract to: Cathy Silva by fax at (408) 875-4144 or email at [email protected].

YMS at a GlanceDATE LOCATION

January 30 Shanghai, China

April 17 Munich, Germany

July 23 San Francisco, California


Cu/low κ

IntroductionChemical Mechanical Planarization (CMP)is a widely accepted polishing and pattern-ing method in microelectronics fabrication.Though CMP is indeed crucial to someprocesses—copper (Cu), for instance, forwhich plasma etching remains problemat-ic—process engineers must still cope withunderpolish and overpolish problems.Stopping a metal polish step too soon(underpolishing) leaves metal or barriermaterial residues, which cause electricalshorts in the target layer. Underpolishingdielectric films causes open circuit defects.Polishing too long (overpolishing) resultsin metal dishing and dielectric erosion,ultimately leading to metal pooling andshort circuits in higher metal layers. Simpletime-based polishing is widespread in fabs.But Cu electroplating produces film thick-ness variations that thwart timed recipes,and the requisite rate monitor wafers arebecoming prohibitively expensive. CMPtool conditions such as temperature, padcondition, and wafer pressure profile alsoaffect the polish rate and uniformity.

To facilitate CMP integration into large-volume production, process controllersmust have cross-wafer information availableand monitor each wafer’s polish profile to

determine the process endpoint (the precise time atwhich the target material has been removed) or theremaining requisite layer thickness. KLA-Tencor’sPrecision In-Situ CMP Endpoint (PRECICE™) systemaddresses these issues by providing real-time film thick-ness measurements, reflectance data, and endpointdetection for a variety of polishing processes, includingCu CMP.

Design: sensors, controller, and communications linksThe system contains an eddy current-based sensor; asingle wavelength, multi-angle reflectometer; a dataacquisition and control processor; and communicationlinks to the CMP host computer. The sensors mountbeneath the CMP tool’s rotary platen (Figure 1). Theeddy probe has a drive coil that induces a current inthe wafer, a sense coil to find in-phase and quadraturecomponents of the induced voltage, and signal genera-tion and data acquisition electronics1. The control com-puter’s calibration curves give absolute metal thicknessvalues, independent of temperature and pad wear. Thestandard optical sensor wavelength is 808 nm. Twomethods exist for creating an optical path to the wafer:a flexible polyurethane window inserted into the padand a self-clearing objective (SCO) that uses a timedflow of deionized water (DIW). Thus, wafer incidenceangles vary; with a SCO they range from 6.7° to 56.3°.A rotary union and slip ring on the table shaft bringfluid lines and electrical paths to table-mounted sensors.


CMP: Where Does It End?

Ron Allen, Charles Chen, Tom Trikas, Kurt Lehman, Robert Shinagawa, and Vijay Bhaskaran, KLA-Tencor CorporationBrian Stephenson and David Watts, Ebara Technologies Inc.

We describe the design, operation, and algorithms for an in-situ CMP endpoint detection and control system, with particularemphasis on copper polishing. The system’s eddy current-based sensor gives absolute surface metal thickness. Its multi-anglereflectometer gives eight optical reflectance measurements. The endpointer improves on existing sensors and techniques in severalways. It can process reflectance traces individually according to their endpoint sensitivity, which applies to dielectric polishing and copper barrier removal processes. Also, it merges reflectance signals for higher signal-to-noise ratios, whichbenefits copper CMP. Finally, the system can fuse the reflectance data with thickness readings for more robust endpoint detection.


In typical operation, the host computer downloadsrecipe data to the endpoint controller (Fiure 1). After adelay for polish process stabilization, data acquisitionfrom the eddy current probe and the multi-anglereflectometer begins. A proximity sensor, or, alterna-tively, the indication of the metal carrier ring from theeddy current device, triggers acquisition. Sensors reportdata on every platen revolution. The electronics serial-izes the data and passes it through the slip ring assem-bly to the computer. Before the next trigger, the con-troller’s algorithm software analyzes the data for char-acteristic endpoint features. When the algorithmsdetect the recipe’s prescribed endpoint feature, the end-pointer notifies the host, which stops the current polishstep.

Principles of operation: eddy currentprobe and multi-angle reflectometerEddy current probe principles are well-known for test-ing and metrology.2 By Faraday’s law, the EMF ε (volts)produced across the sense coil of N turns in MKS unitsis

ε = – N (1)

where φm is the magnetic flux (webers/m2) linking thecoil.3 Let εo be the open coil EMF generated when thesense coil is not over the wafer. As the probe scans thewafer, primary flux enters the Cu layers, inducing anEMF, and thus an eddy current by Ohm’s law. Theeddy currents reduce the primary flux. As the sense coilpasses over thicker Cu regions, the flux moves throughdeeper layers of metal, decreasing the linkage flux, andreducing the voltage magnitude across the sense coilfrom εo (Figure 2). Calibration of the sensor involvesan estimate of εo and a measurement of ε for a Cu sam-ple wafer of known thickness, such as may be measuredwith a four-point probe. A referencing scheme isemployed to compensate for temperature and pad wear.For pass k over the wafer and each wafer sample n, themetal thickness is

T(n) = Scal[||ε(n) – εo(k)|| – Dcal]*Cpt(k) – Wres, (2)

where ε(n) is the complex EMF; εo(k) is open coil EMF;Scal and Dcal are calibration scale and offset, respectively;Cpt(k) is the pad and temperature compensation, andWres is an optional offset for a low resistivity wafersubstrate.

The multi-angle reflectometer can be understoodthrough modeling the reflectance and transmissionthrough the optical objective to the wafer.4 The wafer


Figure 1. System layout, top view. Proximity sensor triggers data

acquisition as eddy probe passes carrier ring. Slip ring passes serial-

ized eddy and optical data to controller. Dual-platen polishers, such

as Ebara’s FREX-300™, may have CW rotation tables; such setups

have proximity flags before the reflectometer.

0

-5

-100 50 100 150 200 250 300

0

-5

-100 50 100 150 200 250 300

0

-5

-100 50 100 150 200 250 300

0

-5

-100 50 100 150 200 250 300

Figure 2. Evolution of in-phase eddy sensor signal: 200 mm 931

patterned test wafer; 27-Jan-2001; 300 samples/channel; vertical

lines are wafer edges; platen RPM: 70; cycles 50, 100, 150, 200.

TABLES AND FIGURES

Table rotation CCW

Reflectometer

Sensor path

Proximitysensor

Eddy currentprobe

Acquisitionelectronics

Slip ring

Carrier ring

Endpointcontrol

computer

Polisherhost

computer

Wafer

dφm ,dt


consists of isotropic media M0, M1, …, Mm+1; withcomplex refractive indices N0, N1, …, Nm+1; whereM0 is the semi-infinite ambient (e.g., DIW); Mm+1 isthe semi-infinite wafer substrate; Mi has thickness di, 1 ≤ i ≤ m; the angle of incidence is φ0; and the angleof refraction in Mi is φi, 1 ≤ i ≤ m+1. The 2×2 scatter-ing matrix is the product

S = I01L1I12…LmIm,m+1/(t01t12…tm,m+1), (3)

where Li and Ii,i+1 are the layer and interface matrices,

e jβi 0 1 ri,i+1Li = Ii,i+1 = ; (4)

0 e–jβi ri,i+1 1

βi = [2πdiNicos(φi)]/λ is the layer phase thickness; λ isthe wavelength; ti,i+1 is either the p- or s-polarization

Fresnel transmission coefficient

(5a)

; (5b)

and ri,i+1 is either the p- or s-polarization Fresnel reflec-tion coefficient

(6a)

. (6b)

Thus, via p- or s-polarization values, the wafer trans-mission coefficient is t = (S11)-1, the reflection coeffi-cient is r = S21/S11, and so the reflectance is R = |r|2.Varying di at Mi’s polish rate and computing R at eachstep produces a model of the CMP process. The model(Figure 3) establishes threshold and time delay parame-ters for endpoint detection algorithms.

Endpoint detection algorithmsEndpoints of interest to the Cu CMP process engineerare: bulk copper to a specified thickness, copper clear,and barrier clear. Endpoint on eddy probe values (2) is assimple as specifying the absolute target thickness. ThinCu endpoints rely on reflectance values whose endpointbehavior is governed by the thin film model (3)-(6).

Wafer areas do not clear uniformly, of course. To spatiallyresolve endpoint declarations, the system either (1)divides the wafer into simple annular zones or (2) computes the actual sensor path. The sensor electronicssamples at uniformly timed rates so, in either case, thesensor spots do not cover the wafer uniformly.

The carrier and platen (Figure 1) rotate at Rc and Rp

RPM, respectively, so their angular orientations are:

ω(t) = 2tπRc/60 φ(t) = 2tπRp/60. (7)

If the machine- and carrier-relative coordinate systemsare (x, y) and (u, v), respectively, then the sensor pathrelative to (x, y) is

Pxy (t) = (rs cos( ),rs sin( )). (8)

In (u, v) coordinates, with the carrier not rotating, thispoint path would be

Puv (t) = (rs cos( )–rs, rs sin( )). (9)

where rs is the sensor path radius.

Now, if a point has coordinates (a, b) in the carrier (u, v)system, and the carrier rotates by an angle ω, then the


Polis

h st

ack:

Cµ[

2000

A]/T

a[20

0A]/

SiO2

[300

A]/s

ubst

rate

Thickness removed (Å)

1

0.5

0

1

0.5

0

1

0.5

00 1000 2000 3000 0 1000 2000 3000 0 1000 2000 3000

Sensor-1 6.7" Sensor-2 13.5" Sensor-3 20.2"

Sensor-4 27.1" Sensor-5 34.0" Sensor-6 41.1"1

0.5

0

1

0.5

0

1

0.5

00 1000 2000 3000 0 1000 2000 3000 0 1000 2000 3000

Sensor-7 48.5" Sensor-8 55.3" Average1

0.5

0

1

0.5

0

1

0.5

00 1000 2000 3000 0 1000 2000 3000 0 1000 2000 3000

Figure 3. Reflectance model for a Cu (2000Å) wafer, 200Å tantalum

barrier, and 300Å of oxide overpolish. Vertical axes: reflectance.

Horizontal axes: material thickness removed (Å).

[ [] ]

2Nicos(φi)Ni+1cos(φ i) + Nicos(φ i+1)

ti,i+1, p =

2Nicos(φi)Ni cos(φ i) + Ni+1cos(φ i+1)

ti,i+1, s =

ri,i+1, p =Ni+1cos(φ i) – Nicos(φ i+1)Ni+1cos(φ i) + Nicos(φ i+1)

ri,i+1, s =Ni cos(φ i) – Ni+1cos(φ i+1)Ni cos(φ i) + Ni+1cos(φ i+1)

2tπRp

60

2tπRp

60

2tπRp

60

2tπRp

60


new coordinates of the point will be

(10)

This means that after rotation by ω(t), the coordinatesof the sensor over the wafer, relative to the (u, v) coor-dinate system will be

(11)

Once thick Cu clears locally, the system relies on theoptical sensors to find remaining thin patches. Thealgorithm, a conventional blob analysis5, is as follows:(1) Cu reflectance values are combined to get a compos-ite optical trace (Figure 3), (2) the algorithm sets areflectance baseline Rb across the wafer. At this time,Cu is still fairly thick, and the reflectance should benear its theoretical average (slurry effects and processstep changes can harm the Rb calculation, but standardprocess trend and control chart techniques greatly mit-igate the risk6); (3) Points where Cu remains are foundby comparing reflectance to this baseline value. Thus,if T is the threshold, and Rm is the measuredreflectance, then Cu is present at sample n if

Cu (n) = 1 ⇔ Rm (n) ≥ T * Rb (n) • (12)

(iv) Median filtering the Cu array fills narrow gapsbetween high R regions. (v) The width of the contigu-ous Cu regions is determined, and where the widthexceeds a percentage of a zone width, a Cu blob isdeclared for the zone. If W is the zone width, Tw is thethreshold, and Blob(m,n) means there is a Cu blob inthe region [m, n], then we have

Blob (m,n) ⇔ Min Cu (k) | m ≤ k ≤ n = 1&Cu(m – 1) = 0&Cu(n + 1) = 0&n – m ≥ W*Tw

The percentage of blob points that intersect a zone iscalculated from the blob array. Though the systemacquires data at fixed time intervals, the wafer samplesare not uniformly spaced. However, the sensor path(11) gives the spatial extent of Blob(m,n). Precessioncalculations using the carrier and platen RPM providethe relative location between successive wafer sweeps.(4) Finally, Cu clear endpoint occurs when the percentageof blob points in a zone is less than a threshold. A time

delay, proportional to the sensor path (11) coverage ofwafer zones, reduces false positives. Figure 4 showsreflectometer data for a 200 mm Sematech 931 patternedCu test wafer.

The Cu thickness and reflectance values can be fused.One technique fits a regression line to thickness valuesto predict clearing. The reflective patch analysis (12)-(13) confirms Cu clearing. Another method is to opti-mize a local thin film model using the measured reflec-tivity and thickness values.

ConclusionThe eddy current sensor measures impedance vectors as opposed to simple scalar measurements offered bycompeting eddy current devices. Absolute measurementmakes CMP process recipes easy to establish, reliable,and portable. Absolute thickness capability also allowstools to be dynamically controlled for within-waferuniformity. After bulk metal clear, the application software merges the eddy current and reflectometrysensors’ data streams within their overlapping ranges; a crisp and repeatable soft landing to the copper-clearendpoint results.

Multiple angle reflectometry advances CMP monitor-ing and diagnostics by giving process engineers morerepeatable and flexible control over endpoints. Softwarecan combine these reflectance signals, improving sig-nal-to-noise ratios, or analyze them separately, forincreased robustness of endpoint control on certain thinmetal films. Depending on the process and film stackproperties, some angles may give a stronger endpointsignal than others (Figure 3). Real-time wafer mapping


(13)

Figure 4. Reflectance data from an edge-slow polish of a 200 mm

patterned Cu wafer.

Fall 2001 Yield Management Solutions36

of metal thickness, non-uniformity, and copper patchesallows for dynamic feedback control during CMP andresults in a sharp and reliable copper-clear endpoint.The in-situ endpoint system shortens process develop-ment cycle, eliminates underpolishing, and reducesoverpolishing to increase yield.

Multi-angle reflectometry allows the endpointer to sup-port other CMP applications: shallow trench isolation (STI)and tungsten processes. Single angle reflectometry hasbeen tried for STI, but the reflectance signal featurethat signifies endpoint is not unique. Such endpointersdepend critically on timing parameters and knowledgeof incoming film thickness. Any problem upstream ofthe CMP process affects endpoint timing accuracy. Inpositive contrast, the PRECICE system manipulates itsangular spectrum reflectometry data to extract a signalfeature unique to STI polish endpoint. Thus, it supportsa CMP process independent of layer thickness variationfrom prior deposition steps.

References1. C.L. Mallory, W. Johnson, and K. Lehman, “Eddy current

test method and apparatus,” U.S. Patent No. 5,552,704,September 3, 1996.

2. R.C. McMaster, P. McIntire, and M.L. Mester eds. Non-destructive Testing Handbook: Electromagnetic Testing,2nd edn., American Society for Nondestructive Testing,1986.

3. J.D. Jackson. Classical Electrodynamics, 3rd edn., NewYork: Wiley, 1998.

4. R.M.A Azzam and N.M. Bashara. Ellipsometry and Po-larized Light, Amsterdam: North-Holland, 1992.

5. D. H. Ballard and C.M. Brown. Computer Vision, Engle-wood Cliffs, NJ: Prentice-Hall, 1982.

6. M. Basseville and I.V. Nikoforov. Detection of AbruptChanges: Theory and Application, Englewood Cliffs, NJ:Prentice-Hall, 1993.


KLA-Tencor Trade Show Calendar

January 30, 2002 YMS China, Shanghai, China

February 5-7 SEMICON Korea, Seoul, Korea

February 11-15 AVS, Santa Clara, California

March 3 Lithography Users Group Meeting, Santa Clara, California

March 5-6 SPIE/Microlithography, Santa Clara, California

March 26 SEMICON China, Shanghai, China

April 10-12 ACE/APC, Dresden, Germany

April 16-18 SEMICON Europa, Munich, Germany

April 17 YMS Europa, Munich, Germany

A version of this article was originally published in the 2001ISSM/IEEE proceedings International Symposium of SemiconductorManufacturing Conference, October 8-10, 2001, San Jose,California, USA.


and depreciation of the facility that are independent ofcapacity utilization. The traditional strategy for mini-mizing the relative contribution of fixed costs is toreduce manufacturing cycle time and operate near maximum capacity. In a supply-limited environment,this means filling the factory with the highest marginproducts.

Demand-limited environments may induce loading thefactory with low-margin products. Such cases reduceaverage gross margins and can generate actual lossesduring times of rapid price erosion. Table 1 shows April2001 estimates of yield-normalized cost per die, revenueper die, revenue per megabit, and revenue per wafer forseveral DRAM products. The 16-, 64-, and 128-megabitchips were nearly perfect commodities at one dollar per16 Mb. Gross margins were negligible for 180 nmdesign rules. Since April 2001, average selling priceshave sunk below the cost of manufacturing2.

IntroductionIn this work, we use a simplified microeco-nomic model for the profitability, or rate ofprofit, generated by the semiconductormanufacturing processi. Let

where R is the factory overhead rate, W isthe number of wafer starts, T is the timeinterval, Y is the metrology-limited yieldentitlement, y is the die yield expressed as afraction of the entitlement, d is the numberof dies per wafer, b is the bin yield expressedas the fraction of good dies in each perfor-mance bin, p is the average selling price perdie, C is the manufacturing cost per wafer, i is the product index, and j is the binindex. This business model represents thegross rate of profit attributable to a factory.It does not include variable costs associatedwith packaging, marketing, or sales of theproduct. Some of the basic strategies formaximizing gross profit are discussed below.

The first term represents the fixed costsassociated with capital investment, operation,

The Dollar Value of Accelerated Shrinks

Kevin Monahan, Adil Engineer, Georges Falessi, Matt Hankinson, Sung Jin Lee, Ady Levy, Mike Slessor, KLA-Tencor Corporation

Previously, we have developed a simple microeconomic model that directly links metrology, yield, and profitability. Themodel has been used to explain the effect of metrology on gross margins in 200 mm and 300 mm factories. The same modelcan be adapted to evaluate the relative economic impact of accelerated design-rule shrinks in demand-limited markets. Usingexamples relevant to the high-volume production of memory products, we demonstrate that metrology-driven shrinks are stillthe most cost-effective way to improve profitability. We also describe the means by which these shrinks can be achieved inhigh-volume factories.


P = −R + ∑ (Yi yi di bij pij −bij Ci )ij

Wi

T

Table 1 Cost and Revenue in Dollars Gross Margins

Date: 4/12/01 Cost($) Price($) $/16Mb $/Wfr 180 nm 150 nm16Mb SDRAM 1.00 1.02 1.02 2040 0.02 0.3364Mb SDRAM 2.00 2.15 1.08 2150 0.15 0.76128Mb SDRAM 4.00 4.35 1.09 2175 0.35 1.57128Mb DDR 5.00 7.90 1.98 3950 2.90 4.43128Mb RDRAM 6.00 10.00 2.50 5000 4.00 5.83256 Mb SDRAM 8.00 13.95 1.74 3488 5.95 8.39

Table 1.


Inspection of the table shows that DRAM profitabilitycan be recovered in at least three ways:

• Increased performance: 266 MHz double datarate (DDR) memory sells at a per-bit premium com-pared to 133 MHz (SDR) memory.

• Increased capacity: 256 Mb memory prices arefalling, but they currently sell at a per-bit premiumrelative to 128 Mb memory.

• Increased density: At constant yield, shrinksimprove margins by decreasing the cost per die (e.g.,30 percent for a 180 to 150 nm shrink).

Microeconomics of shrinksThe second term in the profitability equation above isthe rate of revenue, adjusted for manufacturing cost perwafer. For the sake of simplicity, we can ignore speedbins (b) and estimate a yield-normalized die cost (c)given by

Here, S is the shrink ratio (e.g., 150 nm/180 nm), D is the wafer diameter ratio (e.g., 300 mm/200 mm),and d0 is the initial density. Substituting into the profitability equation, the term to the right of the sumbecomes the product of salable die output and the variable margin for each product:

As shown above, the normalized die cost in the secondterm falls off sharply with larger wafer size, improvedyield, and smaller design rules. For the purposes ofthis work, a demand-limited market is defined as anearly constant revenue opportunity for a given prod-uct, so that excess production results in a reduction ofaverage selling price as shown in Figure 1.

• The benefit of increased wafer size is lower die cost,offset by excess production-driven price reductionsand the cost of 300 mm facilities and equipment.

• The benefit of a metrology-driven shrink is lower diecost, offset by the cost of the metrology, statisticalanalysis, control applications, and an advancedprocess control framework.

The investment required for metrology-driven die-costreduction is 1-2 orders of magnitude lower than thatrequired for 300 mm solutions, with the notable exception of existing pilot lines. Clearly, existing 200 mm factories must pursue aggressive die-costreduction or face closure. The most economicallydefensible strategies will leverage metrology-drivenshrinks initially, followed by ramp of 300 mm lines asthe market recovers.

Metrology-driven shrinksThe bulk of this paper is dedicated to the systems,tools, software, and methodology required for enablingmetrology-driven shrinks. In order to maintain yield,one full generation of design-rule shrink (0.7x) requiresa 30 percent reduction in CD and overlay variation, plusa large drop in the levels of macro and micro defects.For the purpose of this work, we shall focus on factory-wide systems that enable shrinks by improving CDcontrol in the lithography and etch areas. In the nearfuture, performance of such systems will not be mea-sured at the component level (e.g., metrology precision).Instead, performance will be measured at the systemslevel, with the metric being improvement in CD variation given a specified process capability. Since thesespecifications must be data-driven, rigorous factory-wide stochastic analyses will be required beforehand.Currently, such stochastic analyses are provided as aservice to support factory-wide sample planning andadvanced process control (APC).

Key steps in the implementation of a factory-wide gateCD Control System (CD-CS) are outlined below:


P = −R + ∑Wi di Yi yi −(pi −ci)i

1T

Ci ≅ 1 Ci S2

Yi yi di yi d0i D2 Yi[ [ ]]ci ≡

US

Dolla

rs

1614121086420

+185

+107

+32 +29

Spot Prices per 128 Mb

Jan Jul

128Mb DDR-266256Mb SDRAM128 Mb SDRM

Figure 1. In 2001, DRAM spot prices declined eight-fold in six months.

The ASP advantage for DDR SDRAM and 256 Mb SDRAM declined

from 185 and 107 percent to 32 and 29 percent, respectively.


• Utilize factory-wide, generalized, nested ANOVA toseparate systematic and random, plus spatial andtemporal, components of variation by site, field,wafer, lot, and cell. Determine the overall processcapability and CD control opportunity.

• Utilize factory-wide APC simulation to evaluatemodel-based, feed-forward and feedback control as ameans of reducing temporal CD variation in cell-to-cell, lot-to-lot, or wafer-to-wafer data. Determine thespecific APC opportunity.

• Implement the factory-wide APC framework, con-forming to SEMI E-93 standards (Catalyst). Facilitatecontrol system integration (Figure 2).

• Implement a pre-integrated CD Control System consisting of SEM or spectroscopic CD tools, dataand recipe server, data analysis modules, and basiccontrol applications. Optimize tool-specific controlapplications.

DRAM CD control opportunitiesDRAM shrinks are limited by the requirement for tightcontrol over the physical parameters that affect the physicsof the device. An approximate expression3 for saturationcurrent in an MOS transistor illustrates this problem:

Here, W is the gate width, L is effective gate length, µis the carrier mobility, D is the thickness of the gate

dielectric, ε is the permittivity of the gate dielectric,Vgs is the gate voltage, and Vth is the threshold voltageat which switching begins to occur. At small L, short-channel effects reduce Vth non-linearly, so that smallvariations in L have large effects on current. Matchingof L-effective is, therefore, critical to the operation ofdifferential circuits such as the sense amplifiers andcomparators used in memory devices. Moreover, theequation above is an approximation; leakage currentdoes not go to zero in the sub-threshold region. Atsmall L, variations in L can have large effects on leak-age from the DRAM storage nodes. Due to these andother parametric limitations, the DRAM roadmap for1 Gb production has fallen off the historical trend line,and further attempts to lower bit-cost are at risk4. As aresult, control of L-effective in DRAM is becomingmore important as design rules decrease and as perfor-mance requirements increase.

Advanced Analytical MethodsGate CD control for DRAM is quite different fromthat seen in logic factories. Lithography cells are notspecifically dedicated to gate layers. For the purpose ofcontrolling overlay, cells are typically dedicated to aseries of critical layers on a specific product. These usu-ally include the active, gate, contact, and first-metallayers. Each critical layer is aligned and exposed usingthe same stage and lens. Therefore, CD control in ahigh-volume DRAM factory entails controlling cell-to-cell variation over a large number of lithographic cells.In addition, the etch processes used in DRAM manu-facture may induce more field-to-field variation acrossthe wafer and more site-to-site variation across eachfield. Generalized ANOVA is required to identify the

Etcher

Etch Time

Etch Time

Stepper/Track

SEM or SCD

DICDDose

Target DICD

Catalyst APC

Catalyst APC

Catalyst APC FICD

SEM or SCD

Figure 2. An APC scheme incorporating feedback and feed-forward of post-development CDs, feedback of etch CDs, and feedback of etch-time to

adjust the CD target in the lithography cell.

Ids ≅ (W)•(µ )•(ε )•(Vgs - Vth)2

2 L D



sources of correctable systematic variations, as shown inTable 2 above:

Without generalized ANOVA, systematic and randomerrors are confounded (right-hand column). As a result,a semiconductor manufacturer could make the costlyand erroneous conclusion that he had achieved entitle-ment for his process toolset.

Advanced Process ControlThe essence of advanced process control (APC) is theautomated correction of systematic process error. Thestrategy of APC is to de-confound and correct as muchsystematic error as possible. Several tactics can beemployed to support this strategy, as shown in Figure 2.

• Feed back corrections for systematic error. In the caseof lithography, adjustments are typically made to

exposure dose. In the case of etching, adjustments aretypically made to etch-time.

• Feed forward corrections for random error. Afterresist patterns are developed, “random” CD errorsbecome systematic and may be corrected by adjustingparameters such as etch-time.

• Create a systematic manufacturing context. After apattern is etched, CD errors are not correctable; thereis no subsequent patterning step. If the CD errorsarise from chamber offsets, one could adjust the etch-time of individual chambers.

• Develop generic control applications. Ideally, more than80 percent of a generic APC script should be re-use-able anywhere in the factory. Otherwise, unique codewill be created for each application.

Factory-Wide FrameworkCD control systems for DRAM require multiple inte-grations of control applications, metrology tools, andprocess tools for both lithography and etch cells. Theimplementation of a standard factory-wide APC frame-work solves this problem. With a framework, the taskof integrating with the factory MES system is per-formed only once.

Table 2.

Catalyst APC Framework

MES/EquipmentManager

ControlExecutor

ControlJob

Interface

MetrologyProcess

ApplicationInterface

DocumentManager

ProcessControl

WorkbenchGUI

ControlHistory

OracleDB

OracleDB

OracleDB

ControlDatabase

CORBA HOP

Figure 3. Open factory-wide framework for advanced process control.

Variance Generalized ANOVA ANOVA(nm2) Sys Rdm Total

Cell 1.44 2.25 3.69 3.69 Wafer 0.08 0.49 0.57 0.42 Field 1.21 5.29 6.50 NEG Site 6.25 2.25 8.50 8.50



In addition to simplifying MES integration, the frame-work provides middleware for managing the complexinteractions among the control executor, control database,control history, control documents, GUI workbench, andapplication interfaces. The middleware enables rapidextension of APC into overlay, etch, films, and CMP. Itcan also support integrated metrology and control onprocess tools. Failure to use a framework can generaterecurring costs that persist for multiple product gener-ations and compromise availability (e.g., >0.9999).

Advanced Metrology ToolsThe L-effective of DRAM transistors is sensitive toboth gate CD and gate profile. To address the need forCD and profile optimization, control systems based onspectroscopic ellipsometry have been developed to supplement the traditional SEM-based metrology.Spectroscopic CD tools (SCD) can measure CD, sidewallangle, height, and film thickness, simultaneously.Although measurements are made in 50-micron dif-fraction gratings located in the scribe lanes, line andspace dimensions can be adjusted to mimic the prox-imity behavior of gate structures in either dense arraysor relatively isolated logic areas. Intra-field targets maybe used when the economic benefits are compelling.Some typical SCD metrology results are shown inFigure 4.

The multiple data types provided by SCD enable bothprocess and metrology fault detection. Without suchinformation, profile variations that change L-effectivecould go undetected, compromising performance of theAPC system and reducing die yield. The sub-nanome-ter matching and precision of SCD tools enables APCarchitectures for controlling critical dimensions below50nm. Significantly above these dimensions, the con-tribution of metrology error would be negligible.

CD Process Window MonitorsThe algorithms used for CD-APC often depend on factorssuch as stepper focus offsets and illumination settings,which are not explicitly called out in the equations. Forexample, a generic proportional control algorithm withEWMA filtering (λ) might be written as

where Zn is the updated process adjustment, Zn-1 is thelast process measurement, Xt is the process target, andm is the estimate of the local slope of X as a functionof Z. In the specific case of CD control, we could have

Dosen = Dosen-1 − [CDn-1 − CDt]λ

m(Focus)

Average 3σ= 0.44 nm

Average 3σ=1.1 nm Average 3σ=0.22˚

CD

Depth/Height0.5

0.4

0.3

0.2

0.1

0.0

5.9

4.9

3.0

2.0

1.0

0.0

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1 3 5 7 9 11 13 15 17 19 21 23

Sites

Sites

Sites

1 3 5 7 9 11 13 15 17 19 21 23

1 3 5 7 9 11 13 15 17 19 21 23

Sidewall Angle

3 Si

gma

(nm

)

Resist on poly gate6 weeks, 24 sites3σ for each site

Figure 4. The high precision and multiple data types of SCD enable both advanced process control and CD process window monitor applications

(CD-PWM).

Zn = Zn-1 − [Xn-1 − Xt]λm



The stability of the APC algorithm depends on theestimate of the local slope (m), which in turn dependson the focus offset of the lithography tool. Periodicmonitoring of the lithographic focus-exposure windowis essential to detect process drift that could compromisethe integrity of an APC system, particularly for thetight CD control requirements associated with 0.13 and0.10 micron design-rules.

ConclusionsWe have shown that, in most cases, metrology-drivenshrinks are the most economic and effective means forreducing die-cost in demand-limited DRAM markets.We have also identified five technologies that can becombined to achieve shrink-enabling levels of CD con-trol for sub-0.18 micron product generations:

• Generalized ANOVA methods for identification ofcorrectable, systematic CD error

• Advanced control applications for automated correctionof CD error in photo and etch cells

• A factory-wide open framework to support integrationand management of APC applications

• Advanced SCD and SEM systems that address CDand profile metrology requirements for APC

• An automated process window monitor to identifyexcursions that could compromise APC

In the near future, we predict that factories will not becompetitive without APC architectures that are based onfactory-wide integration of network-enabled hardware,software, and control methodology. Considering the highreturn on investment provided by factory-wide APCarchitectures, semiconductor manufacturers are advised tocontinue such investments through industry downturns.

This strategy will enhance the performance and extendthe life of both current and future process tools, con-tributing to efficient use of scarce capital resources.

Principal author biographyDr. Kevin Monahan is a Vice President of Technologyand Director of Parametric Solutions in the CustomerGroup of KLA-Tencor Corporation. His professionalinterests include patterning and parametric processcontrol architectures for high-volume manufacturing.

References1. K. Monahan, G. Falessi, and A. Chatterjee, “Accelerated

yield learning in aggressive lithography”, Proc. SPIE3998, p. 492 (2000), Invited Paper.

2. Source: www.dramexchange.com3. C. Meade and L. Conway. Introduction to VLSI Systems.

Menlo Park: Addison-Wesley, 1980, pp 1-5.4. K. Itoh. VLSI Memory Chip Design. New York: Springer-

Verlag, 2001, pp. 1-99.5. R. C. Elliott, R. K. Nurani, S.-J. Lee, L. Ortiz, M. Preil, J. G.

Shanthikumar, T. Riley, and G. Goodwin, “Sampling planoptimization for detection of lithography and etch CDprocess excursions”, Proc. SPIE 3998, pp. 527 (2000).

Klar

ity

ProD

ATA

Com

pute

d Be

st F

ocus

(µm

) 0.60

0.40

0.20

0.00

-0.20

-0.40

-0.60

-0.80-0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60

Programmed Exposure Tool Focus Offsets (µm)

Dosen = Dose

n-1—

m(Focus) [CD

n-1— CD

t]

λ

CD PWM Focus TrackingResidual 3s = 12 nm

Figure 5. PWM tracking of focus offsets on a 248 nm lithography

tool. The residual 3σ is 12 nm. PWM is a web-enabled, automated

system that can track common process windows and identify matched

stepper groups across entire high-volume factories.

A version of this article was originally published in the 2001ISSM/IEEE proceedings International Symposium of SemiconductorManufacturing Conference, October 8-10, 2001, San Jose,California, USA.



S E C T I O N S

Q The Rayleigh equation says depth offocus decreases with shorter wavelengths.I’ve also heard the opposite, that shorterwavelengths give more depth of focus.Which is correct?

A Both answers are correct, depending on thedetails of the specific question. The Rayleigh equationsays depth of focus (DOF) is directly proportional towavelength. This equation, however, is derived for avery specific case: when the feature being printed is atthe resolution limit of the imaging tool. Rayleigh’sresolution equation (the other Rayleigh equation)says the resolution limit is also directly proportionalto wavelength. Thus, when the wavelength isreduced, the Rayleigh DOF equation says the DOF ofthe smaller feature is less. This is not an astoundingconclusion – small features have less DOF.

Suppose the question were asked in a different way:for a given feature to be printed (say, 130 nm linesand spaces), how does wavelength affect DOF, allother things being equal? Is there a difference inDOF using 193 nm exposure tools versus 248 nm?The Rayleigh DOF equation by itself cannot answerthis question. In fact, the lower wavelength will alwaysgive more depth of focus for a given feature size.

Q I read a paper that talked about “forbidden pitches”. What is a forbiddenpitch and why can’t I use them?

A The term “forbidden pitch” is frequently usedwhen imaging with off-axis illumination, such asquadrupole or annular illumination. These illumi-nations bring light to the mask at an oblique angle.Diffraction of light from the patterns on the maskoccurs at angles that depend on the pitch of the patterns. Off-axis illumination is optimized so thatthe angle of illumination striking the mask matchesthe angle of diffraction for a given pitch to giveoptimum performance (usually be spacing the diffraction orders evenly about the center of thestepper lens). This angle of illumination is onlyoptimum at this one pitch. When the off-axis illumination is optimized for one pitch (usually thesmallest pitch on the mask), there will always besome other pitch where the angle of the illuminationworks with the angle of diffraction to produce a verybad distribution of diffraction orders in the lens (onediffraction order in the middle of the lens and theothers at the outer edges of the lens), resulting inpoor depth of focus for that pitch. We call this pitch“forbidden” because of its poor lithographic response,and because we hope the chip designers will listento us and avoid putting that pitch on the mask.

Got a Litho Question?Ask the Experts Chris A. Mack

Do you have a lithography question?

Just e-mail [email protected] and have your questions answered by ChrisMack or another of our experts.


Product NewsTeraStar SLF77 The TeraStar SLF77, the latest version of KLA-Tencor’s series of advancedreticle inspection systems, provides high-performance, high-sensitivity die-to-database inspection that meets critical layer requirements for 130 nmproduction and 100 nm research and development. Database renderingcapabilities include advanced database modeling, high-precision algorithms,and high-speed image-computing hardware. Reticle defect detection featuresinclude advanced Tera algorithms that enable high-sensitivity inspectionand low false-defect counts. Advanced image-computing capabilities allowinspection of small linewidths and optical proximity correction (OPC) features, including sub-resolution assist features.

TeraPro HP high productivity modeThe TeraPro HP High Productivity Mode, a feature of the TeraStar SLF77reticle inspection system, provides pattern, contamination and must-be-black(MBB) border inspections all in one inspection, saving time and increasingproductivity. This multi-faceted inspection using MBB inspects for yield-killing pinhole defects in the opaquing border, eliminating the need for anextra inspection. With TeraPro HP, multiple algorithms now run concur-rently in multiple areas. Concurrent inspection modes—STARlight anddie-to-die or STARlight and die-to-database—save time by reducing thenumber of inspection passes performed in the reticle flow.

Viper 2430The Viper 2430 is an automated macro-defect inspection system forinspecting 300 mm wafers using a multi-channel, multi-algorithm setupto capture yield-limiting defects at design rules of 0.13 µm and below.Built upon the extensive knowledge base developed in the field with cus-tomers who use the 2401 (the Viper 2430’s predecessor), this system isideal for process modules such as litho, CMP, and etch, or in passivationand final inspection. It also captures defects in advanced processes andmaterials such as copper dual damascene, low-κ dielectrics, and silicon-on-insulator (SOI). The Viper 2430 plays an important role in a fab’s overallstrategy to improve yield because it also monitors process excursions. Itcomplies with all I300I factory-automation standards for immediate andseamless integration into the 300 mm production environment. For rapiddispositioning of wafer lots and faster root-cause analysis, the Viper 2430features inline binning and flexible, on-board review capability that allowsusers to view individual defect images, wafer maps, wafer images, and galleries of wafer maps.


Surfscan SP1 backside inspection moduleAvailable as an option on both the Surfscan SP1TBI and Surfscan SP1DLS, the backside inspection module (BSIM) provides full edge handling andenables fabs to perform automatic, non-destructive inspection of both sidesof a wafer, including the backside of patterned production wafers. Manu-facturers can now control backside contamination and damage. They canalso monitor the effectiveness of backside cleans between process modules,and ultimately reduce yield loss due to particle-induced hot spots and otherdefects that result from backside contamination. The module also supports200 mm and 300 mm wafer manufacturing and advanced processes such ascopper, low-κ dielectrics, and design rules of 0.13 µm and smaller.

µLoop™µLoop (MicroLoop) is the industry’s first inline, non-contact electricaldefect monitoring solution designed to help chipmakers speed time to market and time to profit. The µLoop solution reduces the length of eachelectrical yield-learning cycle within the fab from as much as eight weeksdown to as little as a few days. This enables chip manufacturers to substan-tially accelerate the production ramp of new IC technologies while, at thesame time, increasing their baseline yields. µLoop’s speed and accuracy inisolating the location of electrical defects is made possible by utilizing acombination of seamlessly integrated capabilities, including: (a) patentedtest structures, which replicate customer-specific design rules and products;(b) latest-generation eS20XP scanning e-beam inspection and µLoopController systems, which use a voltage-contrast technique to identify andcharacterize electrical defects; (c) advanced electrical defect and yield-analysisalgorithms, which filter out non-yield relevant defects; and (d) industry-leading yield-acceleration expertise.

3rd Annual Lithography Users ForumAttend KLA-Tencor’s

w w w. k l a - t e n c o r. c o m / s p i e

Sunday, March 3rd, 2002 Techmart, Santa Clara, CA

R e g i s t e r a n d s u b m i t p o s t e r p a p e r s o n l i n e .RSVP by Fr iday, February 22nd, 2002.

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