© 2011 TSMC, Ltd

1

Will Reliability Limit Moore’s Law?

Tony Oates, TSMC

© 2011 TSMC, Ltd

2

Outline

Trends Interconnect Transistors Soft Errors in Memory and Logic Conclusions

© 2011 TSMC, Ltd

3

Market Growth

0

500

1,000

1,500

2,000

2,500

1980 1985 1990 1995 2000 2005 2010 2015

Elec

tron

ic E

quip

men

t Rev

enue

($B

)

1st Wave: Desktop PC

2nd Wave: Mobile Phone

3rd Wave: Mobile Computing

© 2011 TSMC, Ltd

4

?W, “2D”

~7B Logic transistors 20B vias, 20Km metal

System Integration and Scaling in 3D

200x to match brain 2nm node or +7 generations (>15years) Next 10 years: reasonably clear to ~5nm Many new innovations are possible beyond 10 years

Si-based 3D green CMOS + Si wafer-based 3D Chip Stacking Faster, smaller/thinner, lighter, lower power, and higher system

value = Si-Based System Scaling

~20W, “3D”

~100B Neural Cells (~1T Transistors)

Human Brain

vs.

Thousands of Cores 28nm HKMG

“3D + 3D” Si-Based Green System Scaling

3D CMOS (FinFET, ..)

TSV/3D-Stacking

vs.

© 2011 TSMC, Ltd

5

Moore’s Law: Innovation Based IC Scaling

Edelstein 2007

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6

Reliability Improvement Has Enabled IC Progress

But will reliability limit the pace of future progress?

Bohr, 2009

© 2011 TSMC, Ltd

7

Shrinking Reliability Margins Fa

ilure

Rat

e

EM, TDDB, BTI, HCI etc.. SER Defects

© 2011 TSMC, Ltd

8

Interconnect Requirements

• RC reduction

Interconnects dominate system delay

• Jmax Increase

8 12 16 20 24 28 32 36 40 440.0

0.5

1.0

1.5

2.0

2.5

ITRS 2010

Jmax

(MA/

cm2 ) @

110

C

Technology Node (nm)

© 2011 TSMC, Ltd

9

Porous Low-k Dielectrics

Pores reduce breakdown path length

Cu

Cap

SiOC

1 2 3 4 5 6 7

K=2.0(P~40%)

K=2.5(P~25%)

K=2.9(Porosity~15%)

T=125C

TDDB

Life

time

E-Field (MV/cm)

Rapid reduction of reliability with increasing porosity

© 2011 TSMC, Ltd

10

Porous Low-k Reliability Scaling

10

Lee IRPS 2011

k reduction is limited by reliability

Independent of voltage acceleration model

0 10 20 30 40 50 60

K=3.9

E= 4 MV/cm, T=125C

Model

2.02.32.52.82.9

Media

n Tim

e to F

ail (t 63

%)

Porosity (%)

Percolation Theory

© 2011 TSMC, Ltd

11

Solutions for Low-k Scaling

0 10 20 30 40 50 60 70

Model of control porcess increase to by ~10X increase BD path length by ~30% SiO2 Air Gap data Porous SiOC Air Gap data

K=3.9

E= 4 MV/cm,T=125C

Model EeaLtt γβ −

−

=1

00 )(

2.02.32.52.83.0M

edia

n Ti

me

to F

ail (

t 63%)

Porosity (%)

Air Gap / non-porous materials

© 2011 TSMC, Ltd

12

Low-k TDDB – Variability Interaction

0.1%

1%

10%

99%

63%

Failure Time

LER, Via Overlay

LER and via overlay sources of variability are aggravated by scaling

© 2011 TSMC, Ltd

13

LER Variability: Minimal Impact at Use Voltage

0.85 0.90 0.95 1.00 1.05 1.10 1.15

LER σ = 3%s0, β=3, N=10000, E=0.5 MV/cm

t = t0N(s)-1/βe-γV/s

Failu

re T

ime

Normalized dielectric thickness

0.85 0.90 0.95 1.00 1.05 1.10 1.15

LER σ = 3%s0, β=3, N=10000, E = 6 MV/cm

t = t0N(s)-1/βf(V/s)

f(V/S)= E-model f(V/S)= Sqrt(E) model f(V/S)= 1/E model

Failu

re T

ime

Normalized dielectric thickness

sfail = snom

sfai l= smin

Accelerated Test

Circuit Use β=2.68β=1.06β=0.68β=0.49E=0.6 (MV/cm)E=3E=5E=7

0.1%

1%

10%

99%

63%

Time

LER s = 10% s0

© 2011 TSMC, Ltd

14

0

2

4

6

8

10 Trench mode

Slit mode

T5

0 (a

.u.)

Technology node (nm)

Scaling of Cu Electromigration

Critical geometry, fast transport limit reliability

2KwAV

tds

cf

i

i

i≈=

ν

© 2011 TSMC, Ltd

15

A Paradigm Change

8 12 16 20 24 28 32 36 40 440.00.51.01.52.02.53.03.54.04.55.05.56.0

Short length benefit, L<5µm

ITRS 2010 new

Jmax

(MA/

cm2 ) @

110

C

Technology Node (nm)

EM design rules are now driven by short lengths

Cu

Jem Js

ρσ

*)(eZ

jl cΩ∆

=

Blech Effect

© 2011 TSMC, Ltd

16

Short – Length Electromigration Scaling

0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.180

2

4

6

8

10

12

t 0.1%

(L) /

t 0.1%

(L=2

50µm

)

tb/w

L=5 µm L=10 µm L=250 µm

10nm 16nm 20nm 28nm

Short-length reliability reduces fastest! (barrier thickness reduction)

© 2011 TSMC, Ltd

17

Short and Long Length Failure Times are NOT Independent

)( ciis

ivv

ds

cf jjA

wdKLAV

ti

ii

i

i

i −≈=

ν

So…solutions are independent of length

© 2011 TSMC, Ltd

18

Electromigration Process Solutions for Continued Jmax Increase

Liner

Cap

Cu/cap interface

bulk Grain Boundary

Reduction of grain boundary transport is key

Metal Caps – interface Cu Alloys – g.b.

© 2011 TSMC, Ltd

19

1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.71E-201E-191E-181E-171E-161E-151E-141E-131E-121E-11

N10 Pure Cu N10 CuAl doping N10 CuMn doping N10 Co-cap+Co barrier

110

N10 target N7 target N5 target

350Temperature (oC)

300275 250 225 200 175 150 125

V dT/ j

(Kcm

3 /A s

ec)

1000/T (K-1)

Viability of Cu Process Solutions

Cu Drift Velocity

Cu alloys: limited options for 10 nm and below

10 nm 7 nm 5 nm

CuAl Cu

CuMn

CuCo Goal

© 2011 TSMC, Ltd

20

Process Variability Impact on Electromigration Failure Times

Volume=Vc

Area=As Lv

dv

j )( ciis

ivv

ds

cf jjA

wdKLAV

ti

ii

i

i

i −≈=

ν

Vc, As, jci are statistically distributed random variables

© 2011 TSMC, Ltd

21

Impact of Process Variability: Failure when j < jc

0 1000 2000 3000

108

112

116

120

124

R (o

hm)

Time(a.u.)

∆R~15Ω j=0.7jc

0 100 200 300 400 500 600 700 800 900 100015400

15600

15800

16000

16200

16400

L=50 µm, j=0.5 jc

R (o

hm)

Time(a.u.)

Short length immortality cannot be applied to circuits

Multi-link N=50

L=10 µm

© 2011 TSMC, Ltd

22

Impact of Process Variation: New Extrapolation Procedures

Lognormal fitting does not work

Lognormal fit jc=3.4

© 2011 TSMC, Ltd

23

Transistor Structure and Materials Trends

HKMG Planar

FinFET

10nm 2015

16/14nm 2013

20nm 2012

7nm 2017

100X

Mobility (performance)

Moore’s Law

10X

1X

3D transistors and new materials on Si substrate

5nm 2019

III-V on Si CMOS

N16 FinFET

(TSMC, VLSI’04)

Nanowire FET

© 2011 TSMC, Ltd

24

Scaling of HK/MG Transistor Degradation Mechanisms

Linder, DAC, 2013

SiO2/HfO2

© 2011 TSMC, Ltd

25

Technology Scaling Impact on NBTI

2.5 3.0 3.5 4.0 4.5 5.0

EOT1 > EOT2 > EOT3 > EOT4 > EOT5 > EOT6 > EOT7 > EOT8 > EOT9

NBTI

Life

time

due

to ∆

Vit (

a.u.

)

Electric Field (MV/cm)

NBTI R-D Model EOT1 EOT4 EOT7 EOT2 EOT5 EOT8 EOT3 EOT6 EOT9

Interface State Generation

( ) ( ) 61

ox32

C t3E 2γexpEEOTAΔVt ⋅

⋅⋅⋅=

No additional impact of HK/MG and FinFET transitions

Franco, IEDM, 2010

ITRS

© 2011 TSMC, Ltd

26

SiGe Channel: NBTI Scaling Solution

0

0.2

0.4

0.6

0.8

1

6 8 10 12 14 16 18 20 22

Max

. |V G

-Vth

| for

10Y

[V]

Tinv (≈EOT+4Å) [Å]

Ultra-Thin EOT

T=125ºC

MIPS RMG

SiGe

Franco et al, TED, 2013

Si VB

(Si)GeCB

SiO2

HfO2

© 2011 TSMC, Ltd

27

New Channel Materials Ge PMOS NBTI (SiO2 / HfO2)

PBTI becomes the dominant degradation mechanism?

Franco, TED, TDMR 2013

InAs NMOS PBTI

Deora, TDMR 2013

0

0.4

0.8

1.2

1.6

6 10 14 18 22 26 30

Max

imum

|VG-V

th| [

V]

Tinv [Å]

Si baselineSiGe 55%, Tinv1SiGe 55%,Tinv2SiGe 45%, Tinv3SiGe finFETr-Ge (planar)s-Ge (planar & finFET)ITRS Target

T=125C

Si

(Si)Ge

But gate stack quality is critical

© 2011 TSMC, Ltd

28

New Gate Stack Materials: SiO2 IL Replacement by High-k IL

Gate Dielectric TDDB

Al2O3/HfO2

SiO2/HfO2

ITRS

Sahoo and Oates, TDMR 2013

© 2011 TSMC, Ltd

29

Circuit Impact of BTI: SRAM

PMOS (WM)

NMOS (WM)

NMOS (RM)

PMOS (RM)

(+)0(-)

(+)

0

Vcc,

min

Shi

ft

∆Vt

• Cell design is critical to minimize RM increase

0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 0.62(-)

(+)

0

RM+WM Mixed

WM Dominated

RMDominated

Vcc,

min

Drif

t Med

ium

Val

ues

(mV)

Alpha RatioLin IRPS 2007

HK/MG

RM = Read margin WM = Write margin

PGon

PUon

II

ratio,

,=α

© 2011 TSMC, Ltd

30

Circuit Impact of NBTI: Digital Logic

0.8 0.9 1.0 1.1 1.20.1

15

204060809599

99.9Data (symbols)T1000 ~ Nil aging

Simulation (lines)T1000 ~ Nil agingT10yrs ~ 1.65%

T0 (HTOL-Data) T1000 (HTOL-Data)T0 (HTOL-sim) T1000 (HTOL-sim)T10yrs (0.9V 100C-sim)

Prob

abili

ty %

Norm. Freq (a.u.)

ARM11, 40nm

• Process variation can obscure aging

Vaidyanathan IRPS 2011

Vdd=1.4V, 125 oC, 1000 hours

© 2011 TSMC, Ltd

31

BTI is a Time-Dependent Variability Source

σ(∆V

t) (m

V)

1/(AGOX)0.5 (um-1)

GOXAVthEOTKVth )()( ∆∗∗

=∆µ

σ

Scaling

© 2011 TSMC, Ltd

32

BTI Aging and Process Variation: New Definitions of Reliability

fall-outpoint definedby 3σ or 99.9%probability ofoccurence

w/o NBTI w/ NBTI

Prob

abili

ty d

ensi

ty

Circuit/Device parameter

Reliability can be defined in terms of “fall-out” from a process variability window

© 2011 TSMC, Ltd

33

Variability and Degradation of Circuits

Reliability “fall-out” improves with scaling

1 10Pr

oces

s va

riatio

nIn

duce

d 3σ

Id (a

.u.)

NBTI

∆Id

, ∆Fr

eq (%

)@

10yr

s, V

dd, 1

25C

Tech. node (a.u.) 1 10

NBTI

Indu

ced

dela

y fa

ll-ou

t @

10yr

s (%

)

Tech. node (a.u.)

Ring Osc. Fall-out Variability and NBTI Scaling

Transistor, DC Transistor, AC Ring Oscillator

Process Variation

© 2011 TSMC, Ltd

34

SER Scaling Trends

100

1000

10000

130nm 90nm 65nm 40nm 28nm

Technology

SER

per

Meg

a-D

evic

es SRAM FF

Component trends are favorable - but system trends are not

0.00001

0.0001

0.001

0.01

0.1

1

0.1 1 10 100MCU Cluster Size (um)

MC

U P

roba

bilit

y

65nm wi DNW45nm wiDNW40nm wiDNW 45nm woDNW 28m wo DNW

SRAM Multi-bit

DNW=Deep N Well

Alpha and Fast Neutrons

© 2011 TSMC, Ltd

35

Challenges: SER of Combinational Logic

Above ~1 GHz, logic errors can dominate system SER

FF

R-OSC

Comparator

TSMC 40 nm Fast Neutrons

© 2011 TSMC, Ltd

36

Virtual SER Qualification

Accurate ASIC cell and circuit EDA tools available

100

150

200

250

300

350

FF A FF B FF C FF D FF E

Neu

tron

SER

per

MFF

s N40G Exp.TFIT Simulation

IROC TFIT: 40 nm Flip-Flops p

0.0%

0.1%

1.0%

10.0%

100.0%

1 2 3 4 5 6 7+Cell#

Prob

abili

ty

Exp.Sim.

(b) p

0.0%

0.1%

1.0%

10.0%

100.0%

1 2 3 4 5 6 7+Cell#

Prob

abili

ty

Exp.Sim.

(b)IROC TFIT: SRAM Multi-bits

Assess logic circuit reliability

© 2011 TSMC, Ltd

37

Challenge: Thermal Neutrons B10 incorporation in BEOL of advanced nodes

Negligible < 28 nm

1

10

100

65nm 40nm 28nm 20nm

SER

per

Cel

l (A

.U.)

( )

Symbols: exp. dataLines: model

Thermal neutron

Alpha

SRAM

1

10

100

65nm 40nm 28nm 20nm

SER

per

Cel

l (A

.U.)

( )

Symbols: exp. dataLines: model

Thermal neutron

Alpha

SRAM

Fang, TDMR 2013

© 2011 TSMC, Ltd

38

Challenges: Muon SER – A New Issue

Muons are the most abundant high energy cosmic ray particle

Sierawski IRPS 2011

Ibe, IOLTS 2012

© 2011 TSMC, Ltd

39

-0.2

0

0.2

0.4

0.6

0.8

1

100 300 500 700 900

Time(s)D

rain

Vol

tage

(V) LET=5

LET=10LET=20LET=40

Some Good News: FinFET SER

0

0.2

0.4

0.6

0.8

1

100 300 500 700 900Time(ps)

Drai

n Vo

ltage

(V)

LET=10LET=20LET=40LET=60

Unit: MeV-cm2/mg

Space environment only

D S

Ion track Bulk substrate

G

STI

Horizontal Strike

D S

Bulk substrate

G

STI

Vertical Strike

FinFET shows reduced charge collection in the terrestrial environment

© 2011 TSMC, Ltd

40

FinFET SER

Fast neutrons dominate

Charge Collection Simulations

6T-SRAM SER Trend

0.1

1

10

100

1000

40G 28HP 20SOC 16FF

FIT/

Mbi

t

AlphaNeutron

© 2011 TSMC, Ltd

41

SER with III-V Channels

SRAM FF

Increased SER (Vdd > 0.5V)

Liu, TDMR 2013

Simulations

© 2011 TSMC, Ltd

42

Conclusions

Reliability progress/containment has enabled Moore’s law to continue to work its magic

But clearly, technology scaling is accompanied by a shrinking of reliability margins

The reliability challenges to be overcome cover the entire spectrum of known issues

Holistic approaches will ensure that reliability does not limit the pace of technology progression