What are interrupts and why are they needed in an embedded ...people.ucalgary.ca/~smithmr/2017webs/encm511_17/Lectures/17_Lectures/... · A look at interrupts What are interrupts

A look at interrupts

What are interrupts and why are they needed in an embedded system?

Equally as important – how are these ideas handled on the Blackfin

Dispatch_Tasks ( )

SHOWS WHERE INTERRUPTS FIT IN

Assignment 2 Assignment 1 Coffeepot on interrupts

Current Code

Init_Coffeepot( )

While (device_not ready) {UpdateSimulator – software update

check if device is ready;// And you always know when that// will happen at a certain place in// you code so the simulation// unlikely to find real life timing errors

}

New code

Init_Coffeepot( );Stop_CoreTimer_Interrupt( );SetUp_CoreTimer_Interrupts( hardware update);Start_CoreTimer_Interrupt( );

While (device_not ready) {// Hidden background interrupt service routine// The ISR more realistically makes the coffeepot// update out of synchronism with your software// More like real like

check if ready;}

The “standard” instruction cycleof a microprocessor (ENCM369)RESETTHE PROCESSOR

RESET*INTERRUPT(ACTIVE low)

CAUSESRESET INTERRUPT

INSTR PHASE 1FETCH AN INSTRUCTION FROM PROGRAM MEMORY

INSTR PHASE 2 DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY

INSTR PHASE 3 EXECUTE THE INSTRUCTION

INSTR PHASE 4 WRITE BACK THE RESULT

PROCESSOR

RESET*+3 / 5V

RC time constant200 ms on

68K

+3 / 5V

GROUND





The “standard” instruction cycleRESETTHE PROCESSOR

RESET*(ACTIVE low)

EXECUTING‘YOUR PROGRAM’

UNTIL POWER IS REMOVED

The “standard” instruction cyclewith external device having important data

RESETTHE PROCESSOR

RESET*(ACTIVE low)

EXTERNAL HARDWARE

Control signal – I have data for you

16-bits This is the data

Control signal – ThanksProcessor has received data

Checkif

ready





The “standard” instruction cyclewith external device having important data

RESETTHE PROCESSOR

RESET*(ACTIVE low)

FETCHDECODE

EXECUTE

WRITE-BACK

EXTERNAL HARDWARE

Control signal – I have data for you

16-bits This is the data

Control signal – ThanksProcessor has received data

Checkif device

ready

The “wait till ready” approach of reading data from external device

In decode phase – read control register valueIn execute phase – check if 1-- keep waiting (fetch-decode-execute-writeback instruction cycle) until

the control value changes from 0 (device not ready) to 1 (device ready)

When 1 – go to a different part of your program code to read the datae.g. call ReadData( )

Then your program must send an acknowledge back to device that the data has been read. e.g. call AcknowledgeReadData( ).

The device can then go and get more values for you.

PROBLEM: You have no time to do anything else other than waitNot a problem if waiting for this device is the only thing you want to do

with the processor

Wait till ready approachVery problematic if many devices

RESETTHE PROCESSOR

RESET*(ACTIVE low)

EXTERNAL HARDWARE

16-bits

EXTERNAL HARDWARE

16-bits

EXTERNAL HARDWARE

16-

Checkif

ready

Checkif

ready

Checkif

ready

Checkif

ready

WAITS TOO LONG





The “Poll approach” of getting dataNot much waiting – but a lot of “doing”

read control register value of device 1-- if 1

go to a different part of the code to “read the data” (ReadData1( ) ) – after reading the data send an acknowledge signal back to device 1 (AcknowledgeReadData1( ) )

-- if 0go and read the control value of device 2 – don’t worry about device 1 for some time

read control register value of device 2-- if 1

go to a different part of the code to “read the data” (ReadData2() ) – after reading the data send an acknowledge signal back to device 2 (AcknowledgeReadData2( ) )

-- if 0go and read the control value of device 3 – don’t worry about device 2 and 3 for

some time

ETC

PROBLEM: What happens if, while you are handling device 2, device 1 has “time sensitive information” that will disappear if device 1 is not serviced immediately

Interrupt Approach – basic ideaExtra “phase” in instruction cycle

RESETTHE PROCESSOR

RESET*(ACTIVE low)

PHASE 1FETCH AN INSTRUCTION FROM “NORMAL” (NOT ISR)PROGRAM MEMORY

PHASE 2DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY

PHASE 3EXECUTE THE INSTRUCTION

PHASE 4WRITE BACK THE ANSWER

EXTERNAL HARDWARE

16-bits data

PHASE ANY-TIME

CHECK IF ANINTERRUPT

REQUEST HAS OCCURRED

CONTROL SIGNALDATA READY SIGNAL

BECOMES INTERRUPTREQUEST

NO

yesDOISR

CONTINUEAS BEFORE

Acknowledge Request done

These issues MUST be solvedif using interrupts on ANY real uP1. What if device hardware can only provide

a “quick” I am ready signal?2. What if more than one hardware device

wants to send an interrupt request?3. What if the programmer wants to “ignore”

“low priority” interrupt requests?4. What if certain interrupt requests are too

important to ignore?

What if hardware device can only provide a “quick” I am ready signal?

Add interrupt (capture) latch to processor

EXTERNAL HARDWARE

16-bits

CHECK IF ANINTERRUPT REQUEST HAS OCCURRED

CONTROL SIGNALFAST CHANGING

DATA READY SIGNALSignal send (1) and

then becomes 0

yes

DOISR

CONTINUEAS BEFORE

Acknowledge done

Interrupt Buffer

Interrupt Latch (Capture Request)Processor

clock signal causes loadof the latch to capturethe transient interrupt

What if the programmer wants to “ignore” a “low priority” interrupt?

Add (Ignore) Interrupt Mask

EXTERNAL HARDWARE

16-bits



BECOMES INTERRUPTREQUEST LINE

yes

DOISR

CONTINUEAS BEFORE

Acknowledge done

Interrupt Buffer

Interrupt MaskIgnoreProcessor


Interrupt Latch (Capture)

e.g. IGNORE INTERRUPIF FIO_MASK_ABIT is 0 (Lab. 1)

What if certain hardware interrupts are too important to ignore?

NMI bypass the IGNORE Interrupt MaskNon-Maskable Interrupts

EXTERNAL HARDWARE

16-bits




yes

DOISR

CONTINUEAS BEFORE

Acknowledge done

Interrupt Buffer




NMI

What if more than one hardware wants to send an interrupt?

EXTERNAL HARDWARE

16-bits




yes

DOISR

CONTINUEAS BEFORE

Acknowledge done

Interrupt Buffer




Pending interrupts(still to be done

NMI

Blackfin MASKS and LatchesSame hardware in concept as previous slides

Unpredictableand planned

interrupts

Using“idle”

low power mode in

Lab. 0 and 2uTTCOS

Have discussed

Normal,Hardware Loop,

Jump,Conditional Jump

Call,RTS

Program flow before

Normal “linear flow” causesPC to increment to be able to fetch next next instruction

Processor uses program counter PC

as an Instruction Pointer register

Fetch instruction at memory locationPC then increment the PC to point atthe next instruction PC = PC+2or for bigger instr PC = PC + 4;

Subroutine call flow – PC increments, but is then stored (link register) and PC forced to Jump

to new instruction at start of subroutine function

PC = PC + 2

CALL INSTRUCTION DOESRETS = PC + 4 (FFA03C78)

PC set to 0xFFA01E24So instruction 0xFFA01E24 done next

This instruction is NOT fetched (until end of subroutine)

This instruction is now fetchedHAVE JUMPED TO SUBROUTINE

Interrupt different -- Occurs ANYTIME, ANYWHEREMust Jump to ISR NOW, not later!

How can the uP do this? – What must happen to PC?

Use program counter PC

as an Instruction Pointer register

Fetch instruction at memory locationPC then increment the PC to point atthe next instruction PC = PC+2

PC = PC + 4;

Hardware Interrupt could occur anytime,anywhere in C++ or ASM or library code

(or while uP sitting at a breakpointbeing debugged (Lab 0, 2, 3, 4) )

Interrupt occurs HERE (green arrow)Must Jump to ISR NOW – but how?

First step is obvious

PC has 0xFFA01E44 in it – uP just about to fetch P0.L = instruction

Remember what instruction you were about to execute – so uP can do that instruction after finishing the ISR

RETI is “register used to remember the instruction “stopped” by interrupt

RETI = PC (0xFFA01E44)PC must get set to what ?????

value to make interrupt service routine run for this interrupt?

How make this happen?

Interrupt occurs HEREMust Jump to ISR – but how

First step is obviousRemember what instruction

you were about to execute

RETI = PC (0xFFA01E44)PC = ?????

Some how – like magic we must have the uP set

PC = start of Timer ISR0xFFA01EC0then processor will start executing TimerISR code

Solution – Blackfin has Lookup table of what value to put into PC for each interrupt than can occur

Look-up table for the start of every interrupt routine is stored in EVR table Event vector register table (see BF533 reference sheet)

“To Vector” is a verb – Meaning to lead or direct to

Obvious Post-Lab Quiz 3 question to set EVR

Event (e.g interrupts)

TableEVT6 – Entry for

CORE-TIMER interrupt

Why do all these “event addresses” in the EVR (ISR jump) table start the same?

This is the address of the “the processor does not know what to do if there is an interrupt of this sort” EXCEPTION

• IDLEThis is the

assembly code

While(wait till some

happens) instruction

VDSP / CCES Emulator puts in a “breakpoint” so for us, as developers, the program stops.

In real life – processor can’t “stop”, just goes into an infiniteloop until “watchdog timer” resets the processor

The “don’t know what to do” “exception” service routine (ESR)

“Don’t know what to do”Exception

• This exception hangs the processor– Keeps doing same instruction (doing nothing)

which is safer than doing something– The developer should have provided a better

ESR if had known what to do

• Problem solved by using “WATCHDOG TIMER”

Solution – Lookup tableof what value to put into PC for

each type of interrupt that occurs

• Question – the start of the ISR is in the event table – How did it get there?

Event (e.g interrupts)

Table

The start address of the ISR got into the event table HOW?

• Tell (register) the processor how to handle each interrupt service routine

Also we can understand what the raise( ) C++ function does – This is a special C++ instruction to allow us to test ISR

SetUp_EVT

Blackfin MASKS and Latches

Raise( ) use “software to put a 1 into the interrupt latch register – making the processorthink that a hardware interrupt has happened

Event table information can be found in the Blackfin Hardware Manualand Blackfin Reference Sheet

What happens if the device does take away its “I’m ready” signal

during an interrupt?

EXTERNAL HARDWARE

16-bits



yes

DOISR

CONTINUEAS BEFORE

Acknowledge done

Interrupt Buffer

Interrupt Latch (Capture)Processor


These registers control other interrupt capability

IMASK – the interrupt control registerfor the whole processor SIC- IMASK – the interrupt control register

for the processor peripherals

IMASK over-rides SIC_IMASK

These figures are useful for other interrupt activity

Shows how the entries in the SIC_IMASKare normally mapped (multiplexed)

to entries in IMASK

Can be changed if you need to

Details of the

Core Event Table used byIMASK controller when

responding to ISR request

Tackled today• Three ways of handling hardware requests for

service

• Wait till the device signals “ready”then process the data

• If device 1 ready – process its data• Else If device 2 ready – process its data POLL

• Interrupt – start processing the data from a “specific device NOW!

Documents

What are interrupts and why are they needed in an embedded ...people.ucalgary.ca/~smithmr/2017webs/encm511_17/Lectures/17_Lectures/... · A look at interrupts What are interrupts