UNIT 4

Architecture of 8051

Figure 1.4 shows the architectural block diagram of 8051. It has following functional units and registers.

ALU — Arithmetic Logical Unit

This unit is used for the arithmetic calculations.

A-Accumulator

This register is used for arithmetic operations. This is also bit addressable and 8 bit register.

B-Register

This register is used in only two instructions MUL AB and DIV AB. This is also bit addressable and 8 bit register.

PC-Program Counter

Points to the address of next instruction to be executed from ROM It is 16 bit register means the 8051 can access program address from 0000H to FFFFH. A

total of 64KB of code. 16 bit register means.

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0000H)

Final value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (F F F FH)

Initially PC has 0000H ORG instruction is used to initialize the PC ORG 0000H means PC initialize by 0000H PC is incremented after each instruction.

ROM Memory Map in 8051

4KB on chip ROM is available in 8051. Max ROM we can interface externally is 64 KB because 16 bit address line is available in

8051. Starting address for ROM is 0000H (because PC which points the ROM is 16 bit wide).

8051 Flag Bits and PSW Register

Used to indicate the Arithmetic condition of Accumulator. Flag register in 8051 is called as program status word (PSW). This special function

register PSW is also bit addressable and 8 bit wide means each bit can be set or reset independently.

There are four flags in 8051

P → Parity flag → PSW 0.0

0 – odd number of 1 in ACC

1– even number of 1 in ACC

OV (PSW 0.2) → overflow flag → this is used to detect error in signed arithmetic operation. This is similar to carry flag but difference is only that carry flag is used for unsigned operation.

for selecting Bank 1, we use following commands

SETB PSW0.3 (means RS0=1)

CLR PSW0.4 (means RS1=0)

Initially by default always Bank 0 is selected.

F0 → user definable bit AC → Auxiliary carry flag → when carry is generated from D3 to D4, it is set to 1, it is used in BCD arithmetic.

Since carry is generated from D3 to D4, so AC is set.

CY → carry flag → Affected after 8 bit addition and subtraction. It is used to detect error in unsigned arithmetic opr. We can also use it as single bit storage.

SETB C → for cy = 1

CLR C → for cy = 0

Structure of RAM or 8051 Register Bank and Stack

128 byte RAM is available in 8051

Address range of RAM is 00H to 7FH.

In MC8051, 128 byte visible or user accessible RAM is available which is shown in figure. Extra 128B RAM which is not user accessible. 80H to FFH used for storage of SFR (special function register)

Four Register Banks

There are four register banks, in each register bank there are eight 8 bit register available from R0 to R7

By default Bank 0 is selected.

For Bank 0, R0 has address 00H.

R1 has address 01H

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R7 has address 07H

For Bank 1, R0 has address 08H

R1 has address 09H

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. . . . . . . . . . . . . . . .

R7 has address 0FH

For selecting banks we use RS0 and RS1 bit of PSW.

R0 to R7 registers are byte addressable means.

If we want to set the bit 3 of R0 then we can’t use SETB R0.3

We use MOV R0, #08H;

For changing single bit we can modify all the other bits of R0.

Locations 20H to 2FH is bit addressable RAM means each bit from 00H to FFH in this we can set or reset CF rather than changing whole byte.

Locations 30H to 7FH is used as scratch pad means we can use this space for data reading and writing or for data storage.

Stack in 8051

RAM locations from 08H to 1FH can be used as stack. Stack is used to store the data temporarily.

Stack is last in first out (LIFO) Stack pointer (SP) →

• 8bit register• It indicates current RAM address available for stack or it points the top of stack.• Initially by default at 07H because first location of stack is 08H.• After each PUSH instruction the SP is incremented by one while in MC after PUSH

instruction SP is decremented.• After each POP instruction the SP is decremented.

If we want to use more than 24byte (08H to 1FH) of stack. We can change SP to point RAM address 30H to 7FH by MOV SP, #XX

Any value from 30 to 7FH

DPTR → Data Pointer in 8051

16 bit register; it is divided into two parts DPH and DPL. DPH for Higher order 8 bits, DPL for lower order 8 bits. DPTR, DPH, DPL these all are SFRs in 8051.

Special Function Register

RAM scratch pad, there is extra 128 byte RAM which is used to store the SFRs.

Byte Addressable SFR with byte address

SP – Stack printer – 81H

DPTR – Data pointer 2 bytes

DPL – Low byte – 82H

DPH – High byte – 83H

TMOD – Timer mode control – 89H

TH0 – Timer 0 Higher order bytes – 8CH

TL0 – Timer 0 Low order bytes – 8AH

TH1 – Timer 1 High bytes = 80H

TL1 – Timer 1 Low order byte = 86H

SBUF – Serial data buffer = 99H

PCON – Power control – 87H.

Instruction set of 8051

The 8051 instructions are divided among five functional groups:1. Arithmetic2. Logical3. Data transfer4. Boolean variable5. Program branching

1. Arithmetic Instructions:

ADD A, source ; A = A + source The instruction ADD is used to add two operands Destination operand is always in register A Source operand can be a register,

immediate data, or in memory

Ex: MOV A,#0F5H ADD A, #0BH

DA A ; decimal adjust for addition

The DA instruction is provided to correct the afore mentioned problem associated with BCD addition

The DA instruction will add 6 to the lower nibble or higher nibble if need

Ex:

MOV A,#47H ; A=47H first BCD operand MOV B,#25H ; B=25H second BCD operand ADD A,B ; hex(binary) addition(A=6CH) DA A ; adjust for BCD addition (A=72H) After an ADD or ADDC instruction

If the lower nibble (4 bits) is greater than 9, or if AC=1, add 0110 to the lower 4 bits

If the upper nibble is greater than 9, or if CY=1, add 0110 to the upper 4 bits

SUBB A,source ; A = A – source – CY

To make SUB out of SUBB, we have to make CY=0 prior to the execution of the instruction

Notice that we use the CY flag for the borrow

MUL AB ; AxB, 16-bit result in B, A

The 8051 supports byte by byte multiplication only The byte are assumed to be unsigned data

Ex:

MOV A,#25H ; load 25H to reg. A MOV B,#65H ; load 65H to reg. B MUL AB ; 25H * 65H = E99 where; B = OEH and A = 99H

DIV AB; divide A by B, A/B

The 8051 supports byte over byte division only The byte are assumed to be unsigned data

Ex:

MOV A,#95 ; load 95 to reg. A MOV B,#10 ; load 10 to reg. B MUL AB ; A = 09(quotient) and; B = 05(remainder)

2. Logical Instructions:

ANL destination, source ;dest = dest AND source

This instruction will perform a logic AND on the two operands and place the result in the destination

The destination is normally the accumulator The source operand can be a register, in memory, or immediate

Ex: MOV A,#35H ; A = 35H ANL A,#0FH ; A = A AND 0FH

ORL destination,source ;dest = dest OR source

The destination and source operands are ORed and the result is placed in the destination

The destination is normally the accumulator The source operand can be a register, in memory, or immediate

Ex: MOV A,#04H ; A = 04 ORL A,#68H ; A = 6C

XRL destination,source ;dest = dest XOR source

This instruction will perform XOR operation on the two operands and place the result in the destination

The destination is normally the accumulator The source operand can be a register, in memory, or immediate

Ex:

MOV A,#54H XRL A,#78H

CPL A ; complements the register A

This is called 1’s complement To get the 2’s complement, all we have to do is to to add 1 to the 1’s

complementEx:

MOV A, #55H CPL A; now A=AAH; 0101 0101(55H);becomes 1010 1010(AAH)

CJNE destination,source,rel. addr.

The actions of comparing and jumping are combined into a single instructioncalled CJNE (compare and jump if not equal)

The CJNE instruction compares two operands, and jumps if they are not equal

The destination operand can be in the accumulator or in one of the Rn registers

The source operand can be in a register, in memory, or immediate The operands themselves remain unchanged It changes the CY flag to indicate if the destination operand is larger

or smaller

Rotation Instructions:

RR A ;rotate right A

In rotate right The 8 bits of the accumulator are rotated right one bit, and Bit D0 exits from the LSB and enters into MSB, D7

RL A ;rotate left A

In rotate left The 8 bits of the accumulator are rotated left one bit, and Bit D7 exits from the MSB and enters into LSB, D0

RRC A ;rotate right through carry

In RRC A Bits are rotated from left to right They exit the LSB to the carry flag, and the carry flag enters the MSB

RLC A ;rotate left through carry

In RLC A Bits are shifted from right to left They exit the MSB and enter the carry flag, and the carry flag enters

the LSB

3. Data Transfer Instructions:

MOV A, R2 ; moving data from source R2 to destination Accumulator

This instruction will perform a Move the data in source to the destination.

The destination is normally the register, memory location. The source operand can be a register, in memory, or immediate

4. Boolean Instructions:

There are several instructions by which the CY flag can be manipulated directly Instruction FunctionSETB C Make CY = 1CLR C Clear carry bit (CY = 0)CPL C Complement carry bitMOV b,C Copy carry status to bit location (CY = b)MOV C,b Copy bit location status to carry (b = CY)JNC target Jump to target if CY = 0JC target Jump to target if CY = 1

ANL C,bit AND CY with bit and save it on CYANL C,/bit AND CY with inverted bit and save it on CYORL C,bit OR CY with bit and save it on CYORL C,/bit OR CY with inverted bit and save it on CY

5. Program Branching Instructions

DJNZ reg, Label

Repeating a sequence of instructions a certain number of times is called a loop

The register is decremented If it is not zero, it jumps to the target address referred to by the label Prior to the start of loop the register is loaded with the counter for

the number of repetitions Counter can be R0 – R7 or RAM location

Jump only if a certain condition is metJZ label ; jump if A=0

JNC label ; jump if no carry, CY=0

If CY = 0, the CPU starts to fetch and execute instruction from the address of the label If CY = 1, it will not jump but will execute the next instruction below JNC

JBC Jump if bit ＝ 1 and clear bitJNB Jump if bit ＝ 0JB Jump if bit ＝ 1JNC Jump if CY ＝ 0JC Jump if CY ＝ 1CJNE reg,#data Jump if byte ≠ #dataCJNE A,byte Jump if A ≠ byteDJNZ Decrement and Jump if A ≠ 0JNZ Jump if A ≠ 0JZ Jump if A ＝ 0

Addressing Modes of 8051

In short, a way to addressing a operand is nothing but addressing mode. Operand means data on which we are going to operate i.e source data. We can address the operand using direct address or by using register or we can address the data using some numerical value etc. MOVA,#6BHIn this example 6BH is operand i.e. source data. After execution of this instruction 6BH is added to the accumulator.We can execute this instruction by using 5 different ways i.e we can use 5 different addressing modes to execute this instruction. Following are the different type of addressing modes.

Immediate addressing mode Direct addressing mode Register addressing mode Register indirect addressing mode Indexed addressing mode.

1. Immediate addressing mode:As word indicates 'immediate' this addressing mode transfers 8 bit immediate data to destination. MOVA,#6BHThis instruction moves immediate data hex 6B to accumulator.

2. Direct addressing mode: This is type of addressing mode in which the address of the data (source data) is given as operand..i.e. it is given directly in the form of numerical data. MOVB,20H

The instruction above moves value at address 20H memory location to register B .

Here 20H is address of SFR.The difference between direct addressing and immediate addressing mode is, we don't use ‘#’ in direct addressing mode, unlike immediate mode.

3. Register addressing mode:This is type of addressing mode in which we use the register name directly as source data. MOV A, R5After execution of this instruction content of register R5 is get copied to location accumulator.

4. Register direct addressing mode :In this mode of addressing address of source data is given by value at register indirectly that's why we call it as a indirect register addressing mode. MOVA, @R1Here in this instruction register R1 holds the address, suppose value at R1 is '20H' then after execution of above instruction value at location 20H is transferred to to accumulator. Here symbol '@' indicates address. In this type addressing mode we can use only register R0 and R1 to provide indirect address.

5. Indexed addressing mode:In this type of addressing mode we use following instruction: 1. MOVC A, @A+DPTR and 2. MOVC A, @A+PC 'MOVC A, @A+DPTR' instruction copies value at the location given by result of addition of content of accumulator and 16 bit register DPTR. Suppose Accumulator contain '01H' and DPTR contains value '1000H' then after the execution of instruction 'MOVC A, @A+DPTR the value at address '1001H' will be transferred to accumulator. 'MOVC A, @A+PC' instruction copies value at the location given by result of addition of content of accumulator and 16 bit register PC (Program counter). Suppose Accumulator contain '01H' and PC contains value '1000H' then after the execution of instruction 'MOVC A, @A+DPTR the value at address '1001H' will be transferred to accumulator.

Timer Operation in 8051 Micro controller

The 8051 has two counters/timers which can be used either as timer to generate a time delay or as counter to count events happening outside the microcontroller.

The 8051 has two timers: timer0 and timer1. They can be used either as timers or as counters. Both timers are 16 bits wide. Since the 8051 has an 8-bit architecture, each 16-bit is accessed as two separate registers of low byte and high byte. First we shall discuss about Timer0 registers.

Timer0 registers is a 16 bits register and accessed as low byte and high byte. The low byte is referred as a TL0 and the high byte is referred as TH0. These registers can be accessed like any other registers.

Timer1 registers is also a 16 bits register and is split into two bytes, referred to as TL1 and TH1.

TMOD (timer mode) Register:

This is an 8-bit register which is used by both timers 0 and 1 to set the various timer modes.

In this TMOD register, lower 4 bits are set aside for timer0 and the upper 4 bits are set aside for timer1.

In each case, the lower 2 bits are used to set the timer mode and upper 2 bits to specify the operation.

The hardware way of starting and stopping the timer by an external source is achieved by making GATE=1 in the TMOD register. And if we change to GATE=0 then we do not need external hardware to start and stop the timers.

The second bit is C/T bit and is used to decide whether a timer is used as a time delay generator or an event counter. If this bit is 0 then it is used as a timer and if it is 1 then it is used as a counter.

In upper or lower 4 bits, the last bits third and fourth are known as M1 and M0 respectively. These are used to select the timer mode.

M0 M1 Mode Operating Mode

0 0 0 13-bit timer mode, 8-bit timer/counter THx and TLx as 5- bit prescalar.

0 1 1 16-bit timer mode, 16-bit timer/counters THx and TLx are cascaded; There are no prescalar.

1 0 2 8-bit auto reload mode, 8-bit auto reload timer/counter; THx holds a Value which is to be reloaded into TLx each time it overflows.

1 1 3 Spilt timer mode

Mode 1

It is a 16-bit timer; therefore it allows values from 0000 to FFFFH to be loaded into the timer’s registers TL and TH.

After TH and TL are loaded with a 16-bit initial value, the timer must be started. We can do it by “SETB TR0” for timer 0 and “SETB TR1” for timer 1.

After the timer is started. It starts count up until it reaches its limit of FFFFH. When it rolls over from FFFF to

0000H, it sets high a flag bit called TF (timer flag). This timer flag can be monitored. When this timer flag is raised, one option would be

stop the timer with the instructions “CLR TR0“ or CLR TR1 for timer 0 and timer 1 respectively.

Again, it must be noted that each timer flag TF0 for timer 0 and TF1 for timer1. After the timer reaches its limit and rolls over, in order to repeat the process the registers TH and TL must be reloaded with the original value and TF must be reset to 0.

Example program

To create a square wave of 50% duty cycle (with equal portions high and low) on the P1.5 bit. Timer 0 is used to generate the time delay

MOV TMOD, #01 ; Timer 0, mode 1(16-bit mode)

HERE: MOV TL0, #0F2H ; TL0=F2H, the low byte

MOV TH0, #0FFH ; TH0=FFH, the high byte

CPL P1.5 ; toggle P1.5

ACALL DELAY

SJMP HERE

In the above program notice the following step.

1. TMOD is loaded.

2. FFF2H is loaded into TH0-TL0.

3. P1.5 is toggled for the high and low portions of the pulse.

DELAY:

SETB TR0 ; start the timer 0

AGAIN: JNB TF0, AGAIN ; monitor timer flag 0; until it rolls over

CLR TR0 ; stop timer 0

CLR TF0 ; clear timer 0 flag

RET

4. The DELAY subroutine using the timer is called.

5. In the DELAY subroutine, timer 0 is started by the SETB TR0 instruction.

6. Timer 0 counts up with the passing of each clock, which is provided by the crystal oscillator. As the timer counts up, it goes through the states of FFF3,FFF4, FFF5, FFF6, FFF7, FFF8, FFF9, FFFA, FFFB, and so on until it reaches FFFFH. One more clock rolls it to 0, raising the timer flag (TF0=1).At that point, the JNB instruction falls through.

7. Timer 0 is stopped by the instruction CLR TR0. The DELAY subroutine ends and the process is repeated.

Mode 2

It is an 8 bit timer that allows only values of 00 to FFH to be loaded into the timer’s register TH.

After TH is loaded with 8 bit value, the 8051 gives a copy of it to TL. Then the timer must be started. It is done by the instruction “SETB TR0” for timer 0 and “SETB TR1” for timer1. This is like mode 1.

After timer is started, it starts to count up by incrementing the TL registers. It counts up until it reaches its limit of FFH. When it rolls over from FFH to 00.

It sets high the TF (timer flag). If we are using timer 0, TF0 goes high; if using TF1 then TF1 is raised.

When TL register rolls from FFH to 00 and TF is set to 1, TL is reloaded automatically with the original value kept by the TH register. To repeat the process, we must simply clear TF and let it go without any need by the programmer to reload the original value. This makes mode 2 auto reload, in contrast in mode 1 in which programmer has to reload TH and TL.

Example Program

To find the frequency of the square wave generated on pin P1.0 in the following program

MOV TMOD,#20H ;T1/8-bit/auto reload

MOV TH1, #5 ; TH1 = 5

SETB TR1 ; start the timer 1

BACK: JNB TF1, BACK ; till timer rolls over

CPL P1.0 ; P1.0 to hi, lo

CLR TF1 ; clear Timer 1 flag

SJMP BACK ; mode 2 is auto-reload

Solution:

First notice the target address of SJMP. In mode 2 we do not need to reload TH since it is auto-reload. Now (256 - 05) × 1.085 us =251 × 1.085 us = 272.33 us is the high portion of the pulse. Since it is a 50% duty cycle square wave, the period T is twice that; as a result T = 2 × 272.33 us = 544.67 us and the frequency =1.83597 kHz

TCON register

TCON register is the timer control special function register. In which lower nibble is used to control interrupt operation and higher nibble is used to control timer operation. Bits and symbol and functions of every bits of TCON are as follows:

BIT Symbol Functions

7 TF1 Timer1 over flow flag. Set when timer rolls from all 1s to 0. Cleared When the processor vectors to execute interrupt service routine Located at program address 001Bh.

6 TR1 Timer 1 run control bit. Set to 1 by programmer to enable timer to count; Cleared to 0 by program to halt timer.

5 TF0 Timer 0 over flow flag. Same as TF1.

4 TR0 Timer 0 run control bit. Same as TR1.

3 IE1 External interrupt 1 Edge flag. Not related to timer operations.

2 IT1 External interrupt1 signal type control bit. Set to 1 by program to Enable external interrupt 1 to be triggered by a falling edge signal. Set To 0 by

program to enable a low level signal on external interrupt1 to generate an interrupt.

1 IE0 External interrupt 0 Edge flag. Not related to timer operations. 0 IT0 External interrupt 0 signal type control bit. Same as IT0.

Interrupt Operation in 8051 Micro Controller

An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service.

There are six interrupt sources for the 8051, which means that they can recognize 6 different events that can interrupt regular program execution

Six interrupts are allocated as follows

1. Reset – power-up reset2. Two interrupts are set aside for the timers: one for timer 0 and one for timer 13. Two interrupts are set aside for hardware external interrupts P3.2 and P3.3 are for the

external hardware interrupts INT0 (or EX1), and INT1 (or EX2)4. Serial communication has a single interrupt that belongs to both receive and transfer

Each interrupt can be enabled or disabled by setting bits of the IE register. Likewise, the whole interrupt system can be disabled by clearing the EA bit of the same register. Refer to figure below.

EA - global interrupt enable/disable: 0 - disables all interrupt requests. 1 - Enables all individual interrupt requests.

ES - enables or disables serial interrupt: 0 - UART system cannot generate an interrupt. 1 - UART system enables an interrupt.

ET1 - bit enables or disables Timer 1 interrupt:

0 - Timer 1 cannot generate an interrupt. 1 - Timer 1 enables an interrupt.

EX1 - bit enables or disables external 1 interrupt: 0 - change of the pin INT0 logic state cannot generate an interrupt. 1 - Enables an external interrupt on the pin INT0 state change.

ET0 - bit enables or disables timer 0 interrupt: 0 - Timer 0 cannot generate an interrupt. 1 - Enables timer 0 interrupt.

EX0 - bit enables or disables external 0 interrupt: 0 - change of the INT1 pin logic state cannot generate an interrupt. 1 - Enables an external interrupt on the pin INT1 state change.

Interrupt Priorities

If several interrupts are enabled, it may happen that while one of them is in progress, another one is requested.

The IP Register (Interrupt Priority Register) specifies which one of existing interrupt sources have higher and which one has lower priority. Interrupt priority is usually specified at the beginning of the program. According to that, there are several possibilities

If an interrupt of higher priority arrives while an interrupt is in progress, it will be immediately stopped and the higher priority interrupt will be executed first.

If two interrupt requests, at different priority levels, arrive at the same time then the higher priority interrupt is serviced first.

If the both interrupt requests, at the same priority level, occur one after another, the one which came later has to wait until routine being in progress ends.

If two interrupt requests of equal priority arrive at the same time then the interrupt to be serviced is selected according to the following priority list:

1. External interrupt INT0

2. Timer 0 interrupt

3. External Interrupt INT1

4. Timer 1 interrupt

5. Serial Communication Interrupt

IP Register (Interrupt Priority) the IP register bits specify the priority level of each interrupt (high or low priority).

PS - Serial Port Interrupt priority bit

PT1 - Timer 1 interrupt priority

PX1 - External Interrupt INT1 priority

PT0 - Timer 0 Interrupt Priority

PX0 - External Interrupt INT0 Priority

Interrupt Handling Process:

Upon activation of an interrupt, the microcontroller goes through the following steps

1. It finishes the instruction it is executing and saves the address of the next instruction (PC) on the stack

2. It also saves the current status of all the interrupts internally (i.e: not on the stack)

3. It jumps to a fixed location in memory, called the interrupt vector table, that holds the address of the ISR

Interrupt Source Vector (address)

IE0 0003 h

IE1 0013h

TF0 000B h

TF1 001B h

RI, TI 0023 h

The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it

4. It starts to execute the interrupt service subroutine until it reaches the last instruction of the subroutine which is RETI (return from interrupt)

5. Upon executing the RETI instruction, the microcontroller returns to the place where it was interrupted

First, it gets the program counter (PC) address from the stack by popping the top two bytes of the stack into the PC

Then it starts to execute from that address

Serial communication in 8051 micro controller

The serial port of 8051 is full duplex, i.e., it can transmit and receive simultaneously.

The register SBUF is used to hold the data. The special function register SBUF is physically two registers. One is, write-only and is used to hold data to be transmitted out of the 8051 via TXD. The other is, read-only and holds the received data from external sources via RXD. Both mutually exclusive registers have the same address 099H.

Serial Port Control Register (SCON)

Register SCON controls serial data communication. Address: 098H (Bit addressable)

Mode select bits

SM2: multi processor communication bit REN: Receive enable bit

TB8: Transmitted bit 8 (Normally we have 0-7 bits transmitted/received) RB8: Received bit 8 TI: Transmit interrupt flag RI: Receive interrupt flag

Power Mode control Register

Register PCON controls processor power down, sleep modes and serial data band rate. Only one bit of PCON is used with respect to serial communication. The seventh bit (b7) (SMOD) is used to generate the baud rate of serial communication.

Address: 87H

SMOD: Serial baud rate modify bit GF1: General purpose user flag bit 1 GF0: General purpose user flag bit 0 PD: Power down bit IDL: Idle mode bit

Data Transmission

Transmission of serial data begins at any time when data is written to SBUF. Pin P3.1 (Alternate function bit TXD) is used to transmit data to the serial data network. TI is set to 1 when data has been transmitted. This signifies that SBUF is empty so that another byte can be sent.

Data Reception

Reception of serial data begins if the receive enable bit is set to 1 for all modes. Pin P3.0 (Alternate function bit RXD) is used to receive data from the serial data network. Receive interrupt flag, RI, is set after the data has been received in all modes. The data gets stored in SBUF register from where it can be read.

Serial Data Transmission Modes:

Mode-0: In this mode, the serial port works like a shift register and the data transmission works synchronously with a clock frequency of fosc /12. Serial data is received and transmitted through RXD. 8 bits are transmitted/ received at a time. Pin TXD outputs the shift clock pulses of frequency fosc /12, which is connected to the external circuitry for synchronization. The shift

frequency or baud rate is always 1/12 of the oscillator frequency.