WDM-based optical packet switch architectures

Vol. 7, No. 1 / January 2008 / JOURNAL OF OPTICAL NETWORKING 94

WDM-based optical packet switcharchitectures

Rajiv Srivastava,* Rajat Kumar Singh, and Yatindra Nath Singh

Department of Electrical Engineering, Indian Institute of Technology, Kanpur, UP,India. 208016

*Corresponding author: [email protected]

Received June 25, 2007; revised November 6, 2007;accepted November 6, 2007; published December 20, 2007 �Doc. ID 84352�

We have compared different loop buffer switch architectures in terms of theirfunctionality. Some of these architectures have already been proposed withonly their description and operation. The performance evaluation of theswitches has been done in terms of packet loss probability for random andbursty traffic. A new architecture has been proposed, which incorporates thegood features of the existing architectures. © 2007 Optical Society of America

OCIS codes: 060.0060, 210.0210.

1. IntroductionPhotonic switching will be the most promising data transmission technology in thenear future. It not only allows utilization of the higher bandwidth of the fiber by usingwavelength division multiplexing (WDM) technology, but also keeps the data in opti-cal form throughout the switch. One of the main hurdles in optical switching is thecontention among the packets. This contention arises when, for the same destination,more than one packet arrives in the same time slot. In optical domain fiber delay linesare the easiest solution to store the contending packets temporally [1–3]. Hence, thesefiber delay lines are the critical component in the design of the switch architecture.Number of fiber delay lines used in any architecture can be reduced by using wave-length conversion.

In this paper, fiber-loop-buffer-based photonic packet switch architectures are com-pared. All these architectures use recirculating-type delay lines for the storage ofpackets. Some of these architectures contain tunable wavelength convertors (TWCs)inside the buffer, which can also resolve contention among the packets in wavelengthdomain. All the architectures are designed for equal length packets and these packetsare assumed to be frame aligned when they arrive at the input of the switch. Aftermaking comparisons among the architectures, we propose a new architecture thatincludes the good features of all the existing architectures that have been discussed inthis paper.

The paper is organized as follows. Architectures under investigation are describedin Section 2. The buffering and read–write operations are explained in Section 3. InSection 4, dynamic wavelength reallocation is described. The control unit complexityis explained in Section 5. In Section 6, buffering capacity is described. Physical lossesof the architectures are compared in Section 7. The algorithm for the operation ofswitches is given in Section 8. Simulation results are presented in Section 9. Finally,the conclusions are given in Section 10.

2. Description of the Architectures2.A. Loop Buffer Architecture A1The initial design (Fig. 1) proposed by Bendelli et al. [4] consists of N TWCs (one ateach input), a random wavelength accessible recirculating loop buffer having semicon-ductor optical amplifiers (SOAs) as gate switches for a specified number of wave-lengths, and N tunable filters (TF), one at each output. The TWCs at the inputs aretuned at every time slot to place a packet in the loop buffer to avoid contention. Forreading–removing a packet from the buffer, the particular SOA gate is switched“OFF” and the tunable filter at the output is tuned to the packet wavelength. Thepackets from the buffer are broadcast to all the output ports but selected by thedesired port only.

1536-5379/08/010094-12/$15.00 © 2008 Optical Society of America


2.B. Loop Buffer Architecture A2The first modified architecture also consists of N TWCs (one at each input), a recircu-lating loop buffer where the buffer SOAs are replaced by the TWCs, and N output TFsare replaced by N fixed filters (FF) [5]. In this architecture another modification isproposed in [6], as shown in Fig. 2 and referred to as architecture A2. Here, the physi-cal loss of the architecture is reduced by replacing the combination of splitter and FFsby a single arrayed waveguide grating (AWG) demultiplexer. In the splitter and FFcombinations, the splitter divides the total power in equal parts and FFs select a par-ticular wavelength. This can be achieved using an AWG demultiplexer with much lessinsertion loss. In the modified architecture, for the removal of the packets from thebuffer, the TWC inside the buffer tunes the wavelength of the packet as per the rout-ing pattern of the AWG. The TWCs at the inputs are tuned in every time slot to appro-priate wavelength to place, a packet in the loop buffer to avoid contention or to directthem to the appropriate output port.

In both the architectures, packets from all the inputs use WDM technology to sharethe loop buffer [1]. The number of buffer wavelengths (size of memory) depends on thedesired traffic throughput, packet loss probability, and various component parameters[7,8]. The packet to be buffered is converted to the wavelength available in the buffer;if memory is full, then the packet cannot be stored, and will be lost.

2.C. Loop Buffer Architecture A3In this architecture (Fig. 3) [9], the AWG demultiplexer (AWG-1) is used to separatethe buffer wavelengths and the AWG multiplexer (AWG-2) is used to again combinethem. In the buffer two SOA gates (SOA1 and SOA2) are placed in each branch of theAWGs. SOA1 acts as a gate between two buffer AWGs labeled as AWG-1 and AWG-2and SOA2 acts as a gate between AWG-1 and B�1 AWG as shown in the inset.

In the architecture, once wavelength is assigned by the input TWC the packet willkeep on circulating in the loop buffer at the same wavelength, while SOA1 in thebuffer will remain in the ON state and SOA2 in the OFF state, until it is desired toread out a packet from the loop buffer. For the removal of the packet from the loopbuffer, the respective SOA1 is turned OFF and SOA2 is turned ON, and the packet is

Fig. 1. Schematic of loop buffer architecture A1.



directed towards the output B�1 AWG. All the packets appear at one port of theAWG, from where the multiplexed signals are allowed to pass through the splitter anda particular wavelength is selected by the TF, which is placed in each branch of thesplitter.

2.D. Loop Buffer Architecture A4Figure 4 depicts the architecture proposed in this paper. In this architecture oncewavelength is assigned by input TWC, the packet will keep on circulating in the loopbuffer at the same wavelength and the TWC inside the buffer will remain transparentuntil it is desired to readout a packet from the loop buffer. For the removal of thepacket from the loop buffer, the respective TWC in the loop buffer tunes the wave-length of the packet corresponding to the appropriate output port as per the routingtable of the B�N AWG. The connection between the two AWGs placed inside thebuffer and the one placed at the output is shown in inset. In this architecture thebuffer unit gets simplified. In each branch that connects AWG-1 and AWG-2, only oneTWC is required as compared to two SOAs in the architecture A3. Similarly at theoutput unit only one AWG is required in comparison to three components such asAWG, splitter, and TF in architecture A3. In the next few sections the above architec-tures are compared in terms of their functionality.

3. Buffering and Read–Write OperationIn the original design (Fig. 1), the buffer memory has a word size equal to one cellperiod. Its capacity corresponds to predetermined memory positions or the number ofbuffer wavelengths. A packet is assigned a wavelength not being used by the packetswithin the buffer by the input TWC, as shown in Fig. 5(a). The SOA (Fig. 1) is turnedON to accept the packet in the buffer. To readout the packet from the buffer in archi-tecture A1, the packets are broadcast to the output by switching OFF the appropriateSOA gate and simultaneously the output filter is tuned to the packet wavelength. The




read–write operation is shown in Fig. 5(b). It can be observed that writing to the samebuffer wavelength as that being read from cannot be done simultaneously; it is pos-sible only after two cell periods.

In the first modification (Fig. 2) the loop SOA gates are replaced by TWC’s. Thebuffer TWCs can be tuned to any of the buffer or output wavelengths. As shown inFig. 5(c), a packet at �b is written into the buffer, by tuning the input TWC to bufferwavelength �b. It takes one cell period for writing a packet; this is the minimum timea packet can be buffered. Assuming that contention is resolved while a packet is beingbuffered, then the buffer TWC is tuned to �out to direct the packet towards the output.The packet is readout from the buffer after getting converted to �out. After conversion,as the complete packet crosses the TWC, in the process of being buffered out, theTWC is tuned back to the same buffer wavelength �b as before. Hence the writing ofa new packet in this wavelength can take place simultaneously as a packet from thebuffer is being readout from the buffer. Due to the similar operation of the architec-ture A4, simultaneous read–write operation is also possible in architecture A4whereas architecture A3 does not support simultaneous read–write operations.

4. Dynamic Wavelength ReallocationA minimum channel spacing of six times the maximum data rate has been proposedand examined in literature to minimize the cross talk [10]. It will be possible todynamically modify the channel spacing, while a packet is circulating in the loopbuffer, to minimize cross talk in DWDM networks with the use of TWCs as buffergates. This will give flexibility in operation by tuning a packet wavelength to anyother available wavelength in the buffer. However, there is a limit on the maximumnumber of circulations [11], and hence, on the maximum time for which a packet canremain in the buffer to resolve an output contention. One of the factors responsible forthis limit is cross talk. The dynamic wavelength reallocation will reduce the noise dueto cross talk and in turn result in an increase in maximum buffering time. Hence thiswavelength conversion reduces the packet loss probability [12]. Dynamic wavelengthreallocation is shown in Fig. 6(a). This operation is possible in architectures A2 andA4 only.

Fig. 5. Schematic of read–write operation in the buffer. t1−3: cell periods, P1,2: datapackets; �1: SOA gate, �bb, �bo: TWC tuning time to �b, �out, �b: buffer wavelength; �out:output wavelength; W: write operation; R: read operation


5. Control Unit ComplexityThe control operation of routing, scheduling, data forwarding, etc. is implementedelectronically and the actual data transmission takes place optically. Tasks assignedto the control unit [Fig. 6(b)] are header recognition, routing control, tracking bufferstatus, tracking input–output port status, synchronization of operation of switch com-ponents with master clock in reference, communication with other switching nodes,and a packet-scheduling algorithm, among others.

The complexities in the control unit increase with DWDM application where thenumber of input channels in large and data rate is very high. Therefore more photo-nic components will require synchronized control. The modification of introducingTWC gates in place of SOA results in reducing one dynamic component, i.e., TF at theoutput block of the switch. The attempt to introduce a passive photonic component,i.e., FF, in the existing switch architecture yet maintain the same switch operationalcharacteristics, eases the complexities of the control unit as there will be fewer activecomponents to control and synchronize. The control complexity of the architectures A2and A4 is lowest as only two components, input and buffer TWCs, have to be con-trolled. For architecture A1, control unit complexity is moderate as threecomponents—the input TWCs, buffer SOAs, and output TFs—have to be controlled.The control unit complexity is very high for architecture A3. Here four components,i.e., input TWCs, two buffer SOAs, and TFs at the output have to be controlled by thecontrol unit.

In [13], the authors have presented an architecture in which control unit complex-ity is reduced to one component input TWCs only. This architecture has not been con-sidered here as the queuing structure for this architecture is different from the archi-tectures under consideration.

6. Buffer CapacityFor the architectures A1 and A2 the buffer capacity �B� can be fully utilized, but forthe architectures A3 and A4, the buffer capacity is shared by the directly transmittedand buffered packets. Between the architectures A1 and A2, the latter utilizes thebuffer capacity more effectively, as for this architecture simultaneous read–writeoperation is possible that is not possible for the architecture A1.

7. Physical Loss of the ArchitecturesThe physical loss in the architectures has been calculated by considering the insertionloss of each device. The loss due to each component is written in the form Ai

j, where idenotes the component type and j denotes the size of component. This analysis canalso be viewed as the cost analysis of the architectures as the cost of architectures alsodepend on the number and type of components.

Fig. 6. (a) Schematic of dynamic wavelength reallocation. (b) General layout of signalflows and control information in electronic control unit.


The switch architectures are divided into three parts for the description of the lossand are named Ain, which includes the loss from switch input to 3 dB coupler input;Aout includes the loss of a 3 dB coupler and components after that in case of directtransmission; and Aloop is the loss in the loop for each of the architectures. Thenumerical values of the losses for the architectures are calculated using Table 1. Inthe equations, N is the switch size and B is the buffer capacity. In the calculation sizeof the switch �N� is assumed to be 4�4 and buffer space �B� is also assumed to befour. All the following equations are expressed in decibels.

The losses in the architecture A1 can be modeled as

Ain = ATWC + AcomN�1,

Aout = A3 dB + Asplitter1�N + ATF,

Aloop = A3 dB + Ademux1�B + ASOA + Acom

B�1 + Aiso. �1�

The typical numerical values of losses are Ain=8 dB, Aout=11 dB, and Aloop=11.65 dB. Here the loss of the loop is compensated by the amplifier placed in thebuffer, thus G1=11.65 dB, and the packets that pass through the switch suffers a lossof Ain+Aout=19 dB. For all the architectures we have assumed that loop loss is com-pensated by the amplifier gain.

The losses in architecture A2 can be written as


Aout = A3 dB + Ademux1�N ,

Aloop = A3 dB + Ademux1�B + ATWC + Acom

B�1 + Aiso. �2�

Here the typical values of losses are Ain=8 dB, Aout=4.5 dB, and Aloop=12.65 dB andthe amplifier gain is G2=12.65 dB. The packets that pass through the switch suffer aloss of 12.5 dB, which is less as compared to architecture A1.

The losses in architecture A3 can be formulated as


Aout = A3 dB + Ademux1�B + Asplitter

1�2 + ASOA + Ademux1�B + Asplitter

1�N + ATF,

Aloop = A3 dB + Ademux1�B + Asplitter

1�2 + ASOA + AmuxB�1 + Aiso. �3�

Typically Ain=8 dB, Aout=18 dB, and Aloop=10.15 dB. Thus G3=10.15 dB, and hencethe packets that pass through the switch suffer a loss of Ain+Aout−G3=15.85 dB.Here, G3 is subtracted from the total loss because the position of the erbium-dopedfiber amplifier (EDFA) in the loop is such that the directly transmitted packets alsoget amplified.

Similarly the losses in architecture A4 can be calculated as

Table 1. Insertion Loss of Different Components

Symbol QuantityValue(dB)

A3 dB Loss of 3 dB coupler 3.0ACom

N�1 Combiner loss 10 log10 NASplitter

N�1 Splitter loss 10 log10 NADemux

N�1 Loss of demultiplexer (AWG) 1.5� �log2 N−1�ATWC Loss of TWC 2.0 dBAMux

N�1 Loss of multiplexer 1.5� �log2 N−1�ASOA Insertion loss of SOA 1.0AIso Isolator loss 0.15ATF Loss of TF 2.0AFF Fixed filter 1.0



Aout = A3 dB + Ademux1�B + ATWC + Asplitter

1�2 + Ademux1�N ,

Aloop = A3 dB + Ademux1�B + ATWC + Asplitter

1�2 + AmuxB�1 + Aiso. �4�

The typical values of the above losses are Ain=8 dB, Aout=11 dB, and Aloop=11.15 dB. Here the loss of the loop is compensated by the amplifier placed in thebuffer, thus G4=11.15 dB, and the packets that pass through the switch suffer a lossof Ain+Aout−G4=7.85 dB, which is the lowest among all the architectures under con-sideration. Typical values of the losses considered in Table 1 are taken from the litera-ture [14].

8. Algorithm of the SwitchesFor architectures A1 and A2, the switch uses �B+N� wavelengths, where B is thenumber of buffer wavelengths, and N is the number of wavelengths used for directtransmission to the output bypassing the fiber loop [15]. For architectures A3 and A4the switch uses B wavelengths only. The algorithm steps are given below.

(1) All-optical wavelength converters at the inputs of the switch can be tuned toany of the �B+N� wavelengths (for architectures A1 and A2) or B (for architectures A3and A4) wavelengths instantaneously.

(2) For architectures A2 and A4, the buffer is such that read and write operationsare allowed simultaneously in the same slot for the loop buffer wavelength.

(3) If there are i�1� i�b� packets in the buffer, where 2�b�B, for the output j,only one of i packets will be sent to the output j. If in the same slot, there are one ormore packets also present at the inputs for the output j, then these will be buffered inthe loop buffer to the extent allowed by the rules 4–6. Any leftover packets for outputj will be dropped.

(4) Considering the case when there is no packet in the buffer for the output j, butm input lines have packets for that output, then one of these m packets is directlysent to output j in architectures A1 and A2. The remaining m−1 packets will be buff-ered in the buffer to the extent allowed by the rules 5 and 6. For architectures A3 andA4 all the m packets will be put in the buffer to the extent allowed by rules 5 and 6.

(5) The number of packets Xj in the buffer for the output j should never be greaterthan B, i.e., Xj�B for j=1, . . . ,N.

(6) The total number of buffers used should never be greater than B, i.e., �Xj�B.

9. Simulations and ResultsIn this section we examine the packet loss probability of the switch under the variousload conditions. This investigation is done by the computer simulation. In this simu-lation two traffic models have been considered.

9.A. Random Traffic ModelThe random traffic model is simple; still it provides good insight into the performanceof the architecture. This model assumes that the packet can arrive at any of theinputs with probability p and each packet is equally likely to be destined to any of theN outputs with probability 1/N. Thus the probability that K packets arrive for a par-ticular output in any time slot is given by

Pr�K� = NCK� P

N�K�1 −P

N�N−K

, 0 � K � N. �5�

In Fig. 7(a), packet loss probability versus load on the system is plotted for differentbuffer architectures for the random traffic model. It can be visualized from the figurethat the performance of architecture A2 is better as compared to other architectures,while the performance of architecture A3 is the poorest. At the load of 0.7 the packetloss probability of architecture A2 is 100 times better than architecture A3. InFig. 7(b), packet loss probability versus allowed buffer space is plotted at the load of


0.8 for all the architectures. Our architectures A2 and A4 perform better as comparedto architectures A1 and A3. It can be concluded from these figures that architectureA2 performs better as compared to other architectures. The explanation lies in thefact architecture A2 allows simultaneous read–write operations, unlike architecturesA1 and A3. Furthermore, all the buffer wavelengths are used for the buffering in con-trast to architectures A3 and A4, where buffer wavelengths are shared betweendirectly transmitted and buffered packets. The performance of architectures A2 andA4 are comparable to each other, and better than that of architectures A1 and A3.This clearly indicates that simultaneous read–write operations have an impact on theswitch performance. In Fig. 8(a) the probability of packet loss versus load on the sys-tem is plotted for architectures A2, A3, and A4. Here, the allowed buffer space forarchitectures A3 and A4 is 16 and for architecture A2 it is 8, 10, 12, and 16. It can beseen from the figure that architecture A2 with buffer space 10 gives the same resultsas architecture A3 for B=16. Similarly architecture A4 with buffer space B=16 givesthe same results as architecture A2 with buffer space 12. In Fig. 8(b) packet loss prob-ability versus allowed buffer space at different loading conditions is plotted for archi-tecture A3. Here, as expected, packet loss probability increases as the load increases.

9.B. Bursty Traffic ModelIn reality data traffic is usually bursty in nature. In the bursty traffic, arrivals arecorrelated, i.e., packets arrive in the form of burst. It is characterized by the offeredload �� and burst length �BL� [16]. Each burst of packets is equally likely to be des-tined to any one of the output with probability 1/N.

This also implies that if a packet arrives on input i and is destined for the output jin the current slot, then there is a small but finite probability that in the next slotpacket arrives for the same destination. Thus in the time domain, the traffic at each

Fig. 7. (a) Packet loss probability versus load on the switch for switch configurationN=4, B=8. (b) Packet loss probability versus allowed buffer space for switch size N=4.

Fig. 8. (a) Packet loss probability versus load for N=4, and different buffer combina-tions. (b) Packet loss probability versus allowed buffer space for N=4 at different loadfor the architecture A2.


input is composed of a burst of packets destined for the same output. Time correlationof the traffic on each input is characterized by the Markov chain model. This modelassumes three states: idle, burst I, and burst II states (Fig. 9).

The system will be in the idle state if no packet arrives in the current slot. If weconsider that with probability Pa no packet arrives in the next slot, then the systemwill remain in an idle state. Thus, with probability �1−Pa� a new burst will start andthe system will go in the burst state 1. Now considering that with probability Pb anew burst will arrive for the same destination, the burst can terminate in two ways:(1) a new burst starts for another destination with probability �1−Pa��1−Pb�, and (2)by going to the idle state with probability �Pa��1−Pb�.

The steady-state distribution of the Markov chain can be obtained as

�P = �. �6�

Where � is row vector �= ��1 �2 �3� and P is the transition matrix. �j is the prob-ability of being in state j. Now, Eq. (6) can be expressed in terms of Pa, Pb, and vector� as

�Pa �1 − Pb�Pa �1 − Pb�Pa

�1 − Pa� Pb �1 − Pa��1 − Pb�

0 �1 − Pa��1 − Pb� Pb��

�1

�2

�3� = �

�1

�2

�3� , �7�

where

i=1

3

�i = 1. �8�

By solving Eqs. (7) and (8), we get

�1 =Pa�1 − Pb�

1 − PaPb, �2 =

�1 − Pa�

�1 − PaPb��2 − Pa�, �3 =

�1 − Pa�2

�1 − PaPb��2 − Pa�. �9�

The average link utilization can be obtained as

� = 1 − �1 =�1 − Pa�

�1 − PaPb�. �10�

The probability that particular bursts have K packets is

Pr�K� = �1 − Pb��Pb�K−1, K � 1. �11�

Thus, the average burst length can be obtained as

BL = K=1

K . Pr�K� =1

1 − Pb. �12�

Fig. 9. Markov chain model for the bursty traffic.


In Fig. 10(a), packet loss probability versus load is plotted for the system for thebursty traffic. In this figure, three architectures—A2, A3, and A4—have been com-pared. Here, for the less bursty traffic �BL=2� the performances of architectures A3and A4 are comparable to each other. They perform more poorly than architecture A2,but as the data become more bursty �BL=4� in nature architectures A3 and A4 givenearly the same performance but it is still poorer than the performance of architec-ture A2, whereas architecture A2 still performs better. In Fig. 10(b), packet loss prob-ability is plotted versus load on the system for architecture A3 at a different burstlength. Here, the packet loss probability increases with burst length. The degradationand convergence in packet loss probability versus load on the system is fast as com-pared to the random traffic. In Fig. 11(a), packet loss probability versus allowed bufferspace is plotted. It is observed that as the data becomes more bursty in nature, thepacket loss probability starts to increase and this degradation becomes more severewith the load on the system. It can be observed in the figure, at the load of 0.9 andBL=4, the packet loss probability becomes nearly independent of the buffer space.

In Fig. 11(b), we have compared the required buffer space at different loading con-ditions to obtain a packet loss probability of 10−4. The data is presented in Table 2. Itis clear from the figure that as the load increases more buffer space is required tomaintain the same packet loss probability. Thus as the data becomes more bursty innature, comparatively large buffer space is required. This happens because for thelarger burst length there is a finite probability that as more packets arrive for the par-ticular destination, and a major portion of the buffer gets occupied in a very shortperiod, some additional buffer space is required to accommodate packets for the otheroutputs, even they are fewer in number.

Fig. 10. (a) Packet loss probability versus load on the system for N=4, B=16, BL=2(solid curve), BL=4 (dotted curve). (b) Packet loss probability versus load on the systemfor N=4, B=8 at different burst lengths for the architecture A2.

Fig. 11. (a) Packet loss probability versus allowed buffer space for switch size N=4 forthe architecture A2. (b) Allowed buffer space versus load on the switch, for architecture
A2 with size N=4 for different traffic.


10. ConclusionsIn this paper different photonic switch architectures have been compared. The perfor-mance evaluations of the switches are done in terms of their functionality packet lossprobability and effective buffer utilization. The results have been summarized inTable 3. All these architectures have their specific advantages and disadvantages. Ithas been found that architecture A2 will perform better than other architectures pre-sented in the paper. It can also be concluded that as the data becomes more bursty innature, there is not enough of an advantage of increasing the buffer space. At veryhigh load the packet loss probability becomes nearly independent of the buffer space.

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Table 3. Comparison of Different Buffer Architectures in Terms ofFunctionality

Architecture Type A1 A2 A3 A4

Simultaneous R /W Not possible Possible Not possible PossibleWavelength reallocation Not possible Possible Not possible PossibleControl complexity Moderate Lowest Highest LowestNumber of components Moderate Lowest Highest ModerateBuffer utilization Moderate Highest Lowest ModeratePacket loss probability Moderate Lowest Highest Moderate

Table 2. Comparison of Buffer Space at Different Loading Condition forDifferent Traffic

Buffer Space(Random Traffic)

Buffer Space(Bursty Traffic BL=2)

Buffer Space(Bursty Traffic BL=4)

Load BR BT BT /BR BT BT /BR

0.1 2 5 2.50 10 5.000.2 3 7 2.33 17 5.610.3 4 9 2.25 23 5.600.4 4 11 2.75 27 6.750.5 6 14 2.33 33 5.500.6 7 18 2.57 42 6.000.7 10 24 2.40 53 5.300.8 16 37 2.31 82 5.120.9 33 68 2.07 157 4.76


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WDM-based optical packet switch architectures