WCDMA/GSM/GPRS/Polar EDGE Power Amplifier …application-notes.digchip.com/057/57-40026.pdf05/2006 Application Note WCDMA/GSM/GPRS/Polar EDGE Power Amplifier Module with Integrated

05/2006

Application NoteWCDMA/GSM/GPRS/Polar EDGE

Power Amplifier Modulewith Integrated Power Control

Revision 0

Figure 1: Recommended Application Circuit

RELEVANT PRODUCTS• AWT6223

INTRODUCTIONThis WEDGE Power Amplifier Module supports GSMtype dual, tri and quad band applications for GMSKand 8-PSK modulation schemes using a polararchitecture, as well as WCDMA in the IMT band.The WEDGE module includes an internal referencevoltage and integrated power control scheme foruse in GMSK and 8-PSK operation, which facilitatesfast and easy production calibration and reducesthe number of external components required tocomplete a power control function. This integratedcontrol loop reduces the development timeassociated with optimizing loop filters to meet timemask and switching transient requirements, as it iscompletely self-contained.

The module size is a competitive 6 mm x 8 mm andwith the few external components required, it is wellsuited for a small form factor transmit front-endsolution.

GENERAL DESCRIPTIONThe application circuit below shows the relativeease with which this amplifier can be designed intoa GSM transmit front-end. All of the RF ports for thisdevice are internally matched to 50Ω.

The RF inputs can interface to transmit VCO’s withthe addition of simple attenuators. These can beused to set the input drive to the PA and is generallygood practice to help minimize any possible loadpulling effects at the VCO, PA interface. The RFoutputs can interface directly to an antenna switchmodule to complete the front-end solution.

The logical control inputs, TX_EN and BS, are both1.8 V and 3 V logic compliant. The TX_EN is used toenable the amplifier typically with the TX burst. TheBS is used to select which amplifier is enabled.

GSM850/900 RF OUTPUTGSM850/900 RF INPUT

1

2

3

4

5

6

7

18

17

16

15

14

13

12

11

22

DCS/PCS_PIN

BS

TX_EN

VBATT

CEXT1

VRA MP

GSM_IN

VCC_GSM

CEXT2

GND

GND

GSM_OUT

CEXT3

GND

GND

DCS/PCS_OUT

AWT6223R

DCS/PCS RF INPUT

BAND SELECT

TX ENABLE

DAC OUTPUT

DCS/PCS RF OUTPUT

BATTERYVOLTAGE

10K* 27pF*

* Filtering may be required to filter noise from baseband.

** This component should be placed as close to the device pin as possible.

*** If the final design uses a DC-DC Converter, otherwise connect Pin 21 directly to VBATT.

++ These components are recommended as good design practice for improving noise rejectioncharacteristics. The values specified are not critical as they may not be required in the finalapplication.

2.7pF**4.7uF++

22nF**

27pF++

27pF++

8

9

10

19

20

21

GND

WCDMA_OUT

V CC_WCDMAWCDMA_IN

VEN

VMODEWCDMA RF OUTPUT27pF++

27pF++WCDMA ENABLE

WCDMA BIAS MODE

IMT RF INPUT

1nF**

4.7uF++ 22pF**10nF++

22pF**10nF++

SUPPLY VOLTAGE FROMDC-DC CONVERTER***

2 Application Note - Rev 005/2006

WCDMA/GSM/GPRS/Polar EDGE Power Amplifier Module

POWER CONTROLThe scheme used is a closed loop method thatrequires only the application of an analog voltage tothe VRAMP pin to set the output power. This can beapplied directly from a standard DAC output. Themethod used does not require any power or currentsensing. Setting the VRAMP voltage, in turn sets thecollector voltages of the power amplifiers to amultiple of the VRAMP voltage using a pre-determinedformula. This collector voltage is regulated in avoltage control loop as shown below. The amplifier’sbias is held constant while the collector voltage isadjusted to set the power. The relationship betweenthe output power and collector voltage is describedby Equation 1.

Equation 1

where VCC, VSAT are the collector voltage andsaturation voltage of the transistor respectively. This

LOAD

SATCCOUT R

VVWattsP

⋅−⋅

=8

)2()(

2

VBATTVRAMPV 6.120.038.0 ≤+⋅≤

expression shows how the power variation due toVBATT is limited due to voltage control loop.

Under extreme conditions, as the battery voltagedegrades, it is important to maintain the control loopbandwidth, so the collector voltage quickly followsVRAMP. This is done by adjusting VRAMP, such that:

Equation 2

The effect of the loop bandwidth slowing can be seenmost clearly in the switching transientsmeasurement. This adjustment can be incorporatedin the software of the final application, so thatperformance is enhanced under low voltageconditions. Another advantage of this control schemeis the improved noise performance due to individualstages being held in compression, thus improvingthe overall receive band noise performance.

Figure 2: Voltage Control Loop

Application Note - Rev 005/2006

3


DESIGN RECOMMENDATIONS

1. RF DECOUPLINGTo comply with any potential radiated contributionaround the PAM mostly related to PCB design it isgood practice to place two RF decoupling ceramiccapacitors on pins 7 and 22 of the AWT6223, asclose to the PAM as possible. Also, provision shouldbe made to bypass VBATT at the battery connectorwith the same level of decoupling. This can beaccomplished by placing two ceramic capacitorssimilar to the one at VBATT pin 7 as close as possibleto the VBATT pin of the battery connector. The groundingof any bypass capacitors is critical to achieve theexpected improvements. All GND for decouplingcapacitors should be connected to the main GND-plane as directly as possible preferably usingmicrovias, see PCB cutout in Figure 3.

The values of the capacitors chosen depend on theirlocation, grounding and physical size. These factorsdetermine the resonant frequency at which thedecoupling is most effective. One cap should beoptimized for the GSM850/900 band performance,the other for DCS/PCS and IMT. The VBATT line to theAWT6223 pin 7 should be kept as short as possibleand preferably shielded inside the PCB betweentwo GND layers (known as stripline) in order tosuppress radiation originating from this line.

2. INPUT POWERThe GSM quad-band part of the AWT6223 operatesover the 0 to 5 dBm range and has been optimizedfor best typical performance at 3 dBm. ANADIGICSrecommends a series capacitor and resistive

attenuator to be placed between the VCO and PAM.Some transceiver designs require a capacitorbetween the VCO output of the chipset and theresistive attenuator on the input of the PAM becausethe VCO output has a DC offset. The attenuator helpsprevent load pulling of the VCO by further improvingthe return loss and also gives the flexibility to optimizethe input drive to the PAM, which will depend on thetransceiver output power and losses prior to thePAM. In order to avoid potential problems of strongRF signals radiating or coupling to other parts ofthe circuit, we suggest that the attenuator is placedas close to the transceiver chip VCO output aspossible.

3. MATCHING BETWEEN PA AND ANTENNA SWITCH MODULE (ASM)

Provision should be made for matching the ASM to50 ohms. Though the ASM usually specifies 50ohms impedance, the actual impedance on the PCBis dependent on the transmission lines at the PAinterface, and any vias and buried layer routing. Thisis rarely 50 ohms. A T-network or π-network isrecommended for the matching as this givessufficient flexibility. The component values used forthe matching are dependent on the impedancepresented by the ASM used.

4. ANALOG RAMP VOLTAGE INPUTAt the GSM/EDGE VRAMP input pin 9 an analog voltageto set the output power can be applied directly froma standard DAC output. In order to smooth this DACoutput staircase shaped signal, it is recommendedto make provision for an RC filter. The values for thisfiltering depend on DAC bit resolution and samplerate.

5. WCDMA PA OUTPUTThe majority of current WCDMA design solutionsusing ANADIGICS WCDMA PAMs do not require anisolator or circulator in the front end design in orderto reject any reverse signal from the duplex filterand antenna due to mismatch. The impedance ofthe duplex filter often changes in the upper TXfrequency area where it is about to cut off and filterout TX signals in order to separate TX & RX as theupper TX frequency is closest to the RX frequencyarea. The load deviates from the ideal 50 Ω andincreases the mismatch seen at the WCDMA PAoutput. The WCDMA PA stage would in most casesbe able to address this, by decreasing output powerby a relative small level of approximately 1 dB.

Figure 3: Example of GND Connection from PadUsing Microvia and Buried Via

COMPONENTS

SIGNAL

MICROVIA

SIGNAL

GND

Buried or through VIA



Components

PA

Signal

Signal

GND

Power

GND

Signal Keypad

Figure 4: Example of PCB Stack-up withMicrovias from Top and Bottom Layers, BuriedVias from Layers 2 to 7, and through Vias from

Layers 1 to 8

For more information regarding GND underneaththe PAM, please refer to the “Package Outline”chapter and the “Soldering Guidelines for ModulePCB Mounting - Application Note”. Generally, it isgood practice to establish shielding around the PAM.For the shielding to be effective, a good GND-connection is also required. Therefore a lot of vias

VIAS

GND Land area for shielding

Figure 5: Example of Via Placement at ShieldingLandpattern Close to PA

7. RF TRACKSKeep RF tracks as short as possible and with asfew corners and bends as possible. Make openingsin the ground plane on the layer just under all 50 Ωpads on the PAM and the FEM (Front End Module) orASM (Antenna Switch Module). The short distancebetween the component layer and the first inner layeris very small compared to the pad size. This meansthat the pads terminate the transmission line in lowimpedance much different from that of the track. Theresult of this is mismatch, which again can result inup to a couple of dB loss of signal. As a rule,ANADIGICS normally uses a clearance aroundmicrostrips and striplines of at least the same widthas that of the track, i.e. if the track width is 12 mil or0.3 mm, the clearance on both sides of the track toany copper area is also 12 mil or 0.3 mm.

Generally, keep reference clock signals, digitalsignals or analog I and Q signals away from RFtracks and VBATT connections. Make sure that thesedifferent signal connections are not running directlyunderneath or above RF tracks or VBATT.

6. PCB LAYOUT GROUNDINGTo have the best performance good grounding iscrucial. “Local ground planes” only connected to theboard GND plane using a few microvias is notadequate. All GND planes must be connected to themain GND layer (one designated inner layer of thePCB) using a lot of through vias. Besides being thereference for the all RF and other signals, the GNDplane is also used to distribute the heat dissipatedby the PA and should therefore by sufficient size andwith many through vias to spread the heat to othercopper layers. In order to establish a good groundconnection for the PA, it is necessary to assign anarea on the first inner layer to GND. Microvias will gofrom the large GND pad under the PA to area on thefirst inner layer and buried or through vias will go therest of the way to the ground plane in the center ofthe board, see Figure 4.

should be used, where the shielding - whether it ismetallized plastic or a traditional shielding can - isattached to the PCB surface, see Figure 5.


5


SETUP RECOMMENDATIONS1. TIMINGIn order to meet the ETSI specified GSM power timetemplate and switching transients, the sequence ofevents outlined in Figure 6 is recommended. Thetiming on BS is not critical; it just needs to be enabledand settled prior to TX_EN going high (approx. 2µs). The PA “forward isolation 1” parameter and the

ASM isolation is met outside burst. The PA “forwardisolation 2” parameter ensures the time template ismet during the burst with sufficient margin. Thetiming of the TX_EN is critical to ensure theapplication has sufficient margin for meeting theburst timing requirement.

Figure 6: Timing Recommendations

dBm

t ( s)

GSM TRANSMITTED POWER vs TIME

0 543-18-28

TX_EN = HIGH

TX_EN = HIGH

Start VRAMP approx 18usprior to useful part of burst

VRAMP

End VRAMP approx 12usbefore end of guard period

TX_EN = LOW

Raised cosine foroptimum spectral

efficiency

t

V

12µs

VBATT

BS



The change in the power ramping profile couldpossible conflict with the timing of the PA. Since thesignals like TX_EN are usually used to improve theisolation, it can be quite close to the VRAMP rampingsignal. If one of the control signals for instancecontrolling the ASM conflicts with the VRAMP signal, itusually results in a very poor switching spectrumperformance. In order to verify this, all the controlsignals for ASM, TX_EN, BS, etc. should becompared with the VRAMP profile using anoscilloscope. The timing can affect the switchingspectrum and the isolation. In Figure 7 and Figure 8the yellow line [1] is the VRAMP signal and the blueline [2] is TX_EN and the figures shows an exampleof how logic signals should be kept clear of the powerramping signal VRAMP.

2. POWER RAMPINGSince different PAMs have different controlcharacteristics, it is necessary to optimize the power

Figure 7: Close in of the Timing With a ProperDistance Between the Logic TX_EN Signal and the

Analog Power Ramping Signal VRAMP

Figure 9: Rising Edge of a Smooth Power RampingProfile Example Resulting in Good Switching

Spectrum

Figure 10: Falling Edge of a Smooth Power RampingProfile Example Resulting in Good Switching

Spectrum

Figure 8: Total Timing Period of TX_EN & VRAMP Witha Proper Distance Between the Logic TX_EN Signal

and the Analog Power Ramping Signal VRAMP

ramping with regard to switching spectrum whendeveloping a new platform. This is usually not acomplicated task, and can be done manually in afew hours. The power ramping affects switchingspectrum, and have to meet the Power TimeTemplate specified by ETSI. Generally, the rampprofile should be as close as possible to a raisedcosine waveform. In Figures 9 and 10 is an exampleof a smooth shaped power ramping profile resultingin good switching spectrum performance, see Figure11. The example is based on measurement resultsfrom a radio demo platform based on an ANADIGICSPAM and a standard tranceiver. ANADIGICSbaseband emulator provides the baseband signalsfor this platform.


7


Figure 11: Corresponding Switching SpectrumResult from the Total Power Ramping Profile

Shown in Figures 9 and 10

3. OUTPUT MATCHING OF THE PAMDifferent PAMs will have different load contours. Thismeans that they, in order to function at optimumperformance, need to have the output matchingcircuitry tuned. The way to do this is by using theload contours provided by ANADIGICS and a networkanalyzer and then tune the matching network on thePA output toward the desired performance. Theoptimum matching network will usually be acompromise between output power, currentconsumption, and conducted harmonics. In mostcases, 50 Ω is the best choice. In extreme cases,the switching spectrum can be affected if a poormatching solution is selected. This case is causedby the poor matching solution resulting in limitingthe output power to the point of conflict with the ETSIspecifications and forces the PAM close tosaturation.

WCDMA MODE RECOMMENDATIONIn order to maximize performance the ANADIGICSHELPTM WCDMA Bias Control functionality shouldbe used, which enables the WCDMA PA to operatein Low and High Bias Modes thereby optimizingcurrent consumption. Applying a logic level at VEN

pin 3 or VMODE pin 2 corresponding to the desiredPA Bias control mode controls this feature. Operationin the High Bias Mode allows the PA to exceed thesystem performance requirements at output powerlevels from +16 dBm to +28.5 dBm. For an outputpower less than +16 dBm, the Low Bias Mode shouldbe used to minimize quiescent current whilemaintaining system performance. Setting the VEN

logic high (+2.4V) and logic low (0 V) at the VMODE pinplaces the PA in High Bias Mode, and a logic high

(+2.4 V) at the VMODE pin places the PA in Low BiasMode. Applying a logic low (0 V) to both the VEN andVMODE pins places the amplifier in shutdown(standby) mode. The Bias-mode switching ofHELPTM can also be used with a DC-to-DC convertercontrolling the VCC_WCDMA pin 21 to achieve furtherefficiencies at power levels under 7 dBm, thoughusing HELPTM alone offers the best balance ofimproved performance, efficient use of board space,and low bill of materials cost.

EVALUATION BOARDThe evaluation board is a multilayer board usingGETEK substrate, which is similar to FR4, but has amore controlled dielectric constant. The boardthickness is 1.57 mm. All the routing is on the toplayer (1) of a 4 layer board with a distance of 0.36mm to the ground plane, which is on layer 2. All RFrouting has been sized to present a 50 Ω impedance.



Figure 13: Evaluation Board Structure

Figure 12: Evaluation Board Layout


9


Figure 14: Pinout (X- Ray View)

Table 1: Pin Description

CEXT2

1 21

2

3

4

5 17

20

19

18

6

7

8

9

10

16

15

14

13

1211

22 VCC_WCDMA

VBATT

GND

GND

GND

CEXT3

VCC_GSM

VMODE

VEN

BS

TX_EN

CEXT1

VRAMP

GSM_IN GSM_OUT

DCS/PCS_OUTDCS/PCS_IN

WCDMA_IN

WCDMA_OUT

GND

GNDGND

NIP EMAN NOITPIRCSED NIP EMAN NOITPIRCSED

1 NI_AMDCW tupnIFRAMDCW 21 TUO_MSG tuptuOFR009/058MSG

2 V EDOMlortnoCedoMAMDCW

egatloV 31 DNG dnuorG

3 V NE nwodtuhSAMDCW 41 DNG dnuorG

4 NI_SCP/SCD tupnIFRSCP/SCD 51 C 3TXE ssapyB

5 SB tupnIcigoLtceleSdnaB 61 DNG dnuorG

6 TX NE_ tupnIcigoLelbanEXT 71 DNG dnuorG

7 V TTAB ylppuSyrettaB 81 TUO_SCP/SCD tuptuOFRSCP/SCD

8 C 1TXE ssapyB 91 DNG dnuorG

9 V PMAR

otdesulangisgolanAtuptuoMSGehtlortnoc

rewop02 TUO_AMDCW tuptuOFRAMDCW

01 NI_MSG tupnIFR009/058MSG 12 V AMDCW_CC egatloVylppuSAMDCW

11 V MSG_CC

V CC MSGroftnioptset.tcennoctonoD.notces

.dnuorgtonoD22 C 2TXE ssapyB



PACKAGE OUTLINE

Figure 16: Package Outline - 22 Pin 6 mm x 8 mm x 1 mm Surface Mount Package


11


Figure 17: Recommended PCB Metal



Figure 18: Recommended PCB Solder Mask


13


Figure 19: Recommended Stencil Aperture



NOTES


15


NOTES

WARNINGANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICSproduct in any such application without written consent is prohibited.

IMPORTANT NOTICE

ANADIGICS, Inc.141 Mount Bethel RoadWarren, New Jersey 07059, U.S.A.Tel: +1 (908) 668-5000Fax: +1 (908) 668-5132

URL: http://www.anadigics.comE-mail: [email protected]

ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time withoutnotice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets aresubject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and areassumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urgescustomers to verify that the information they are using is current before placing orders.


16


Documents

WCDMA/GSM/GPRS/Polar EDGE Power Amplifier …application-notes.digchip.com/057/57-40026.pdf05/2006 Application Note WCDMA/GSM/GPRS/Polar EDGE Power Amplifier Module with Integrated