VTS 2012: Zhao-Agrawal1 Net Diagnosis using Stuck-at and Transition Fault Models Lixing Zhao* Vishwani D. Agrawal Department of Electrical and Computer

VTS 2012: Zhao-Agrawal 1

Net Diagnosis using Stuck-at and Transition Fault Models

Lixing Zhao*Lixing Zhao*Vishwani D. AgrawalVishwani D. Agrawal

Department of Electrical and Computer EngineeringAuburn University, AL 36849 USA

* Presently with FutureWei Technologies, Inc., Santa Clara, CA 95054 USA

April 25, 2012

2

Outline

MotivationBackgroundProblem StatementDiagnosis Method

Fault FilteringFault RankingNet Ranking

ConclusionReferences

VTS 2012: Zhao-AgrawalApril 25, 2012


Motivation

Fault diagnosis can bring the yield up in manufacturing rounds by identifying the possible causes of defects in earlier tape-outs.Net fault diagnosis is an important area of fault diagnosis. Because of the large routing area of modern VLSI devices, the routing interconnection nets are more vulnerable to certain defects.

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Background

• Net defects sometimes have certain complicated characteristics.

• Simply using traditional fault models cannot solve the net fault diagnosis problem well.

• Using complicated fault models to match the behavior of a net fault is time consuming, not supported by tools, and not suitable for practical use.

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Problem Statement

• Find an effective method for solving the net-fault-diagnosis problem using available software tools.

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Diagnostic Test PatternsWe use test patterns, which have high diagnostic coverage for single stuck-at faults and single transition faults.

•Y. Zhang and V. D. Agrawal, “A Dianostic Test Generation System,” Proc. International Test Conf., 2010, Paper No. 12.3.•Y. Zhang and V. D. Agrawal, “Reduced Complexity Test Generation Algorithms for Transition Fault Diagnosis,” Proc. International Conf. on Computer Design, 2011, pp. 96-101.

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Diagnostic Procedure• Start with collapsed set of faults.

• First Filter (Simple): Test pattern matching.

• Second Filter: Primary output (PO) matching.

• Discard faults below count thresholds.

• Rank order remaining faults.

• Map top suspects onto nets.

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A: patterns detectingfault F

B: patternsfailing CUTon ATE

CCount (F) = |C|/|A|

Count for Second Threshold• Set a high threshold for first count; few faults left.

• Compute a second PO-specific count


D: C ×POpairs forfault F

C ×POpairs for CUTon ATE

E: HitpatternsCount (F) = |E|/|D|

Training for Count Thresholds

• Set a high threshold for the first filter.

• Generate sample circuits by injecting some (e.g., four) randomly chosen faults.

• Select second threshold so 90% injected faults survive the two filters.

• If necessary, lower the first threshold.



Filtering ResultsCircuit # of Total

FaultsReduction

RateSurvival

Rate

C432 524 0.77 0.975

C880 942 0.97 0.96

C1355 1574 0.75 0.97

C1908 1879 0.85 0.95

C2670 2747 0.925 0.97

C3540 3428 0.95 0.965

C6288 7744 0.933 0.96

C7552 7419 0.992 0.96

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Ranking SuspectsRank filtered fault candidates in a list of key suspects.Only patterns failing on ATE are simulated.A structure called erroneous PO-tree (EPO-tree) is

constructed for all failing patterns. Faults are ranked at each PO separately by their total

number of appearances in EPO-trees.

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Failing pattern 1

Diagnostic Experiments• ISCAS’85 circuits.• 200 faulty circuit samples: 1-4 randomly selected faults

injected.• Diagnosis:

– Diagnosability (Dia): fraction of injected faults found

– First hit rank (FHR): Position of an injected fault in the ranked suspect list

– Resolution (Res): Ratio of number of diagnosed faults to injected faults


Experimental Results


Ciruit Our Work (1 Stuck-at) Wang et al. (1 stuck-at)

Dia FHR RES CPU s Dia FHR Res CPU s

c2670 1.0 1.0 1.0 6.4 1.0 1.27 1.3 0.01

c3540 1.0 1.0 1.0 0.5 1.0 1.2 1.5 0.01

c6288 1.0 1.0 1.0 0.6 1.0 1.1 1.3 0.01

c7552 1.0 1.0 1.0 1.5 1.0 1.15 1.6 0.01

Z. Wang, M. Marek-Sadowska and J. Rajski, "Analysis and Methodology for Multiple-Fault Diagnosis,” IEEE Tran on CAD of Integrated Circuits and Systems, March 2006, vol. 25, pp. 558-576.

Circuit

Our Work (2 Stuck-at) Wang et al. (2 stuck-at)


c2670 0.97 1.0 2.0 8 0.97 1.35 2.0 0.05

c3540 0.95 1.0 1.0 0.6 0.95 1.2 1.7 0.06

c6288 0.99 1.0 2.0 1 0.97 1.28 2.0 0.2

c7552 0.93 1.0 2.0 1.7 0.925 1.25 2.0 0.2

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Circuit Our Work (3 Stuck-at) Wang et al. (3 stuck-at)


c2670 0.94 1.0 2.0 13 0.925 1.35 2.6 0.1

c3540 0.94 1.0 2.0 0.7 0.92 1.15 2.4 0.1

c6288 0.95 1.0 2.0 2.7 0.93 1.15 2.5 0.5

c7552 0.90 1.04 2.0 2.9 0.92 1.2 2.3 0.25

Circuit Our Work (4 stuck-at) Wang et al. (4 stuck-at)


c2670 0.89 1.06 2.0 17 0.92 1.3 2.6 0.2

c3540 0.91 1.0 2.0 1.8 0.89 1.25 2.5 0.2

c6288 0.92 1.02 2.0 5.7 0.82 1.15 2.8 0.8

c7552 0.88 1.1 2.0 3.2 0.91 1.2 2.4 0.5

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Net Ranking

• Each ranked fault is uncollapsed and all equivalent faults are given the same rank as the parent fault.

• Count for a net is the highest rank of any fault on it.

• Nets are ranked in order of descending count.



Circuit One Net Fault (Stuck-at) Two Net Faults (Stuck-at)

Dia FHR Res CPU s Dia FHR Res CPU s

c432 1.0 1.1 2.0 0.1 0.98 1.2 3.0 0.2

c880 1.0 1.1 2.0 0.1 1.0 1.1 3.0 0.1

c1355 0.98 2.0 3.0 1.0 0.75 2.6 5.0 16

c1908 0.92 1.4 3.0 7.5 0.86 1.3 3.0 13

c2670 0.98 1.4 3.0 7.4 0.95 1.14 4.0 12

c3540 0.98 1.04 3.0 0.5 0.96 1.1 3.0 0.7

c6288 0.98 1.1 3.0 3 0.9 1.06 3.0 4

c7552 0.96 1.1 3.0 3 0.9 1.2 3.0 11

Experimental Results

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Circuit One Net Fault (Transition) Two Net Faults (Transition)

Dia FHR Res CPU s Dia FHR Res CPU s

c432 1.0 1.05 2.0 0.48 0.9 1.2 3.0 0.7

c880 0.9 1.2 2.0 0.8 0.8 1.3 3.0 2.3

c1355 1.0 1.0 1.0 0.9 0.86 1.3 3.0 13

c1908 0.96 1.2 2.0 7.2 0.93 1.4 3.0 35

c2670 1.0 1.16 2.0 0.9 0.97 1.06 2.0 4.6

c3540 0.98 1.2 2.0 1.7 0.95 1.1 2.0 2.3

c6288 1.0 1.08 2.0 2.8 0.92 1.3 2.0 2.8

c7552 0.98 1.3 2.0 7.5 0.96 1.08 2.0 13.1

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Conclusion Net diagnosis is a practical way of identifying possible sites of

defects. Use of fault models facilitates test generation, fault grading and

diagnostic analysis. Using a variety of fault models may have benefits in diagnosis. Tests with higher diagnostic coverage may be beneficial. Basic idea is to gradually narrow down the list of suspects using

single fault analysis tools: Initial filtering only uses collapsed fault list and all test patterns. Next filtering uses failing PO information, filtered faults and failed

patterns. Suspect ranking uses failed patterns, filtered fault list and PO matching. Suspected net ranking is based upon the ranked faults and their

equivalent fault sets.

April 25, 2012


References1. Y. Zhang and V. D. Agrawal, “A Dianostic Test Generation System,” Proc.

International Test Conf., 2010, Paper No. 12.3.

2. Y. Zhang and V. D. Agrawal, “Reduced Complexity Test Generation Algorithms for Transition Fault Diagnosis,” Proc. International Conf. on Computer Design, 2011, pp. 96-101.

3. N. Sridhar and M. S. Hsiao, “On Efficient Error Diagnosis of Digital Circuits,” Proc. International Test Conference, 2001, pp. 678-687.

4. S. M. Reddy, H. Tang, I. Pomeranz, S. Kajihara and K. Kinoshita, “On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout,” Proc. International Test Conf. , 2002, pp. 83-87.

5. Z. Wang, M. Sadowska, and J. Rajski, “Analysis and Methodology for Multiple-fault Diagnosis,” IEEE Tran on CAD of Integrated Circuits and Systems, vol. 25, pp. 558-576, Mar. 2006

6. S. Venkataraman and S. B. Drummonds, “Poirot: Applications of a Logic Fault Diagnosis Tool,” IEEE Design and Test of Computers, Jan. 2001, pp. 19-29.

7. J. Segura and C. F. Hawkins, CMOS Electronics: How It Works, How It Fails,”Wiley-

IEEE, Apr. 2004.

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Thank You . . .

April 25, 2012


Questions

April 25, 2012

Documents

VTS 2012: Zhao-Agrawal1 Net Diagnosis using Stuck-at and Transition Fault Models Lixing Zhao* Vishwani D. Agrawal Department of Electrical and Computer