VLSI_LAB10

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AMERICAN INTERNATIONAL UNIVERSITY-BANGLADESHFACULTY OF ENGINEERING

EEE 4217: VLSI CIRCUIT DESIGN

Experiment 10: Layout design of a 4x4 bit Static RAM

Objectives:

• To understand the operation of 6-transistor static RAM cell.

• To check the layout of a 6-transistor static RAM cell.

• To simulate the 1-bit RAM cell layout.

• To build a 4x4 bit RAM array.

• To build a complete 4x4 bit RAM chip including I/O pads.

• To generate a CIF file of the RAM chip.

RAM Memory

The schematic diagram of the static memory cell used in High Capacity Static RAMs isgiven in Figure 1. The circuit consists of 2 cross-coupled inverters and two nMOS passtransistors. The cell has been designed to be duplicated in X and Y in order to create a

large array of cells. Usual sizes for Megabit SRAM memories are 256 x 256 cells or higher.The selection line Sel concerns all the cells of one row. The lines Data and nData concernall the cells of one column.

The RAM layout is given in Figure 2. Click on File -> Read -> RAM.MSK to read it fromC:\MICROWIND directory. The Data and nData signals are made with metal and crossthe cell from top to bottom. This allows easy matrix-style duplication of the RAM cell.

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WRITE CYCLE. Values 1 or 0 must be placed on Data, and the data inverted value on

nData. Then the line Sel goes to 1. The two-inverter latch takes the Data value. When

returning to 0, the RAM is in a memory state.

READ CYCLE. In order to read the cell, the line Sel must be asserted. The RAM value

propagates to Data, and its inverted value propagates to nData.

SIMULATION. The simulation parameters correspond to the write cycle in the RAM. The

simulation steps are as follows :

Mem reaches 1, nMem 0 (unpredicatable value).

Data gets to value 1 and nData to value 0.

Sel is asserted. The memory cell reaches stays at 1.

Data gets to a value of 0 and nData gets to a value of 1.

Sel is still asserted. The memory cell gets 0.

. Sel is inactive. The RAM is in a memory state.Simulate the RAM cell layout and check the results with that shown in Fig. 3. PRINT.

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Complete RAM 4x4 Bit

You can duplicate the RAM cell into a 4x4 bit array using the command Edit -> Duplicate

XY. Select the whole RAM cell and a new window appears. Enter the value « 4 » for X and

« 4 » for Y into the menu. Click on « Generate ». The result is shown below. PRINT.

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The row decoder is based on the schematic diagram of Fig. 5. One line is asserted while allthe other lines are at zero. In this circuit one line was picked out from a choice of four lines. Using AND gates would be an easy solution, but in order to save the inverter, we

chose NOR gates with inverted inputs. The layout of the row decoder is given in Figure 6.Click on File -> Read -> RamLineSelect.MSK to read it from C:\MICROWIND directory.

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Simulate the layout of row selection circuit and check the results with that shown in Fig. 7.PRINT.

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The NOR gate height should be adjusted to that of the RAM cell height. When making the

final assembly between blocks, the command Edit -> Move Area is very important. Thiscommand helps to move a selected block with a lambda step.

The column decoder is based on the same principles as those of the row decoder. Themajor modification is that the data flows both ways, that is firstly from the cell to the readcircuit (Read cycle) and secondly from the write circuit to the cell (Write cycle). Fig. 8

proposes an architecture for this.

The n-channel MOS device is used as a switch controlled by the column selection. Whenthe n-channel MOS is on and Write is asserted, the data issued from DataIn is amplified

by the buffer, flows from the bottom to the top and reaches the memory. If Write is off, the3-state inverter is in high impedance, which allows one to read the information.

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The final layout of the RAM 4x4 is proposed in Fig. 9. Click on File -> Read ->

Ram44.MSK to read it from C:\MICROWIND directory. The simulation shown in Fig 10 proposes the read and write cycles at a specific RAM cell address. Perform the simulation

and PRINT results.

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The simulation of Fig. 10 can be described as follows. A [00] fixed line selection selects theupper line, that way « sel0 » is asserted while all others are at 0. The memory cells mem00

and mem01 do not reach the same initial state : mem00 gets to 0 and mem01 is at 1. WhenDataIn is at zero, writing a zero has no effect on Mem00. But when the column selectionchanges, DataIn=0 is copied to Mem01.

When DataIn rises to 1 (t=10ns), and when write is 1, the memory cells change from 0 to 1.It is interesting to point out that the memory cell fights against the logic value before

surrending and changing its internal state.

Complete RAM ChipClick on the chip library icon and click on Pads. The window shown in Fig. 11appears. Select the Pads Tab and the Pad ring option. A pad ring with 3 pads in X and 3 pads in Y is generated by a click on Generate Pad. In that case, a set of pads is added to

your circuit. The VSS pad is situated at the bottom, and the VDD pad at the top with theassociated power rings.

Figure 12 displays an example of circuit with its input-output pads and interconnects. Thechip contains a pad ring of 28 input/outputs (CHIP.MSK file). You open this example chip by clicking File -> Read -> Chip.MSK from C:\MICROWIND directory. Magnify the

different to vuew how connenctions are made to the Pads with metal lines. Use the sametechnique (magnify and draw boxes) to connect various signal lines in your RAM layoutto the Pads. Don’t violate design rules. Connect all the Data, Address and Control (Write)lines of your RAM layout to the Pads and perform DRC. When clean, save and print the

complete chip layout.

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Generate CIF fileMICROWIND converts the MSK layout into CIF using a specific interface. The CIF file can be exported to various industrial software. The screen is shown below. The right table givesthe correspondence between MICROWIND layers and CIF layers, the number of boxes in the

layout and the corresponding over-etch. The over-etch is used to modify the final size of the

CIF boxes in order to fit the exact design rules.

Click on « Convert to CIF » to start conversion. Some parts of the result appear in the left

window.

Demonstration and reportYou must demonstrate your complete layout and simulation results to the lecturer during the

practical class. You should also print the layout and simulation results, and get these signed by the lecturer during the class. You should submit these in the next class along with a cover

sheet (clearly showing your ID number and name, course number and name, number and

name of the practical assignment) and your comments on various aspects of thedesign/experiment for marking.

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VLSI_LAB10