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S.NO CODE TITLE DOMAIN YEAR
1 VLSI-01 Area-Delay-Power Efficient Fixed-Point LMSAdaptive
Filter With Low Adaptation-Delay
Area + Power +
Delay Efficient
2014
2 VLSI-02 Fast Sign Detection Algorithm for the RNSModuli Set
{2
n+1 1, 2n 1, 2n}
Area + Power +
Delay Efficient
2014
3 VLSI-03 Efficient Integer DCT Architectures for HEVC Area +
PowerEfficient
2014
4 VLSI-04 AreaDelayPower Efficient Carry-Select Adder Area +
PowerEfficient
2014
5 VLSI-05 Design of Efficient Binary Comparatorsin Quantum-Dot
Cellular Automata
Area + Power
Efficient
2014
6 VLSI-06 Reverse Converter Design via Parallel-PrefixAdders:
Novel Components, Methodology,
and Implementations
Delay + Power
Efficient
2014
7 VLSI-07 Area-Delay Efficient Binary Adders in QCA Area +
DelayEfficient
2014
8 VLSI-08 Low-Complexity Low-Latency Architecture forMatching of
Data Encoded With Hard Systematic
Error-Correcting Codes
Area + Delay
Efficient
2014
9 VLSI-09 Parallel AES Encryption Engines for Many-CoreProcessor
Arrays
Area + Delay
Efficient
2013
10 VLSI-10 Multifunction Residue Architectures
forCryptography
Area Efficient 2014
11 VLSI-11 Low-Complexity Multiplier for GF(2m) Based onAll-One
Polynomials
Area Efficient 2013
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12 VLSI-12 Split Radix Algorithm for Length 6mDFT Area Efficient
2013
13 VLSI-13 Flexible Integer DCT Architectures for HEVC Area
Efficient 201314 VLSI-14 Area-Efficient Parallel FIR Digital
Filter
Structures for Symmetric Convolutions Based on
Fast FIR Algorithm
Area Efficient 2012
15 VLSI-15 Low-Power, High-Throughput, and Low-AreaAdaptive FIR
Filter Based on Distributed
Arithmetic
Power
Consumption
2013
16 VLSI-16 A Novel Modulo Adder for 2n-2 - 1ResidueNumber
System
Power
Consumption
2013
17 VLSI-17 Low-Power and Area-Efficient Carry Select Adder
PowerConsumption
2012
18 VLSI-18 Measurement and Evaluation of Power AnalysisAttacks
on Asynchronous S-Box
Power
Consumption
2012
19 VLSI-19 A Low-Power Single-Phase Clock MultibandFlexible
Divider
Power
Consumption
2012
20 VLSI-20 Aging-Aware Reliable Multiplier Design WithAdaptive
Hold Logic
High Speed 2014
21 VLSI-21 Critical-Path Analysis and
Low-ComplexityImplementation of the LMS Adaptive Algorithm
High Speed 2014
22 VLSI-22 Eliminating Synchronization Latency UsingSequenced
Latching
High Speed 2014
23 VLSI-23 Design of Digit-Serial FIR Filters:
Algorithms,Architectures, and a CAD Tool
High Speed 2013
24 VLSI-24 Design of an Error Detection and Data
RecoveryArchitecture for Motion Estimation Testing
Applications
High Speed 2012
25 VLSI-25 Gate Mapping Automation for Asynchronous Testing
2014
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NULL Convention Logic Circuits
26 VLSI-26 Design of Testable Reversible Sequential Circuits
Testing 201327 VLSI-27 Test Patterns of Multiple SIC Vectors:
Theory
and Application in BIST Schemes
Testing 2013
28 VLSI-28 Period Extension and Randomness EnhancementUsing
High-Throughput Reseeding-Mixing PRNG
Testing 2012
29 VLSI-29 High-Throughput Multistandard Transform
CoreSupporting MPEG/H.264/VC-1 Using Common
Sharing Distributed Arithmetic
VLSI+
MATLAB
2014
30 VLSI-30 Improved 8-Point Approximate DCT for Imageand Video
Compression Requiring Only 14
Additions
VLSI+
MATLAB
2014
31 VLSI-31 Efficient FPGA and ASIC Realizations of DA-Based
Reconfigurable FIR Digital Filter
VLSI+
MATLAB
2014
32 VLSI-32 Multicarrier Systems Based on Multistage LayeredIFFT
Structure
VLSI+
MATLAB
2013
33 VLSI-33 Improvement of the Security of ZigBee by a NewChaotic
Algorithm
VLSI+
MATLAB
2013
34 VLSI-34 CORDIC Based Fast Radix-2 DCT Algorithm
VLSI+MATLAB
2013
