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S. Go alan Amrita Viswa Vid a eetam 04.05.05

VLSI Fabrication

Contacts and Metallization04.05.05

Amrita Vishwa Vidyapeetam


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Deep Trench Isolation

Used for trench capacitors

Rounded corners reduce

stress and hence lessdefects


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Shallow Trench Isolation (STI)

Less complicated than DTI. Advent of CMP makes this feasible


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Metallization

Wire-to substrate capacitance and wire-to-wire capacitance

As wiring density increases, wires get narrower wire to wire

capacitance increases Wire-to-substrate capacitance does not decrease proportional to width

due to fringing capacitance (capacitance at the edges of metal)

Having low resistivity of metal line is very important for speed

The time delay (rise time) due to

global interconnects is:

where Kox is the dielectric

constant of the oxide, KI accounts

for fringing fields and is the

resistivity of the interconnect line.


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Multilevel Metallization

As device density on wafer increases increase in interconnects

By reducing pitch of interconnect, cross talk noise between adjacent

lines is higher increasing the number of interconnect layers is

the solution

Interconnect and gate time delay

versus chip area

As interconnect levels increase, the

chip speed is heavily dependent oninterconnect delay

Al metal lines have been used due to

low resistivity.

Going to Copper reduces delay evenfurther

micron


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Metallization

Increased wiring levels cause speed to be dependent on interconnects


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Contacts and Vias

Vias: Tungsten (W) plugs used dueto its low resistivity and its ability to

fill high aspect ratio holes

W deposited by CVD

TiN used as barrier layerbetween

metal, vias, and dielectrics

gate

drain

Earlier structures used Al contacts Good contact between S/D/Gate and

metal required highly doped silicon

necessary for low contact resistance

Use of silicides (TiSi2, NiSi2) improvescontact resistance


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Metallization

Aluminum was most popular choice till late 90s

Has low resistivity (2.7ohm-cm)

Good adhesion to SiO2

Simple deposition (PVD usually used)

Problems with Aluminum

Low melting point (660C) prevents any post-metal high

temperature treatment

Junction Spiking: Al diffuses fast through Si and incase of a

shallow junction, causes spiking or shorting between S/D and

substrate

Electro migration: High current densities through Al lines lead to

movement of large number of atoms

As a result voids are created in some places and short circuit in

other places


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Al Metallization

Junction Spiking

Diffusion of Al through

Si

Prevented by using abarrier layer

from Sze, 2nd, p. 410.

~5m

Electromigration

Adding a small

amount of Cu or use ofCu interconnects

reduce

electromigration


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Copper (Cu) for Metal lines

Advantages with Copper (Cu) Lower resistivity than Al (1.7) which leads to

reduction in delays

Higher melting point (~1200C) than Al

Higher electro migration resistance thancopper

Use of Cu was first announced in 97 by IBM

Currently Cu is most common in industry

Disadvantages / Challenges

Highly reactive or corrosive Difficult to etch

Poor adhesion to dielectrics

High diffusivity in Si (a barrier layer is

required)

L. Geppert, Technology 1998, Analysis and Forcast:

Solid State, in IEEE Spectrum, vol. 35, 1998, pp. 23-28.


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Cu metal: Damascene Process

ILD inter layer dielectric

Cu etched by CMP chemical mechanical polish Cu deposited by electroplating

1.

2.

3.

5.

4.

6.


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Cu metal: Dual Damascene Process

ILD inter layer dielectric; CMP chemical mechanical polish

1. First deposit two layers of dielectric

2. Patternand etch

holes in 2nd

ILD layer

3. Pattern

and etch

holes in 1st

ILD

4. Fill copperin both holes

5. CMP Cuto stop on

ILD


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Inter Layer Dielectrics

Dielectrics electrically and physically separateinterconnects from each other and from active regions.

Two types:

First level dielectric Inter metal or inter-layer dielectric (ILD)

First level dielectric is usually SiO2 doped with P or B or

both (2-8 wt. %) for good step coverage PSG: phospho-silicate glass

BPSG: boro-phospho-silicate glass

Inter-metal dielectrics also made primarily of SiO2 today,but tending towards low-dielectric constant (low-K)

materials

CMP needed for getting planar structure

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