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8/17/2019 VLSI Design Tools
1/2
VLSI Design Tools
Design Flow Design Details Tools Company
Code Editors/DocEditors
Vi/Vim GNU
Emacs GNUFrameMake Adobe
!!ice Microso!t
FrontEnd Sim"lation VCS S#no$s#s
NC%Verilog&IUS' Cadence
Verilog (L Cadence
ModelSim Mentor
Deb"g Deb"ss# S$ringSo!t/No)as
Verdi S$ringSo!t/No)asSim)ision Cadence
DVE S#no$s#s
Lint C*ecking +AL Cadence
S$#Glass Atrenta
,%in C*ecklist Arc*er
nLint S$ringSo!t/No)as
E-"i)alence C*ecking LEC Cadence/Ver$le.
Con!ormal ASIC Cadence
SLV Cadence
Co)erage +DLScore S"mmit
ICC Cadence
In!initeStream Cacence
VCS Co)erage Metrics S#no$s#s
Formal Veri!ication Fromalit# S#no$s#s
lackTie Cadence/Ver$le.
IFV Cadence
SV Veri!ication $en Vera S#no$s#s
S$ecman Elite Verisit#
VCS/S#stemVerilog S#no$s#s
Incisi)e Cadence
0"esta Mentor
8/17/2019 VLSI Design Tools
2/2
Design Flow Design Details Tools Company
Assertion asedVeri!ication
SVA
VL
CV
CDC ,%In CDC Mentor
EC nEC S$ringSo!t/No)as
Lo1 2o1er Anal#sis 2o1er Com$iler S#no$s#s
2o1er T*eater Se-"ence
Em"lation 2alladi"m Cadence
FrontEnd%ackEnd S#nt*esis Design Com$iler S#no$s#s
3TL Com$iler Cadence
2*#sical Com$iler S#no$s#s
STA 2rimeTime S#no$s#s
DFT DFT Com$iler S#no$s#s
SD Com$iler S#no$s#s
DFT MA( S#no$s#s
TetraMA( AT2G S#no$s#s
Enco"nter Cadence
Silicon Ensemble Cadence
IC Com$iler S#no$s#s
A$$ollo
Magma Magma
LVS/D3C Drac"la Cadence
+erc"les S#no$s#s
Calibre Mentor Gra$*ics