VLSI/FPGAVLSI/FPGA

Design and Test Flow with Design and Test Flow with

Mentor Graphics CAD ToolsMentor Graphics CAD Tools

Victor P. NelsonVictor P. Nelson

ASIC Design FlowASIC Design FlowBehavioral

ModelVHDL/Verilog

Gate-LevelNetlist

Transistor-LevelNetlist

PhysicalLayout

Map/Place/Route

DFT/BIST& ATPG

VerifyFunction

VerifyFunction

Verify Function& Timing

Verify Timing

DRC & LVSVerification

IC Mask Data/FPGA Configuration File

Standard Cell IC & FPGA/CPLD

Synthesis

Test vectors Full-custom IC

Physical Design Physical Design -- FPGAFPGA

Map to FPGA LUTs, FFs, IOBs

Place & Route

Component-Level Netlist

Configuration File

Generate Programming

Data

Xilinx “ISE”Altera “Max Plus 2”

FPGA/PLD Technology

FilesUser-SpecifiedConstraints

Simulation Model

Generate Timing Model

Mentor Graphics CAD Tool SuitesMentor Graphics CAD Tool Suites

�� IC/SoC design flowIC/SoC design flow11

�� DFT/BIST/ATPG design flowDFT/BIST/ATPG design flow11

�� FPGA design flowFPGA design flow2,32,3

�� PCB design flowPCB design flow22

�� Digital/analog/mixedDigital/analog/mixed--signal modeling & simulationsignal modeling & simulation1,21,2

�� ASIC/FPGA synthesisASIC/FPGA synthesis1,21,2

�� VendorVendor--provided (Xilinx,Altera,etc.) back end toolsprovided (Xilinx,Altera,etc.) back end tools22

1.1. UserUser--setup selection: setup selection: eda/mentor/ICFlow2006.1eda/mentor/ICFlow2006.1

2.2. UserUser--setup selection: setup selection: eda/mentor/EN2002.3eda/mentor/EN2002.3

3.3. UserUser--setup selection:setup selection: eda/mentor/FPGAeda/mentor/FPGA

Mentor Graphics CAD Tools Mentor Graphics CAD Tools (select (select ““eda/mentoreda/mentor”” in userin user--setup on the Sun network*)setup on the Sun network*)

�� ICFlow2006.1ICFlow2006.1–– For custom & standard cell IC designsFor custom & standard cell IC designs

–– IC flow toolsIC flow tools (Design Architect(Design Architect--IC, IC Station, Calibre)IC, IC Station, Calibre)

–– Digital/analog/mixed simulation Digital/analog/mixed simulation (Modelsim,ADVance MS,Eldo,MachTA)(Modelsim,ADVance MS,Eldo,MachTA)

–– HDL SynthesisHDL Synthesis (Leonardo)(Leonardo)

–– ATPG/DFT/BIST toolsATPG/DFT/BIST tools (DFT Advisor, Flextest, Fastscan)(DFT Advisor, Flextest, Fastscan)

–– Limited access to Quicksim II Limited access to Quicksim II (some technologies)(some technologies)

�� EN2002u3 EN2002u3 –– For FPGA For FPGA ““front endfront end”” design & printed circuit boardsdesign & printed circuit boards

–– Design Architect, Quicksim II, Quicksim Pro Design Architect, Quicksim II, Quicksim Pro (Schematic/Simulation)(Schematic/Simulation)

–– ModelSim & Leonardo ModelSim & Leonardo (HDL Simulation/Synthesis)(HDL Simulation/Synthesis)

–– Xilinx ISE & Altera Xilinx ISE & Altera ““QuartusQuartus”” tools tools (Back end design)(Back end design)

�� FPGAFPGA (FPGA Advantage, Modelsim, Leonardo)(FPGA Advantage, Modelsim, Leonardo)

*Only one of the above three groups may be selected at a time*Only one of the above three groups may be selected at a time

Mentor Graphics ASIC Design Kit (ADK)Mentor Graphics ASIC Design Kit (ADK)

�� Technology files & standard cell librariesTechnology files & standard cell libraries–– AMI: ami12, ami05 AMI: ami12, ami05 (1.2, 0.5 (1.2, 0.5 µµm)m)

–– TSMC: tsmc035, tsmc025, tsmc018 TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 (0.35, 0.25, 0.18 µµm)m)

�� IC flow & DFT tool support files:IC flow & DFT tool support files:–– Simulation Simulation

�� VHDL/Verilog/MixedVHDL/Verilog/Mixed--Signal modelsSignal models (Modelsim/ADVance MS)(Modelsim/ADVance MS)

�� Analog (SPICE) modelsAnalog (SPICE) models (Eldo/Accusim)(Eldo/Accusim)

�� PostPost--layout timing layout timing (Mach TA)(Mach TA)

�� Digital schematic Digital schematic ((Quicksim II, Quicksim Pro)Quicksim II, Quicksim Pro) (exc. tsmc025,tsmc018)(exc. tsmc025,tsmc018)

–– Synthesis to std. cells Synthesis to std. cells (LeonardoSpectrum)(LeonardoSpectrum)

–– Design for test & ATPG Design for test & ATPG (DFT Advisor, Flextest/Fastscan)(DFT Advisor, Flextest/Fastscan)

–– Schematic capture Schematic capture (Design Architect(Design Architect--IC)IC)

–– IC physical design (standard cell & custom) IC physical design (standard cell & custom)

�� Floorplan, place & route Floorplan, place & route (IC Station)(IC Station)

�� Design rule check, layout vs schematic, parameter extraction Design rule check, layout vs schematic, parameter extraction (Calibre)(Calibre)

Xilinx/Altera FPGA/CPLD DesignXilinx/Altera FPGA/CPLD Design

�� Technology files & libraries for frontTechnology files & libraries for front--end design with end design with

Mentor Graphics toolsMentor Graphics tools

–– Schematic symbols for Schematic symbols for Design ArchitectDesign Architect

–– Simulation models forSimulation models for Quicksim II, Quicksim ProQuicksim II, Quicksim Pro

–– Synthesis library for Synthesis library for LeonardoLeonardo

�� Vendor tools for backVendor tools for back--end design end design

(map, place, route, configure, timing)(map, place, route, configure, timing)

–– Xilinx Xilinx Integrated Software EnvironmentIntegrated Software Environment (ISE)(ISE)

�� Xilinx XST can synthesize the design from VHDL or Verilog (insteXilinx XST can synthesize the design from VHDL or Verilog (instead ad

of Leonardo)of Leonardo)

–– Altera Altera Quartus II & Max+Plus2Quartus II & Max+Plus2

Behavioral Design & VerificationBehavioral Design & Verification(mostly technology(mostly technology--independent)independent)

Create Behavioral/RTL HDL Model(s)

Simulate to VerifyFunctionality

Synthesize Gate-LevelCircuit

LeonardoSpectrum(digital)

ModelSim (digital)

VHDL-AMSVerilog-A

ADVance MS (analog/mixed signal)

VHDLVerilog

SystemC

Technology Libraries

Post-Layout Simulation,Technology-Specific Netlist

to Back-End Tools

ADVance MSADVance MSDigital, Analog, MixedDigital, Analog, Mixed--Signal SimulationSignal Simulation

ADVance MS

WorkingLibrary

Design_1Design_2

VITAL

IEEE 1164 ResourceLibraries

SimulationSetup

EZwaveor Xelga

InputStimuli

VHDL,Verilog,VHDL-AMS, Verilog-A,

SPICE Netlists

Eldo,Eldo RF ModelSim

View ResultsMach TAMach PA

Analog(SPICE) Digital

(VHDL,Verilog)

Mixed Signal(VHDL-AMS,Verilog-A)

SPICEmodels

Automated Synthesis with Automated Synthesis with

Leonardo SpectrumLeonardo Spectrum

Leonardo Spectrum(Level 3)

VHDL/Verilog Behavioral/RTL Models

FPGA

ASIC

TechnologySynthesis Libraries

Technology-SpecificNetlist

DesignConstraints

VHDL, Verilog, SDF,EDIF, XNF

Level 1 – FPGALevel 2 – FPGA + Timing

ADKAMI 0.5, 1.2TSMC 0.35, 0.25

Leonardo Leonardo –– ASIC Synthesis FlowASIC Synthesis Flow

Synthesis exampleSynthesis example

�� Load technology library: Load technology library:

tsmc035 (ASIC), or Xilinx Spartan2 (FPGA)tsmc035 (ASIC), or Xilinx Spartan2 (FPGA)

�� Load design file: Load design file: modulo7.vhdmodulo7.vhd

�� Specify constraints: Specify constraints: clock freq, delays, etc.clock freq, delays, etc.

�� Optimization: Optimization: effort, performance vs. areaeffort, performance vs. area

�� Write synthesized netlist output(s): Write synthesized netlist output(s):

–– modulo7_0.vhdmodulo7_0.vhd : VHDL netlist for ModelSim & DFT: VHDL netlist for ModelSim & DFT

–– modulo7.vmodulo7.v : Verilog netlist for import into DA: Verilog netlist for import into DA--ICIC

–– modulo7.sdfmodulo7.sdf : For ModelSim to study timing : For ModelSim to study timing

–– modulo7.edfmodulo7.edf : EDIF netlist for 3: EDIF netlist for 3rdrd party toolsparty tools

–– modulo7.xnfmodulo7.xnf : Xilinx netlist for Xilinx ISE: Xilinx netlist for Xilinx ISE

Behavioral model to be synthesizedBehavioral model to be synthesized

---- modulomodulo--7 counter with asynchronous reset and synchronous load/count7 counter with asynchronous reset and synchronous load/count

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_stlibrary ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;d.all;

entity modulo7 isentity modulo7 is

port( count,load,reset,clk: in std_logic;port( count,load,reset,clk: in std_logic;

I: in unsigned(2 downto 0); I: in unsigned(2 downto 0); ---- ““unsignedunsigned”” form of std_logic_vectorform of std_logic_vector

Q: out unsigned(2 downto 0)); Q: out unsigned(2 downto 0)); ---- defined in IEEE defined in IEEE ““numeric_stdnumeric_std”” packagepackage

end modulo7;end modulo7;

architecture Behave of modulo7 isarchitecture Behave of modulo7 is

signal Q_s: unsigned(2 downto 0);signal Q_s: unsigned(2 downto 0);

beginbegin

process (reset,clk) beginprocess (reset,clk) begin

if (reset='0') then Q_s <= "000";if (reset='0') then Q_s <= "000";

elsif (clk'event and (clk='1')) thenelsif (clk'event and (clk='1')) then

if (count = '1') and (Q_s = "110") then Q_s <= if (count = '1') and (Q_s = "110") then Q_s <= "000";"000";

elsif (count='1') then elsif (count='1') then Q_s <= Q_s + 1;Q_s <= Q_s + 1;

elsif (load='1') then elsif (load='1') then Q_s <= I;Q_s <= I;

end if;end if;

end if;end if;

end process;end process;

Q<=Q_s;Q<=Q_s;

end; end;

Synthesized netlist (1)Synthesized netlist (1)

---- Definition of modulo7Definition of modulo7

---- Thu Sep 21 10:48:09 2006Thu Sep 21 10:48:09 2006

---- LeonardoSpectrum Level 3, 2005a.82LeonardoSpectrum Level 3, 2005a.82

----

library IEEE;library IEEE;

use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_1164.all;

entity modulo7 isentity modulo7 is

port (port (

count : IN std_logic ;count : IN std_logic ;

load : IN std_logic ;load : IN std_logic ;

reset : IN std_logic ;reset : IN std_logic ;

clk : IN std_logic ;clk : IN std_logic ;

I : IN std_logic_vector (2 DOWNTO 0) ;I : IN std_logic_vector (2 DOWNTO 0) ;

Q : OUT std_logic_vector (2 DOWNTO 0)) ;Q : OUT std_logic_vector (2 DOWNTO 0)) ;

end modulo7 ;end modulo7 ;

Synthesized netlist (2)Synthesized netlist (2)

architecture Behave of modulo7 isarchitecture Behave of modulo7 issignal Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, NOT_reset, nx4, nxsignal Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, NOT_reset, nx4, nx14, nx22, 14, nx22, nx48, nx60, nx169, nx179, nx189, nx202, nx204, nx208, nx21nx48, nx60, nx169, nx179, nx189, nx202, nx204, nx208, nx212, nx214, 2, nx214, nx218, nx225, nx228, nx230: std_logic ;nx218, nx225, nx228, nx230: std_logic ;

beginbeginQ(2) <= Q_2_EXMPLR ;Q(2) <= Q_2_EXMPLR ;Q(1) <= Q_1_EXMPLR ;Q(1) <= Q_1_EXMPLR ;Q(0) <= Q_0_EXMPLR ;Q(0) <= Q_0_EXMPLR ;ix170 : mux21_ni port map ( Y=>nx169, A0=>nx14, A1=>Q_0_EXMPLix170 : mux21_ni port map ( Y=>nx169, A0=>nx14, A1=>Q_0_EXMPLR, S0=>nx225);R, S0=>nx225);ix15 : oai22 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>nx202, Bix15 : oai22 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>nx202, B0=>nx230, 0=>nx230,

B1=>count);B1=>count);ix203 : nand02 port map ( Y=>nx202, A0=>count, A1=>nx204);ix203 : nand02 port map ( Y=>nx202, A0=>count, A1=>nx204);ix205 : nand04 port map ( Y=>nx204, A0=>count, A1=>Q_2_EXMPLRix205 : nand04 port map ( Y=>nx204, A0=>count, A1=>Q_2_EXMPLR, ,

A2=>Q_1_EXMPLR, A3=>nxA2=>Q_1_EXMPLR, A3=>nx228);228);ix180 : oai32 port map ( Y=>nx179, A0=>nx208, A1=>count, A2=>ix180 : oai32 port map ( Y=>nx179, A0=>nx208, A1=>count, A2=>load, load,

B0=>nx212, B1=>nx225);B0=>nx212, B1=>nx225);Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>nx208,Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>nx208, D=>nx179, D=>nx179,

CLK=CLK=>clk, R=>NOT_reset);>clk, R=>NOT_reset);

Synthesized netlist (3)Synthesized netlist (3)

ix211 : inv01 port map ( Y=>NOT_reset, A=>reset);ix211 : inv01 port map ( Y=>NOT_reset, A=>reset);

ix213 : aoi22 port map ( Y=>nx212, A0=>I(2), A1=>nx214, B0=>nix213 : aoi22 port map ( Y=>nx212, A0=>I(2), A1=>nx214, B0=>nx22, B1=>nx4 );x22, B1=>nx4 );

ix216 : inv01 port map ( Y=>nx214, A=>count);ix216 : inv01 port map ( Y=>nx214, A=>count);

ix219 : nand02 port map ( Y=>nx218, A0=>Q_1_EXMPLR, A1=>Q_0_Eix219 : nand02 port map ( Y=>nx218, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR);XMPLR);

Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx189, D=>nx189,

CLKCLK=>clk, R=>NOT_reset);=>clk, R=>NOT_reset);

ix190 : mux21_ni port map ( Y=>nx189, A0=>nx60, A1=>Q_1_EXMPLix190 : mux21_ni port map ( Y=>nx189, A0=>nx60, A1=>Q_1_EXMPLR, S0=>nx225);R, S0=>nx225);

ix61 : ao32 port map ( Y=>nx60, A0=>nx48, A1=>nx218, A2=>nx4,ix61 : ao32 port map ( Y=>nx60, A0=>nx48, A1=>nx218, A2=>nx4, B0=>I(1), B0=>I(1),

B1=>nx214);B1=>nx214);

ix49 : or02 port map ( Y=>nx48, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLix49 : or02 port map ( Y=>nx48, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR);R);

ix226 : nor02_2x port map ( Y=>nx225, A0=>count, A1=>load);ix226 : nor02_2x port map ( Y=>nx225, A0=>count, A1=>load);

Q_0_EXMPLR_EXMPLR : dffr port map ( Q=>Q_0_EXMPLR, QB=>nx228,Q_0_EXMPLR_EXMPLR : dffr port map ( Q=>Q_0_EXMPLR, QB=>nx228, D=>nx169, D=>nx169,

CLKCLK=>clk, R=>NOT_reset);=>clk, R=>NOT_reset);

ix231 : inv01 port map ( Y=>nx230, A=>I(0));ix231 : inv01 port map ( Y=>nx230, A=>I(0));

ix5 : inv01 port map ( Y=>nx4, A=>nx202);ix5 : inv01 port map ( Y=>nx4, A=>nx202);

ix23 : xor2 port map ( Y=>nx22, A0=>nx208, A1=>nx218);ix23 : xor2 port map ( Y=>nx22, A0=>nx208, A1=>nx218);

end Behave ;end Behave ;

PostPost--synthesis simulation (1)synthesis simulation (1)((LeonardoLeonardo--generated netlist)generated netlist)

�� Verify synthesized netlist matches behavioral Verify synthesized netlist matches behavioral modelmodel

�� Create simulation primitives library for std cells:Create simulation primitives library for std cells:>vlib adk>vlib adk>vcom $ADK/technology/adk.vhd>vcom $ADK/technology/adk.vhd>vcom $ADK/technology/adk_comp.vhd>vcom $ADK/technology/adk_comp.vhd

�� Insert library/package declaration into netlistInsert library/package declaration into netlistlibrary adk;library adk;use adk.adk_components.all;use adk.adk_components.all;

�� Simulate in Modelsim, using Simulate in Modelsim, using ““do filedo file”” or test bench from or test bench from original behavioral simulation original behavioral simulation –– results should matchresults should match

VITALmodels of all ADK std cells

PostPost--synthesis simulation (2)synthesis simulation (2)

�� Edit the synthesized VHDL netlist file (modulo7_0.vhd) to Edit the synthesized VHDL netlist file (modulo7_0.vhd) to include the package of component declarations:include the package of component declarations:

---- Definition of modulo7Definition of modulo7

---- Thu Sep 21 10:48:09 2006Thu Sep 21 10:48:09 2006

---- LeonardoSpectrum Level 3, 2005a.82LeonardoSpectrum Level 3, 2005a.82

----

library IEEE;library IEEE;

use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_1164.all;

library adk;library adk; ---- add these two linesadd these two lines

use adk.adk_components.all;use adk.adk_components.all;

entity modulo7 isentity modulo7 is

port (port (……....

PostPost--synthesis simulation (3)synthesis simulation (3)

�� Compile the VHDL netlist: Compile the VHDL netlist:

vcom modulo7_0.vhdvcom modulo7_0.vhd

�� Simulate the model:Simulate the model:

vsim modulo7 vsim modulo7 ––do modulo7.dodo modulo7.do

(modul7.do is a (modul7.do is a ““force fileforce file””))

�� Verify that the synthesized circuit produces the Verify that the synthesized circuit produces the

same results as the behavioral circuitsame results as the behavioral circuit

PostPost--synthesis timing analysissynthesis timing analysis�� Leonardo can generate SDF (std. delay format) file with Leonardo can generate SDF (std. delay format) file with

technologytechnology--specific, VITALspecific, VITAL--compliant timing parameters.compliant timing parameters.

(CELLTYPE "dffr")(CELLTYPE "dffr")

(INSTANCE Q_0_EXMPLR_EXMPLR)(INSTANCE Q_0_EXMPLR_EXMPLR)

(DELAY(DELAY

(ABSOLUTE(ABSOLUTE

(PORT D (::0.00) (::0.00))(PORT D (::0.00) (::0.00))

(PORT CLK (::0.00) (::0.00))(PORT CLK (::0.00) (::0.00))

(PORT R (::0.00) (::0.00))(PORT R (::0.00) (::0.00))

(IOPATH CLK Q (::0.40) (::0.47))(IOPATH CLK Q (::0.40) (::0.47))

(IOPATH R Q (::0.00) (::0.55))(IOPATH R Q (::0.00) (::0.55))

(IOPATH CLK QB (::0.45) (::0.36))(IOPATH CLK QB (::0.45) (::0.36))

(IOPATH R QB (::0.53) (::0.00))))(IOPATH R QB (::0.53) (::0.00))))

(TIMINGCHECK(TIMINGCHECK

(SETUP D (posedge CLK) (0.47))(SETUP D (posedge CLK) (0.47))

(HOLD D (posedge CLK) ((HOLD D (posedge CLK) (--0.06))))0.06))))

ASIC Physical Design (Standard Cell)ASIC Physical Design (Standard Cell)(can also do full custom layout)(can also do full custom layout)

FloorplanChip/Block

Place & RouteStd. Cells

Component-Level Netlist (EDDM format)

IC Mask Data

Design RuleCheck

Std. CellLayouts

Mentor Graphics“IC Station”

(adk_ic)

Mach TA/Eldo Simulation Model

BackannotateSchematic

GenerateMask Data

Layout vs.SchematicCheck

Design Rules

Process Data

Libraries

Calibre Calibre Calibre

ICblocks

CellCell--Based ICBased IC

CellCell--Based BlockBased Block

Source: Weste “CMOS VLSI Design”

Basic standardCell layout

Preparation for LayoutPreparation for Layout1.1. Use Design ArchitectUse Design Architect--IC to convert Verilog netlist to IC to convert Verilog netlist to

Mentor Graphics EDDM netlist formatMentor Graphics EDDM netlist format–– Invoke Design ArchitectInvoke Design Architect--IC IC (adk_daic)(adk_daic)–– On menu bar, select On menu bar, select File > Import VerilogFile > Import Verilog

�� Netlist file: Netlist file: count4.v count4.v (the Verilog netlist)(the Verilog netlist)�� Output directory: Output directory: count4count4 (for the EDDM netlist)(for the EDDM netlist)

�� Mapping file Mapping file $ADK/technology/adk_map.vmp$ADK/technology/adk_map.vmp

2.2. Open the generated schematic for viewingOpen the generated schematic for viewing–– Click Click SchematicSchematic in DAin DA--IC palette IC palette

–– Select schematic in directory named above Select schematic in directory named above (see next slide)(see next slide)

–– Click Click Update LVS Update LVS in the schematic palette to create a netlist to in the schematic palette to create a netlist to be used later by be used later by ““CalibreCalibre””

3.3. Create design viewpoints for ICstation toolsCreate design viewpoints for ICstation tools–– adk_dve count4 adk_dve count4 ––t tsmc035 t tsmc035 (V.P(V.P’’s: layout, lvs, sdl, tsmc035)s: layout, lvs, sdl, tsmc035)

�� Can also create gate/transistor schematics directly in Can also create gate/transistor schematics directly in DADA--IC using components from the ADK libraryIC using components from the ADK library

DADA--IC generated schematicIC generated schematic

Create a stdCreate a std--cell based logic block cell based logic block

in IC Stationin IC Station

�� Invoke: Invoke: adk_ic adk_ic

�� In IC Station palette, select:In IC Station palette, select: Create CellCreate Cell–– Cell name: Cell name: count4count4

–– Attach library: Attach library: $ADK/technology/ic/process/tsmc035$ADK/technology/ic/process/tsmc035

–– Process: Process: $ADK/technology/ic/process/tsmc035$ADK/technology/ic/process/tsmc035

–– Rules file: Rules file: $ADK/technology/ic/process/tsmc035.rules$ADK/technology/ic/process/tsmc035.rules

–– Angle mode: Angle mode: 4545

–– Cell type: Cell type: blockblock

–– Select Select With connectivityWith connectivity

–– EDDM schematic viewpoint:EDDM schematic viewpoint: count4/layoutcount4/layout

–– Logic loading options:Logic loading options: flatflat

Create Cell dialog boxCreate Cell dialog box

AutoAuto--””floorplanfloorplan”” the blockthe blockplace & route > autofpplace & route > autofp

AutoAuto--place the std cellsplace the std cellsAutoplc > StdCelAutoplc > StdCel

AutoAuto--place place ““portsports”” (Autoplc > Ports)(Autoplc > Ports)

Signal connections on cell boundariesSignal connections on cell boundaries

AutoRoute all netsAutoRoute all nets(hand(hand--route any unrouted route any unrouted ““overflowsoverflows””))

Then: Add > Port Text to copy port names from schematic – for Calibre

Layout design rule check (DRC)Layout design rule check (DRC)

�� TechnologyTechnology--specific design rules specify specific design rules specify minimum sizes, spacing, etc. of features minimum sizes, spacing, etc. of features to ensure reliable fabricationto ensure reliable fabrication–– Design rules file specified at startupDesign rules file specified at startup

Ex. Ex. tsmc035.rulestsmc035.rules

�� From main palette, select ICrules From main palette, select ICrules –– Click Click Check Check and thenand then OK OK in prompt boxin prompt box

(can optionally select a specific area to check)(can optionally select a specific area to check)

–– Rules checked in numeric orderRules checked in numeric order

Layout vs schematic checkLayout vs schematic check

Calibre Interactive LVSCalibre Interactive LVS

�� From ICstation menu: From ICstation menu: Calibre > Run LVSCalibre > Run LVS

–– In popup, Calibre location: In popup, Calibre location: $MGC_HOME/../Calibre$MGC_HOME/../Calibre

–– Rules: Rules: $ADK/technology/ic/process/tsmc035.calibre.rules$ADK/technology/ic/process/tsmc035.calibre.rules

–– Input: Input: count4.src.net count4.src.net (previously created in DA(previously created in DA--IC)IC)

–– HH--cells: cells: $ADK/technology/adk.hcell$ADK/technology/adk.hcell (hierarchical cells)(hierarchical cells)

–– Extracted file: Extracted file: count4.lay.netcount4.lay.net

�� Compares extracted transistorCompares extracted transistor--level netlist vs. level netlist vs.

netlist saved in DAnetlist saved in DA--ICIC

PostPost--layout parameter extractionlayout parameter extraction

Calibre Interactive PEXCalibre Interactive PEX

�� Extract Spice netlist, including parasitic RCExtract Spice netlist, including parasitic RC–– Simulate in Eldo or MachTASimulate in Eldo or MachTA

�� ICstation menu: ICstation menu: Calibre>Run PEXCalibre>Run PEX–– Options similar to Calibre LVSOptions similar to Calibre LVS

–– Extraction options:Extraction options:�� lumped C + coupling caplumped C + coupling cap’’ss

�� distributed RCdistributed RC

�� distributed RC + coupling capdistributed RC + coupling cap’’ss

–– Output file: count4.pex.netlistOutput file: count4.pex.netlist