VLSI DesignL 4 Wi d ViLecture 4: Wires and Vias,

ParasiticsParasitics

Shaahin HessabiDepartment of Computer Engineering

Sharif University of TechnologyAdapted, with modifications, from lecture notes prepared by the

book author (from Prentice Hall PTR)

Topicsp

Wire and via structures. Wire parasitics.CapacitancepResistance

Transistor parasitics Transistor parasitics. Fabrication theory and practice.

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Wires and vias

metal 3

metal 2

viasmetal 1

vias

p-tub

poly poly

n+n+ p tub

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Metal interconnect

Many layers of metal interconnect are possible.12 layers of metal are common.

Lower layers have smaller features, higher layers have y , g ylarger features.

Can’t directly go from a layer to any other layer Can t directly go from a layer to any other layer.

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Copper interconnectpp

Much better electrical characteristics. Copper is poisonous to semiconductors---must be

isolated from silicon.Bottom layer of interconnect is aluminum.

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Metal migrationg

Current-carrying capacity of metal wire depends on cross-section. Height is fixed, so width determines current limit.

Metal migration (a.k.a. electromigration): when current is too high, electron flow pushes around metal grains. g , p gHigher resistance increases metal migration, leading to destruction of wire.

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Metal migration problems and solutionsg p

Marginal wires will fail after a small operating period—infant mortality.

Normal wires must be sized to accomodate maximum current flow:Imax = 1.5 mA/m of metal width.max /

Mainly applies to VDD/VSS lines.

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Diffusion wire capacitancep

Capacitances formed by p-n junctions:

depletion regionsidewall

capacitances

n+ (ND)n (ND)

substrate (NA)bottomwallcapacitance

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Depletion region capacitancep g p

Zero-bias depletion capacitance:Cj0 = si/xd.

Depletion region width:p gxd0 = sqrt[(1/NA + 1/ND)2siVbi/q].

Junction capacitance is function of voltage across Junction capacitance is function of voltage across junction:C (V ) = C /sqrt(1 + V /V )Cj(Vr) = Cj0/sqrt(1 + Vr/Vbi)

» Junction capacitance decreases as the reverse bias voltage increases.

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Poly/metal wire capacitancep

Two components:parallel plate; fringe.

fringe

plate

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Metal coupling capacitancesp g p

Can couple to adjacent wires on same layer, wires on above/below layers:

metal 2

metal 1 metal 1metal 1 metal 1

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Example: parasitic capacitance measurementp p p

n-diffusion: bottomwall=2 fF, sidewall=2 fF. metal: plate=0.15 fF, fringe=0.72 fF.

1.5 m

3 m

0.75 m 1 m 2.5 m

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Wire resistance

Resistance of any size square is constant:

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Calculating resistanceg

Determine current flow, then aspect ratio:

I2

20I2

vs.

20I2

20

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Current around corners

Resistance at corner of two equal width wires is Resistance at corner of two equal-width wires is approximately 1/2 square:

1/2 square

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Skin effect

At low frequencies, most of copper conductor’s cross section carries current.

As frequency increases, current moves to skin of q y ,conductor.Back EMF (electromagnetic force) induces counter-current in ( g )

body of conductor.

Skin effect most important at gigahertz frequencies.p g g q

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Skin effect, cont’d

Isolated conductor: Conductor and ground:

Low frequencyLow frequencyq y

High frequencyi h f

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High frequency

Skin depthp

Skin depth depth at which conductor’s current is reduced to 1/e = 37% of surface value: = 1/sqrt(f ) f = signal frequency = magnetic permeabilityg p = wire conductivity

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Effect on resistance

Low frequency resistance of wire:Rdc = 1/( wt)

» w and t are the width and height of the conductor.

High frequency resistance with skin effect:Rhf = 1/[2 (w + t)]hf [ ( )]

Resistance per unit length:R = sqrt(Rd

2 + Rhf2Rac sqrt(Rdc + Rhf

Typically = 1.2.

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Transistor gate parasiticsg p

Gate-source/drain overlap capacitance:

tgate

source drain

overlap

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Transistor source/drain parasiticsp

Source/drain have significant capacitance, resistance.Significant effect on circuit performance.

Measured same way as for wires.y Source/drain R, C may be included in Spice model rather

than as separate parasiticsthan as separate parasitics.

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Why we need design rulesg

Masks are tooling for manufacturing. Manufacturing processes have inherent limitations in

accuracy.y Design rules specify geometry of masks which will

provide reasonable yieldsprovide reasonable yields. Design rules are determined by experience.

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Design rules and yieldg

Design rules are determined by manufacturing process characteristics.

Design rules should provide adequate yield if followed.g p q y Types of design rules:Spacing and minimum size rulesSpacing and minimum size rules.Separation.CompositionComposition.

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Yield

Gamma distribution for yield of a single type of structure:Yi = [1/(1+Ai)]i

Total yield for the process is the product of all yield components:pY = Yi

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Manufacturing problemsg p

Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature Variations in temperature. Variations in oxide thickness.

I i i Impurities. Variations between lots. Variations across a wafer.

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Transistor problemsp

Varaiations in threshold voltage:oxide thickness; ion implanatation;poly variations.

Changes in source/drain diffusion overlap.g / p Variations in substrate.

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Wiring problemsg p

Diffusion: changes in doping -> variations in resistance, capacitance.

Poly, metal: variations in height, width -> variations in y, g ,resistance, capacitance.

Shorts and opens: Shorts and opens:

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Oxide problemsp

Variations in height. Lack of planarity -> step coverage.

t l 2

metal 1metal 2

metal 2

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Via problemsp

Via may not be cut all the way through. Undesize via has too much resistance. Via may be too large and create short Via may be too large and create short.

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Scaling theoryg

Chips get better as features shrink in classical scaling theory:Capacitive load goes down faster than current.

Classical scaling theory runs into complications at nanometer features.Leakage.Smaller supply voltage.Smaller supply voltage.

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Scaling modelg

/x. W W/x, L L/x. t t /x tox tox /x. Nd Nd/x.

(V V ) (V V )/ (VDD VSS) (VDD VSS)/x.

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Current and capacitance scalingp g

Saturation drain current scales as 1/x. Capacitance scales as 1/x. Total performance over scaling: Total performance over scaling: [C’V’/I’]/[CV/I] = 1/x.Circuit speeds up by factor xCircuit speeds up by factor x.

Shrinking makes chip faster and smaller.

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Interconnect scalingg

Two varieties of interconnect scaling: Ideal scaling reduces vertical and horizontal dimensions equally.

» resistance per unit length grows quickly as wires are scaled

Constant dimension does not change wiring sizes.» resistance per unit length stays the same.

Higher levels of interconnect are constant dimension---same as older technologies.

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Interconnect scaling trendsg

Ideal scaling Constant dimensionLine width and spacing S 1Line width and spacing S 1Wire thickness S 1Interlevel dielectric S 1Wire length 1/sqrt(S) 1/sqrt(S)Resistance/unit length 1/S2 1Capacitance/unit length 1 1RC delay 1/S3 1/SCurrent density 1/S SCurrent density 1/S S

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ITRS roadmapp

Semiconductor industry projects fabrication trends.Helps plan future technologies.

Roadmap describes features, technology required to get p , gy q gto those goals.

2005 2006 2007 2008 2009 2010 2011 2012

CPU l i h 90 75 68 59 52 45 40 36CPU metal pitch 90 75 68 59 52 45 40 36

CPU gate length 32 28 25 23 20 18 16 14

ASIC l h 45 38 32 28 25 23 20 18ASIC gate length 45 38 32 28 25 23 20 18

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