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PPT of the few chapters of the author
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http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
Laser on silicon
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courtesy: Blas Garrido
http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
Laser on silicon
Group IV materials …. Indirect bandgap materials….
What are the potentialities of such materials?
Erbium doped silicon nanocrystalsStrained germanium to go towards a pseudo direct gap
materialGe/SiGe heterostructures…
III-V SC on silicon Is it a CMOS compatible technology?
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http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
Germanium laser
Demonstration of optical gain in strained Ge
Demonstration of electro-luminescence
Demonstration of the first Ge laser
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“The first Ge laser”; J. Liu, X. Sun, L.C. Kimerling, J. Michel : Presentation at Group IV photonics – San Francisco (September 2009).
http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
Gemanium laser
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http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
III-V on silicon
Numerous works did and to do…
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J. Van Campenhout et al., Optics Express,15(11),p.6744-6749(2007)
http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
Option beta -
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Use wire-bonding to connect chips
Not a waferscale approach
Not compatible with micro-electronics packaging
http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
PhotonicsTransistors
Photonics-electronics integration
Front-end fabrication
Very low parasitics Custom SOI, specific libraries process co-integration
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http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
Front-end approach
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http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
CMOS front-end monolithic nanophotonicsintegration – IBM approach
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Advantages:
Deeply scaled NanophotonicsMost dense integration with CMOSUltra-low power optical interconnectsSame mask set, standard processingSame design environment (e.g. Cadence) Same EDA tools and design flowPossible in-line system-level testing
Nanophotonics sharing Si layer with FET body
http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
Photonics
TransistorsPhotonicsTransistors
Photonics-electronics integration
Front-end fabrication
Very low parasitics Custom SOI, specific libraries process co-integration
Back-end fabrication
On top of CMOS or in metal layers Serial process Compound yield Thermal budget < 400C
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http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien11
http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
Photonics-electronics integration
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Photonics
TransistorsPhotonicsTransistors
Front-end fabrication
Very low parasitics Custom SOI, specific libraries process co-integration
Back-end fabrication
On top of CMOS or in metal layers Serial process Compound yield Thermal budget < 400C
3D integration Separate processes No change in CMOS Front-End No thermal budget! Other layers: MEMS, antennas Higher (but reasonable) parasitics
Transistors
Photonics
http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
3D integration
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CMOSwafer
transistorsmetal interconnects
FC
Modulator
AWG
Ge PD
InP source
Pad
3D integration Not depending on the
specific node used to produce the electronic wafer
Germanium Germanium
Si rib waveguide Germanium PD Flip grating coupler AWG on CMOS
http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
Conclusion
Photonic links may replace copper links, even for very short distances
Integration on silicon is key To reach competitive cost To reduce size and power consumption while scaling up
bandwidth A full design, fabrication and integration chain is under
construction High performance building blocks demonstrated Versatile photonics-electronics integration process
Complex circuits are under development
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http://silicon-photonics.ief.u-psud.fr/ Laurent Vivien
Main challenges
Silicon photonics is still in its infancy and is facing several challenges: Automated design flow Laser: yield, reliability, temperature
Integrated, hybrid assembly or external ? Modulator: footprint, driving voltage, power consumption Process integration Integration of complex circuits: thermal, electrical, photonic
crosstalk/feedback Photonic-electronic integration scheme
Front end, 3D wafer-wafer integration, 3D chip to wafer Packaging: RF, optical, thermal management
Keys for development:
Reliability at wafer scale Driving voltage of modulator Power consumption Integration cost Packaging
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