VIVADO TUTORIAL- TIMING AND POWER

ANALYSIS

IMPORTING THE PROJECT FROM ISE TO VIVADO ➢ Initially for migrating the same project which we did in ISE 14.7 to Vivado 2016.1 you will need to

follow the steps below.

➢ First open the Vivado software and you will get the screen shown below. Click on create project and

proceed to next step.

➢ Click on next and proceed to the next window. In this window click on Imported project as shown

below

Click next and proceed to the next window.

➢ Next click on the ISE tab under project file section and click on to select the appropriate ISE file

of the project that you want to import in Vivado.

➢ Once you click next you will get the following screen to select the ISE file.

➢ Click on OK after selecting the ISE file and you arrive at the following screen.

➢ Then click Next to import the project to Vivado.

➢ Once you follow these steps the project will be imported in Vivado successfully and you should get the

following screen.

VIVADO TIMING ANALYSIS ➢ From the Flow Navigator, select Add Sources in the Project Manager section.

➢ From the list displayed in the Add Sources dialog box, select Add or Create Constraints and click Next.

➢ After you click next you should arrive at the following screen. Please click on Create File and give the File name as you like. Click OK after you name it. This will create a xdc file.

➢ Next Select Edit Timing Constraints from the Flow Navigator under the Netlist Analysis section.

➢ The Vivado IDE displays the Timing Constraints window as shown below.

➢ Under the Clocks heading of the Constraints tree view, double-click Create Clock. This opens the Create

Clock wizard as shown below.

➢ Enter the Clock Name. The clock name can be any name and does not have to match any element of the design (port or pin); it is just a name. For the Source Objects field select the browse button to bring up the following screen.

➢ Change “*” to “*clk” and click the Find button. “clk” should appear under Find results. ➢ Select “clk” and click the directional (right) arrow to move it under Selected names.

➢ Select OK to finish specifying the clock sources and return to the Create Clock wizard. Click OK again to close the Create Clock wizard and create the clk clock constraint as shown.

➢ Click Apply at the bottom of the Timing Constraints window to save the clk constraint and update the

in-memory design with any new or changed constraints. ➢ Note that You have not yet saved the constraint to the timing.xdc file. Notice that when you create the

clock constraint, the Save Constraints icon is enabled. As shown below.

➢ Click the Save Constraints icon. ➢ Double-click on the timing.xdc file. The timing.xdc opens in the Vivado text editor and shows the

create_clock command with context-sensitive text coloring as shown below.

➢ Next click on the Report Timing Summary under the Implementation column as shown below.

➢ Once you do that you should arrive at the flowing screen.

➢ Click OK and proceed to get the Design Timing Summary which contains the Worst Negative Slack, Worst Hold Slack and WPSN as shown below.

➢ We can generate a custom timing report for all paths in the Design. Select Tools > Timing > Report Timing to bring up the Report Timing dialog box as shown below.

➢ The report Timing dialog box opens as shown below.

➢ Click OK to generate the timing report as shown below.

➢ Notice that you now see values in the Slack Column and have Source and Destination Clock values for each path.

VIVADO POWER ANALYSIS

➢ You can click on the Report Power under the Synthesis column to get the power utilization summary of

the Design as shown below.

➢ Once you do that you can view the following window.

➢ Click ok to proceed and you should be able to view the Power Analysis as follows.

SCHEMATIC OF THE IMPLEMENTED DESIGN

➢ Once you Synthesize the Design in Vivado you can view the schematic of the Design by clicking on

Open Elaborated Design under the RTL Analysis column.

➢ Once you do that you will be generating the Schematic of your design as Shown in the Below

Example.