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Vivado Flow

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    VIVADO FLOW1. Open Vivado

    2. Click Create New Project to start the wizard. You will see Create A New Vivado

    Project dialog box. Click Next.

    3. Browse your project location and give your project name.

    4. Select RTL Project option in the Project Type form, and click Next.

    5. Change Family to Artr ix 7 ,Sub Family to Artr ix 7 and so on as specified on the kit.

    6. Project Manager window pops up. Go to ADD Sources then Add or Create Design

    Sources then create file and next and then finish.

    7. Assign ports in the pop up window.

    8. In the project manager window observe the files created under design sources and

    then click on the files and write the corresponding codes

    9. Change or set the properties of test bench file to simulation only and uncheck the

    synthesis and implementation check boxes .

    10. Save both the files and then perform simulation by selecting Run Simulation and

    then Run Behavioural Simulation and observe the waveforms.

    11. Perform RTL Analysis on the source code

    Expand the Open Elaborated Design entry under the RTL Analysis tasks of

    the Flow Navigator pane and click on Schematic.

    12. Port Mapping or allocation of pins

    Select the source code then RTL Analysis and then change the Default

    Layout in the menu bar to I/O Planning.

    ** Note : Change I/O Standard to LVCMOS33

    13. Run Synthesis on your project source file by selecting Run Synthesis from the

    Synthesis flow navigator.

    14. Run Implementation by selecting Run Implementation from Implementation flow

    navigator.

    15. Generate bit file by choosing Generate bit stream from Program and Debug flow

    navigator.

    Functionality Verification

    16. Select the Open Hardware Manager option and click OK

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    17. Click on the Open a new hardware target link and Next to see CSE Server Name and

    Next with localhost port selected.Click Next twice and Finish

    18. Select the device and verify that the bit file is selected as the programming file in the

    Generaltab.

    19. Right-click on the device and select Program Device to program the target FPGA

    device.

    20. Click OK to program the FPGA with the selected bit stream.


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