Upload
cihd1698488
View
112
Download
4
Embed Size (px)
DESCRIPTION
electronics and commn
Citation preview
FPGA IMPLEMENTATION OF FIR FILTER STRUCTURES
ByG. Aruna Sukeerthi (M.Tech - C&C)
Regd. No: 08021D3627
Under the Guidance of
Sri K.BABULU,Associate Professor in ECE,
JNTU CE, Kakinada
AIM
This Project work mainly concentrates on Design and FPGA implementation of FIR filter structures.
Design Entry -VHDL Language Simulation -ModelSim XE III 6.2g Synthesis -Xilinx Synthesis Tool FPGA Target Device -Spartan3E:XC3S500E
INTRODUCTION
Choices of implementing a DSP application (FIR Filter)
Using a dedicated DSP processor
Using a hardware approachFPGAASIC
FIR FILTER
An FIR filter is usually implemented by using a series of delays, multipliers, and adders to create the filter's output.
The logical structure of an FIR filter
PROBLEMS IN DESIGNING FIR FILTER
• Excessive area
• Power consumption
FIR FILTER DESIGN WITH FDA TOOL
6-tap FIR Filter Structures are designed with constant and fixed coefficients.
• Filter specifications
• Sampling Frequency Fs = 50 KHz
• Pass Band Edge Frequency = 15 KHz
• Stop Band Edge frequency = 18 KHz
FIR FILTER STRUCTURES
Direct form FIR filter
Transposed form FIR filter
Symmetric form FIR filter
Distributed arithmetic FIR filter
MODULES IN FIR FILTER STRUCTURES
• Adder/ Subtractor
• Multiplier
• Parallel In Parallel Out shift register
• LUT
• Accumulator
DIRECT FORM FIR FILTER - BLOCK DIAGRAM
y(n)
16 16 16 16 16 16
16 16 16 16 16 16
1616161616
16 16 16 16 16
16
16
TRANSPOSED FORM FIR FILTER - BLOCK DIAGRAM
h(6)
16
16
Z-1
h(5)
16
16Z-1
h(4)
16
16Z-1
h(3)
16
16Z-1
h(2)
16
16Z-1
h(1)
16
16Z-1
X[n]
Y[n]
SYMMETRIC FORM FIR FILTER - BLOCK DIAGRAM
DISTRIBUTED ARITHMETIC FIR FILTER - BLOCK DIAGRAM
SIMULATION RESULTS
Impulse Response
SIGNAL DESCRIPTION• Input Signals : rst, clk,x (15 downto 0)
• Output Signal : count, y (15 downto 0)
• Logic: Whenever the ‘rst’ is set to ‘1’ the register will reset i.e.; all the
bits are set to ‘0’. When rst=’0’ normal operation will be carried out. Under the raising edge of clock the input is assigned at the input line. Here, ‘Count’ is an intermediate signal that counts the number of clock cycles. When the count reaches the value 6 that indicates input sequence is entirely processed till the last stage. The output response of a filter for an impulse is nothing but the sequence of filter coefficients.
Contd…
Step Response
Contd..
• Input Signals : rst, clk,x (15 downto 0)
• Output Signal : y (15 downto 0)
• Logic: Whenever the ‘rst’ is set to ‘1’ the register will reset i.e.; all the
bits are set to ‘0’. When rst=’0’ normal operation will be carried out. Under the raising edge of clock the input is assigned at the input line. The input x is a step signal hence it is shown as a sequence of bits for which a few bits are 0’s at the start and next all 1’s. The output response of a filter for a step is nothing but the cumulative sum of fir filter coefficients processed.
Contd…
Low frequency Sine wave
Contd..
• Input Signals : rst, clk,x (15 downto 0)
• Output Signal : y (15 downto 0)
• Logic: Whenever the ‘rst’ is set to ‘1’ the register will reset i.e.; all the
bits are set to ‘0’. When rst=’0’ normal operation will be carried out. Under the raising edge of clock the input is assigned at the input line. For the sine wave signal at the input, the filter gives the output same as input signal without any attenuation as this is a low pass filter.
Contd…
Low frequency sine wave with added noise
Contd..
• Input Signals : rst, clk,x (15 downto 0)• Output Signal : y (15 downto 0)• Logic: Whenever the ‘rst’ is set to ‘1’ the register will reset
i.e.; all the bits are set to ‘0’. When rst=’0’ normal operation will be carried out. Under the raising edge of clock the input is assigned at the input line. The noise added sine wave gives the response as the sine wave with reduction in noise to some extent at the output. As this is a low pass filter high frequency components are attenuated to some extent.
SYNTHESIS REPORT ANALYSIS -COMPARISON OF FIR FILTER
STRUCTURESFIR
Structures Number of arithmetic
operationCritical path
delay(ns)
FPGA area(number of
slices)Additions
Multiplications
Direct Structure
5 6 6.669 257
Transposed
Structure
5 6 6.047 95
Symmetric structure
5 3 1.967 95
Distributed Arithmetic Structure
5 shift & Add
operations
0 6.290 39
DIRECT FORM FIR FILTER- RTL VIEW
TRANSPOSED FORM FIR FILTER- RTL VIEW
SYMMETRIC FORM FIR FILTER- RTL VIEW
DISTRIBUTED ARITHMETIC FIR FILTER – RTL VIEW
FLOOR PLANNING
ROUTING ANALYSIS
CHIP VIEW
PROTOTYPING ON FPGA
• FIR filter architectures are implemented on Spartan3E FPGA device by incorporating ChipScope modules into design.
• The implemented filter structure is tested for validation by the following test cases. Impulse responseStep responseLow frequency sine waveLow frequency sine wave with riding high frequency
noise on it
ChipScope Pro Analyser Results
Impulse Response
Contd…
Step response
Contd…
• Input : Low Frequency Sine Wave
• Output
Contd…• Input : Low freq sine plus high frequency noise
• Output
APPLICATIONS
• FPGA based digital signal processing algorithms
• Digital front end receiver for filtering the high frequency components in digital
• Several other places where FIR filter is required.
CONCLUSION
• Different FIR filter architectures have been introduced and the sub modules involved for all the architectures have been discussed clearly.
• Simulation for all the FIR filter architectures has been carried out and the outputs have been clearly discussed by considering four different input formats.
• Synthesis has been performed for all the FIR filter structures.
• All the FIR filter architectures have been successfully implemented on Spartan 3E FPGA device.
FUTURE SCOPE
• The implemented FIR structures at code level can be modified to make full benefit from the FPGA, such as using fast carry chains, Embedded Array Blocks etc.
• To achieve the peak performance fully parallel pipelined version can be implemented
• In the present work the DA based FIR filter is implemented with one LUT and without pipelining. This can be extended to full parallel implementation with more than one LUTs for high speed applications. The following figure shows a possible architecture.
BIBLIOGRAPHY Simon Haykin, Communication Systems, Fourth Edition, John
Wiley & Sons, Inc. J. Bhaskar, A VHDL Premier, Third Edition, Pearson
Education Asia. 5. Volnei A. Pedroni, Circuit design with VHDL. Digital Signal Processing with Field Programmable Gate
Arrays, by U. Meyer-Baese, Springer Publications. Practical FIR Filter Design in MATLAB, Revision 1.1, Ricardo
A. Losada The MathWorks, Inc. Essentials of electronic testing for digital, memory and mixed
signal VLSI- by Micael Lee Bushnell, Vishwani D Agarwal. www.hunteng.co.uk www.fpgajournal.com