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A PresentationOn
DESIGN OF A LOW- VOLTAGE LOW- DROPOUT REGULATORIn Partial Fulfillment of the Requirements for the Degree of
MASTER OF TECHNOLOGY
inAdvanced Electronics and Communication Engineering with Specialization in VLSI Design
by DEVYANI
(Enrollment No.: 1309136702)
Under the Supervision of
Dr. Sampath Kumar and Mrs. Sangeeta Mangesh
JSS Academy of Technical Education, Noida
To theDepartment of Electronics Engineering
Dr. A.P.J. ABDUL KALAM UNIVERSITYLUCKNOW
May 2016
OUTLINE
• Problem Statement• Project Objective• Block Diagram• Proposed Work (Basic Circuit to result analysis)• Conclusion • Future Scope References
PROBLEM STATEMENT
“Design Of Low-Voltage Low-Dropout Regulator Using Current Splitting Technique
And 90nm CMOS Technology”
PROJECT OBJECTIVE
The aim is to design a LDO using current splitting technique with 90nm technology
model file. In which input of 1V convert into output of 0.85-0.5V with load of 1μF and
quiescent current of 60μA.
The next aim is to optimize the circuit to reduce power dissipation.
BLOCK DIAGRAM
Conceptual block diagram of LDO regulator
BASIC CIRCUIT OF LDO
LDO With Capacitor
SIMULATION OF LDO WITH 1μF CAPACITORand
AVERAGE POWER IS 7.06mW
CONVENTIONAL TWO STAGE MILLER OP- AMP
ANALYSIS OF SLEW RATE OF TWO STAGE MILLER OP- AMP
PROPOSED LDO WITH APPOS CIRCUIT
SIMULATION OF PROPOSED LDO WITH APPOS CIRCUITAnd
AVERAGE POWER IS 2.07mW
CONCLUSION
This project contains a deep study of LDO. An input of 1V used to achieve output of 0.85 to 0.5 V with a load capacitor of 1uF and quiescent current up to 60uA. This LDO provides minimum area of 0.0041mm2. But the drawback of the circuit is that it doesn’t include power and energy delivered to meet this compact area desire. However, on the basis of simulation results we can see that the power consumed by circuit is 7.06 mW which is exceptionally quite large.
In order to maintain a tradeoff between power and area an assistant push- pull output stage circuit was introduce along with class AB stage op- amp through which power consumption reduced to a level. And, this time average power of the circuit was 2.07mW
FUTURE SCOPE
We use low dropout regulator in most hand-held, battery-powered electronics feature power saving techniques to reduce power consumption. • The complexity and density of today's electronic designs equate to a limited amount of
PCB space. In order to address the trend toward ever-smaller electronics, LDOs must deliver the same performance while consuming as little space as possible.
• It offers a variety of LDOs that have been designed to address high-performance requirements in a tiny solution size.
• It’s wide input voltage LDOs (up to 100 volts) help designers manage large transient voltages for smart metering, smart grid, building automation and medical device applications. With their low quiescent current (down to 1uA), they extend the designs primary or back-up battery life. They come in robust packaging to accommodate power dissipation and harsh environments.
REFERENCES
BASE PAPER: Chung-Hsun Huang, Member, IEEE, Ying-Ting Ma, and Wei-Chen Liao, “Deaign of a Low – Voltage Low – Dropout Regulator,” IEEE J. TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , VOL. 22, NO. 6, JUNE 2014.
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THANK- YOU