VIRTUS

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http://www.virtus.eee.ntu.edu.sg

VIRTUS advances discovery and design (D&D) as well as research and development (R&D) in IC design and technology for applications in medical technology, clean technology and consumer electronics. Jointly funded by the Nanyang Technological University and Economic Development Board, the centre’s research areas are mainly in analog, mixed-signal, power management and data converters, energy harvesting, low-power RF and mm-wave IC’s, and new technology directions such as 3D-integration and physical design, 3D RF and mixed-signal circuits, and terahertz IC.

VIRTUS, IC Design Centre of Excellence

Director Associate Professor Siek Liter Email: elsiek@ntu.edu.sg

Siek Liter received the B.A.Sc. from University of Ottawa (OU), the M.Eng.Sc. from University of NSW (UNSW); and the PhD from Nanyang Technological University (NTU) with over 30 years of experience from the industry and the university in Analog/Mixed Signal IC Design. He is currently the Director of VIRTUS, IC Design Centre of Excellence in the School of Electrical and Electronic Engineering in NTU as well as the Director for the Joint NTU-TUM PhD & MSc (IC Design) Programmes. His research interests are in the design of analog/mixed signal ICs especially in the areas of Power Management circuits, PLLs and ADCs.

Founding Director Professor Yeo Kiat Seng Email: eksyeo@ntu.edu.sg

Yeo Kiat Seng is a widely known authority and world leader in the field of integrated circuit design. He has secured over S$30 million of research funding, published 6 books, 3 book chapters, over 300 international top-tier refereed journal and conference papers and holds 30 patents. He gave keynotes/invited talks at international conferences, serves in the editorial board of IEEE Transactions on Microwave Theory and Techniques and holds/held key positions as Advisor, General Chair, Co-General Chair and Technical Chair in international conferences. Dr. Yeo was awarded the Public Administration Medal (Bronze) on National Day 2009 by the President of the Republic of Singapore and was also awarded the distinguished Nanyang Alumni Award in 2009 for his outstanding contributions to the university and society.

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NTU’s NIEO to commercialize this novel batteryless transceiver. With the success of this work, Asst. Prof. Boon has been appointed as a principal investigator (PI) for electronic systems in the Singapore-MIT joint collaboration project “Low Energy Electronic Systems”. The project has won the Singapore-MIT Alliance for Research and Technology (SMART) International Research Grant (IRG) proposal with a grant total of S$25 million.

Batteryless Flexible Transceiver IEEE 802.15.4

Assistant Professor Boon Chirn Chye

Fig. 1 (a) Test setup of the transceiver, (b) Chip of the transceiver

In order to monitor the vital signs of an individual today, the patient is either confined to a hospital setting or connected to a cumbersome device that limits mobility. Miniature sensors can be used to detect and record heartbeats, respiration, blood pressure, or even taste and odour. These data could be wirelessly transferred to a central location and to notify healthcare personnel of abnormalities. To achieve such vision and to make sure it is practical, a critical problem that needs to be solved is the high power consumption in the transceiver for wireless communication. A research team led by Asst. Prof. Boon Chirn Chye has implemented and demonstrated a novel batteryless fully integrated transceiver. The novel transceiver was conceptualized, designed and silicon tested together with the energy harvesting module. Based on the energy aware and sub-threshold concept, the transceiver achieves a significant power consumption reduction of 11 times compared to conventional transceiver while meeting the specifications of IEEE802.15.4. This RF chip is energy-aware, meaning that it can adjust its performance based on the received signal strength. The energy harvested from Wi-Fi node can be used to power the transceiver. Discussion with venture capitalist Get2Volume is currently underway through

Fig. 2 (a) Experimental Setup (b) Pixel response with respect to moving object speed

Asynchronous Full-array-parallel Ultra-fast Motion Detection Imager

Assistant Professor Chen Shoushun

Motion feature is important to many applications including security surveillance, traffic enforcement and machine vision. These applications require continuous image acquisition and processing in real time. Conventional image sensor without on-chip computation capability will produce massive amounts of primitive and redundant image data. Transmitting and processing of these raw data consumes a lot of bandwidth and power. Moreover, with increasing spatial and coding resolutions for image sensor, such issues become even worse in multi-sensor network applications.

A team led by Asst. Prof Chen Shoushun designed an image sensor that allows high-speed pixel-parallel motion detection at the focal plane and combines address event representation (AER). Each pixel in the sensor can individually monitor the change in light intensity and reports an event if a threshold are reached. The output of the sensor is not a frame, but a stream of asynchronous digital events. Therefore the speed of the sensor is not limited by any traditional concept such as exposure time, frame rate. Shown by the simulation results in Fig. 2(a), it can capture ultra-fast motion object at more than 500m/s, which is traditionally done by high speed camera with millions frames per second.

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The sensor was designed using Global Foundries 0.18µm 6M1Pprocess, with die size of 2.5 x 2.5 mm2. The chip consumes about 70mW with power supply at 1.8V. The pixel has 30µmx30µm dimension with a fill-factor of 11%. Nearly 35% of the pixel area is consumed by capacitors and they are placed between analog and digital circuitry to achieve noise isolation. In order to test the chip, the team developed a FPGA based testing platform. The sensor is interfaced with an Opal-Kelly XEM 3010 FPGA board. The FPGA is configured to provide input control signals (clock, reset and switch

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between analog/motion mode), temporarily store the cluster data to an on-board SDRAM and communicate with a PC through a high speed USB link. On the PC side, a graphic user interface is developed which translates operational parameters such as frame rate and motion sensitivity into FPGA signals. The chip is currently under test and the team has obtained promising result.

3D NVM for Future Data Storage

Assistant Professor Yu Hao

Asst. Prof. Hao Yu and his students have developed a 3D Non-volatile Memory (NVM) design platform for future data storage. Featured with fast access speed, high density and zero standby power, the emerging NVM technologies at nano-scale such as spin-transfer torque magnetic tunnel junction (STT-MTJ) device, phase change memory (PCM) and etc. have introduced promising future for the new non-volatile computing. Their tremendous advantages over the currently prevailing NVM (i.e. Flash memory) make the nano-scale NVMs not only the candidates to serve as the next-generation storage, but also become the universal memory in computing systems.

Hybrid CMOS/NVM simulation is time consuming due to the very complex equivalent circuit of NVM devices. Asst. Prof. Yu suggested to introduce internal state variables into existing new MNA based SPICE simulator. Internal state variables describe device physics, based on which geometry-based physical models can be built. With this enhanced MNA, one SPICE-like simulator is developed, which simulates hybrid CMOS/NVM circuits tens of times faster than equivalent circuit approach, with similar or improved accuracy.

Based on the developed 3D NVM design platform, new 3D NVM devices and topologies could be efficiently explored. For example, Fig. 3(b) shows one hybrid CMOS and Memristor based 3D-crossbar memory architecture which was developed and analyzed with the platform. Diode-added memristors are used to prevent sneak-path and thus simplify the realization of 3D structure as well as reduce limitation on maximum crossbar size. An estimated 33% increase in the memory density is realized.

Fig. 3(c) shows a system level low power application by data retention using CBRAM crossbar based NVM. By exploiting the low power and fast access speed of CBRAM crossbar NVM, the system can transit between working mode and sleep mode frequently with unnoticeable overhead. Dirty bit write back strategy is deployed to further reduce unnecessary actions. The results suggested that both speed and power performance have several times improvement when compared with other works.

Fig. 3 (a) Enhanced MNA with internal state variables of NVM devices considered. (b) Diode-memristor crossbar based 3D non-volatile memory. (c) 3D hybrid memory system with CBRAM-crossbar based data-retention for power reduction

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THz Imaging for Security and Skin Cancer

Assistant Professor Yu Hao

The application of terahertz (THz) radiation brings new opportunities to imaging for purpose of security and also in-vivo diagnostic of skin/breast cancer. For example, THz for security examination is better than X-ray as it is non-invasive. Moreover, recent research shows successful revelation of contrast in THz images of skin cancer since tumor has different water content from healthy tissue. THz spectroscopy of breast cancer has also revealed difference between healthy breast adipose and fibrous tissues.

Currently, THz imaging systems are developed based on time-domain signal analysis with wide spectrum (0.1~10THz) generated by laser diode, where several drawbacks can be found. Firstly, the penetration depth and resolution are greatly limited by the high absorption coefficient of THz signal in the human tissue. Secondly, the implementation cost is very high as 2D array cost is high and also complex high-speed signal processing is required for the data acquisition and analysis in the time-domain. The above two issues could be overcome by the sub-THz imaging in the frequency domain with 40/65nm CMOS technology.

Asst. Prof. Yu Hao and his students are working on the development of THz imaging system. Compared to the other semiconductor technologies such as SiGe, InP or GaAs, standard CMOS technology is always considered as the cost-effective solution to integrate all digital, analog and RF components on one single chip. In recent years, with the advance scaling-down of CMOS technology, it becomes feasible to realize sub-THz signal transmitting and receiving system with CMOS on-chip solution. A CMOS transceiver operating in this frequency range could provide high penetration depth, high resolution with very low fabrication cost for 2D array and on-chip signal processing.

140GHz Regenerative Receiver with SRR loaded Resonator for hand-held security imagingSince firstly proposed by Armstrong in 1922, regenerative receiver has been widely used for many applications such as short-range wireless/optical communication and radar with simple structure, low power, and low cost. CMOS THz imager with regenerative technique can be demonstrated in 65nm CMOS with LC tank based oscillator. However, due to the limited Q factor of LC tank resonator, the sensitivity is limited as -74dBm. In this work, a metamaterial based split ring resonator (SRR) is utilized to improve the Q of resonator. And a regenerative receiver with SRR based oscillator is proposed to further improve the receiver sensitivity for the imager application. Post layout simulation results show that the proposed receiver can achieve -78dBm sensitivity and 0.28 NEP (Noise equivalent power) with 7.2mW power consumption.

280GHz Receiver with Wideband on-chip SIW Antenna for skin cancer diagnosticThe key challenges in the THz imaging are the huge path loss in human tissue due to absorption and small refraction index difference between normal and cancer cells. It has been shown that 0.3~0.5THz is a perfect spectrum for Vivo diagnostic of skin/breast cancer as it has low absorption coefficient about 100/cm-1 and largest refraction index difference between Tumor and Fibrous. However, high gain and wideband antenna is required to overcome the path loss and show good resolution for receivers in this frequency range with low cost. In this work, Substrate Integrated Waveguide Circular Polarized (SIWCP) Antenna is fabricated on chip with CMOS 65nm process together with down-conversion mixer and Power Gain Amplifier (PGA). The 280GHz signal received from antenna will be down-converted to 3GHz and amplified before detection. Post layout simulation results show that the proposed antenna has 1.0dB Gain and 21.5GHz bandwidth, and the receiver has 20dB conversion gain and -63dBm sensitivity.

Fig. 4 (a) 140GHz Regenerative Receiver design in 65nm CMOS process with SRR loaded Resonator. (b) 280GHz direct-conversion Receiver with Wideband on-chip SIWCP Antenna

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A 0.45V 100-channel Neural Recording IC for Neural Prosthesis

Assistant Professor Zheng Yuanjin

Conventional neural recording systems face limitations in achieving a good NEF and low power consumption simultaneously, because the input amplifier current consumption is dictated by input-referred noise requirement which determines the system sensitivity while the supply voltage is determined by dynamic range (DR) requirement at the analog recording chain output which limits the maximum achievable resolution of the A-to-D conversion. A power-efficient neural recording architecture using a DR-folding technique is proposed to enable low-voltage operation without compromising the DR performance. Asst. Prof. Zheng Yuanjin and his PhD student Mr. Han Dong, collaborating with Institute of Microelectronics, Singapore, have developed a 0.45V 100-channel neural recording IC with 0.73μW/Channel Consumption in 0.18μm CMOS. The proposed architecture optimizes overall power consumption (uses only 50% of typically required voltage) and occupies a very small area of 5mm × 5mm. The prototype IC was used to record the neural signal using a glass electrode in anesthetized Sprague-Dawley rat. A comparison with the other state-of-the-art neural recording ICs shows that the proposed multi-supply-voltage scheme and DR-folding technique allow their design to achieve sub-μW/channel power consumption and outstanding FOMs compared to other designs. This significant work is recently accepted to be presented at ISSCC 2013, a world most pretigious IC design conference.

Fig. 5 100-channel ultra-low power neural recording IC for neural prosthesis