Via Placement for Minimum Interconnect Delay inThree-Dimensional (3-D) Circuits

Vasilis F. Pavlidis and Eby G. FriedmanDepartment of Electrical and Computer Engineering, University of Rochester

Rochester, New York 14627, USA

Abstract- The propagation delay of interlayer 3-D intercon- been described in the literature [5]-[7]. The delay expres-nects is investigated in this paper. For RC interconnects sions included in these interconnect prediction models for 3-connecting two circuits located on different physical planes, the D circuits are similar to traditional CMOS models, neglect-interconnect delay is minimized by optimally placing the non- ing the impact ofthe vias. Zhang et al. [8] consider the effectstacked interlayer vias. The problem of determining these op- of the vertical vias on the interlayer interconnects in theirtimum via locations under the Elmore delay model is described delay expression; however, the via is assumed to be placed inas a geometric program. Simulations indicate delay improve- the middle of the line, independent of the line length andments of up to 26% for relatively short interconnects. The impedance, leading to significantly inaccurate delay estima-proposed approach is also compared with a wire sizing algo- tionmperithm. Timing-driven via placement exhibits better results both t [in terms of delay and power consumption.

Vertical Interlayer Interconnects (Vias) Intralayer Interconnects

1. INTRODUCTION Device layerThe performance of integrated circuits (ICs) can be enhanced - Device layerby technology scaling, producing smaller and faster devices; - Device layerlong interconnects, however, can significantly degrade thisimprovement. Repeater insertion and other design tech- 3rd Planeniques, such as wire sizing, have been developed to mitigate 2nd Planethese effects. As clock frequencies increase, however, boththe number and power of the buffers increase beyond where 1st Pla Bu& Cthere is no longer any performance benefit. To sustain per- s Ple B CMO

formance improvements in future technology generations,non-conventional design paradigms are required. Figure 1. Schematic of a three-dimensional circuit.

Three-dimensional (3-D) integration is such a promising To fully exploit the potential of 3-D circuits sophisti-alternative which offers the opportunity to relieve the delete- cated placement and routing algorithms are required [10],rious effects of long interconnects. Another important [1]. Due to the significance of thermal effects in 3-D cir-characteristic of 3-D structures is that these circuits can in- cuits, a thermal-driven algorithm for via placement wasclude various technologies such as GaAs and SiGe, and 'design disciplines such as analog, digital, and .MS within presented in[12]. These algorithms however do not addressa single 3-D multiplane system. Several research efforts have the savings idelay that can originate from the optimumfocused on developing manufacturing techniques for 3-D place whilersim s o nsidering1 1 * rr oA 1 *f' n * * - *11 1 non-uniform impedance characteristics of the mnterlayer mn-technologies [1-3]. A schematic of a 3-D circuit is illustrated terconnects. It is shown in [9] that considerable delay savingsin Fig. 1, where several physical planes are bonded with ad-hesive materials or metal padls [4]. Each physical plane of the ca .eahee hntevaloaini osdrddrnhesive materials or metal pads [4]. Each physical plane ofthe the routing process. In this paper, the results presented in [9]stack is similar to a conventional two-dimensional (2-D) are extended to more complicated structures such as vias thatcircuit, in that a plane includes a device layer and multiple cannot be stacked due to obstacles or other routed intercon-metal layers to connect individual circuits located on the nects.same physical plane (the intralayer interconnects). Intercon-nections among the physical planes (the interlayer In the following section, the problem of timing-driveninterconnects) are implemented by vertical through vias, placement of vias between interlayer interconnects in 3-Dwhich are called vias here for brevity. ICs is described. A delay expression for a 3-D interconnect

To evaluate the performance of three-dimensional cir- system as a function of the length of the interconnect seg-cuits, several a priori interconnect prediction models have ments is presented in Section 3. In Section 4, simulation

This research is supported in part by the Semiconductor Research Cor-poration under Contract No. 2003-TJ-1068 and 2004-TJ-1207, the NationalScience Foundation under Contract No. CCR-0304574, the Fulbright Pro-gram under Grant No. 87481764, a grant from the New York State Officeof Science Technology & Academic Research to the Center for AdvancedTechnology in Electronic Imaging Systems, and by grants from Intel Cor-poration, Eastman Kodak Company, and Manhattan Routing.

0-7803-9390-2/06/$20.00 ©2006 IEEE 4587 ISCAS 2006

results that demonstrate the decrease in interlayer intercon- different physical plane with length li. The vias are denotednect delay and power consumption achieved by optimally by the index of the first of the two connected segments. Forplacing the vias are presented along with a comparison with example, if a via connects segment i and i+1, the via is de-a wire sizing algorithm. Finally, some conclusions are of- noted as vi with length 4i. The total length of the line L isfered in Section 5. equal to the summation of the length of the horizontal seg-

ments and vias and can be written asII. PROBLEM FORMULATION

The primary contribution of this work is introduced in this L I++l I+ + (1)section. Consider the interlayer inteconnect shown in Fig. 2that consists of n horizontal segments connecting two In addition, the length of each horizontal segment iscircuits located m physical planes apart. Each of the bounded,horizontal segments of the line corresponds to a metal layerof some physical plane of the stack. The horizontal nsegments of the line are connected through the vias which limin Y. L - min (2)can traverse more than one plane. Consequently, the number j-1,j.iof horizontal segments of the line is smaller than or at most The lower bound in (2) results from the presence of obstaclesequal to the number of physical planes between the two that prohibit the placement of a via in certain locations, whilecircuits, i.e., m > n, where the equality applies when each of the upper bound is set such that only two circuits are con-the vias connects metal layers from two adjacent physical nected. If no obstacles exist, the minimum lengthplanes. requirement for the first and last segment is constrained by

In conventional 2-D circuits, a two terminal net such as the design rules that determine the distance between a cellthe structure shown in Fig. 2 is modeled as a line with uni- and a via, which are technology dependent. For the remain-form impedance characteristics, while the vias are either ing segments, the distance can be set to zero. Additionally,ignored or considered as lumped capacitive loads. The het- the upper bound can be changed as desired without alteringerogeneity of 3-D circuits, however, does not support a the proposed methodology.uniform line model. In 3-D systems, circuits from different The correspondin electrical model of the line is shownprocesses and disparate technologies are integrated onto a in Fig. 3. The tota rgesistancand ofcthe of a hownsingle multiplane system. The interlayer interconnect lines (tl) setotalgresistance andcapacitanceofa horizontalare therefore modeled as wire segments with non-uniform (vertical) segment i (v;) isRd(ot)e re(ss)l(ac)and Ca(,,ctace,1impedance characteristics. Due to the non-uniform imped- wherers(tv) and Ci(vi) denote the resistance and capacitance,ance characteristics of the line, the via locations or respectively, per unit length. The driver is modeledas a stepalternatively, the length of each horizontal wire segment input voltage and a linear resistance Rs, and the load stage asaffects the delay of the line. Thus, the objective is to place a capacitive load C. The Elmore delay of the line in matrixthe vias such that the interconnect delay is minimum. To form iSanalyze the delay of a line, the Elmore delay model has beenadopted due to the simplicity and high fidelity of this model. T(l) = 0.5 ITAl + bl + D (3)The accuracy of the model can be further improved as dis-cussed in [13]. Interconnects that exhibit inductive behaviorare not addressed in this paper. The analysis of the optimum wherevia placement problem is presented in the following section.

inL I =t[i 12 ...T1st In1 ]T (4)Ik

Re-ceive-r

Driver E LrlCl rlC2 *.- r (C> ol L=ll+lvl+ +li+ +lh+ +ln | ~~~~~A=L (5)

[r1cn r2Cn. rnjCnFigure 2. Interlayer interconnect consisting ofn segments and connecting

two circuits located m planes apart.

III. OPTIMUM VIA PLACEMENTTr{ E cv1IV + CL J+ C, RS |In this section, the optimum via location problem is dis- b= .(6)cussed. Consider again the interlayer interconnect shown in rn-+~R~ lFig. 2. Each horizontal segment i of the line is located on a rn L +Cy s + .rvivi)

4588

n-I n-I 1 n-I TABLE I. Delay savings by optimum via placement. The resistance andRSYcvilvi + CL IE l -+-E rviCvil, + RSCL (7) capacitance per unit length of the vias is r,i = 6.7 Q/mm and CVi = 6 pF/mm,

i=1 i=1 2 i1 respectively. The length of the vias is 4,i 20 ptm. The driver resistance isRs 15 Q and the load capacitance is CL 50 fF.

RS r1, C1Tl c1 - - riT3 rc Ie r7 Cn Length Tei (equally Tel1 [ps] Improvement n

[mm] spaced) [ps] [%]Vs TL T T T T1 1.560 56.11 52.40 7.08 10

17W Tr CL1.609 58.78 53.15 10.59 10I- - - -- - - l2.383 75.00 64.11 16.99 10

1.665 60.36 50.10 20.48 10Figure 3. Interlayer interconnect model composed of a set of non- 1.749 63.10 52.4220.37 10

uniformly distributed RC segments. 1.233 35.92 33.11 8.49 71.167 34.97 31.43 10.12 7

Since (7) is a constant quantity, the optimization problem can 1.132 34.26 30.28 11.62 7be described as follows, 1.933 45.23 34.65 23.39 7

1.716 46.18 37.18 19.49 7(P) min. T(l) = 0.5 ITAl + bl 2.428 29.03 23.89 17.71 4

subject to (1)and (2). 1.875 44.28 38.73 12.53 4subjectto (1) and (2). 2.121 34.56 25.62 25.86 4

The primal problem (P) is a quadratic programming problem, 3.429 56.11 42.47 24.31 4which in general is not convex. Applying a variable trans- 1.701 27.34 25.69 6.03 4formation, (P) is converted to a convex optimization problem Average Improvement 15.67[14]. Problem (P) can be effectively solved through geomet-ric programming [15]. In the following section, simulation Wire sizing is a well-known technique to reduce the in-results and a comparison with a wire sizing algorithm in terconnect delay. Wire shaping, however, is not alwaysterms of the delay and power consumption are presented. feasible due to routing congestion or obstacles such as placed

cells. Additionally, as the interconnect is tailored to lowerthe interconnect resistance, the capacitance and, conse-

IV. SIMULATION RESULTS quently, the power consumption of the interconnectIn this section, the improvement in delay and the decrease in increases. The wire sizing algorithm described in [18] haspower consumption achieved by optimally placing the vias been applied to several interconnects to improve the lineare demonstrated. The interlayer interconnects for various delay. The interconnect length is divided equally among thenumbers of physical planes are analyzed. The impedance horizontal segments that constitute the interconnect. For thecharacteristics of the horizontal segments and vias are ex- same interconnects, the line delay where the width is mini-tracted for several interconnect structures using a mum and the vias are optimally placed is also determined.commercial impedance extraction tool [16]. Based on the In Fig. 4, the average interconnect delay for the optimumextracted impedances, the resistance and capacitance of the via placement and wire sizing technique is shown. The in-horizontal segments range from 5 Q/mm to 25 Q/mm and stance where the optimum via placement outperforms wirefrom 100 fF/mm to 300 fF/mm, respectively. Copper inter- sizing (and vice versa) is depicted. The average delay im-connect has been assumed. For each horizontal segment, the provement ranges from 6.23% for n = 4 to 17.8% for n = 5,lower bound in (2) is randomly generated. For simplicity, all justifying that via placement can reduce delay in interlayerof the vias connect the segments of two adjacent physical interconnects in 3-D circuits without requiring additionalplanes. The delay of the line, where the total line length is area. The primary reason wire sizing does not significantlydivided equally among the horizontal segments, is compared reduce delay is due to the via impedance characteristics andto the line delay where the vias are optimally placed. These because the vias cannot be sized as aggressively as the hon-via locations or, alternatively, the length of the horizontal zontal segments. Furthermore, via sizing is not desirable assegments are obtained solving (P) with a generic optimiza- wider vias decrease the via density or, equivalently, thetion solver YALMIP that also supports geometric programs number of interlayer interconnects that can be routed[17]. throughout the 3-D system. In Fig. 5, the normalized average

SPICE delay measurements are reported in Table 1. Note power consumption (NAPC) for various interconnects isthat the variation in delay improvement changes significantly illustrated. The crosshatched bar corresponds to intercon-for the listed instances even when the interconnect lengths nects of minimum width and horizontal segments of equalare similar. Depending upon the impedance characteristics of length. The white bar considers those interconnects wherethe line segments, the equally spaced via placement is a near the horizontal segments are of equal length and wire sizingoptimal case for certain instances, explaining why the delay has been applied. The NAPC where the line segments are ofimprovement is not significant for those instances. From minimum width and optimum length is depicted by the grayTable 1, delay improvements of up to 260% are observed for bar. The proposed technique exhibits a lower power con-relatively short interconnects. sumption as compared to the other two cases. The

aforementioned wire sizing increases the capacitance of the

4589

line, resulting in a greater NAPC than the optimum via REFERENCESplacement technique. Note that although the NAPC is the [1] R. J. Gutmann et al., "Three-dimensional (3D) ICs: A Technologylowest for optimally placing the vias, the capacitance and Platform for Integrated Systems and Opportunities for Newtherefore the NAPC is not minimum as the time constant for Polymeric Adhesives," Proceedings of the Conference on Polymersthe interconnect also depends upon the resistance of the line. and Adhesives in Microelectronics and Photonics, pp. 173-180,Due to this dependency, the capacitance is not minimized to October 2001.avoid an increase in the interconnect resistance. Note that the [2] L. Xue, C. Liu, and S. Tiwari, "Multi-layers With Buried Structuresreduction in NAPC is of considerable importance due to pro-

(MLBS): An Approach to Three-dimensional Integration,"reductionin NAPC is of considerable importance due to pro- Proceedings of the IEEE International Conference on Silicon Onnounced thermal effects in 3-D circuits [19]. Insulator, pp. 117-118, October 2001.

35 40 [3] M. Koyanagi et al., "Future System-on-silicon LSI Chips," IEEEM Wire sizing Micro, Vol. 18,No. 4, pp 17-21, July/August 1998.

303

0 timum via lacement[4] A. Fan, A. Rahman, and R. Reif, "Copper Wafer Bonding,"3025 a | ffi Tm aeElectrochemical and Solid-State Letters, Vol. 10, No. 2, pp. 534-536,w 25 -, October 1999.

20 W. eofoCE-0D [5] J. W. Joyner el al., "Impact of Three-dimensional Architectures on

[7U.Sroad)ndJ a apnot "Etrmatnsacntironsneryio

U,20 Interconnects in Gigascale Integration," IEEE Systems onIEr10 >o Large Scale Integration (VLSI) Systems, Vol. 9, No. 6, pp. 922-927,

E 15 CD December 2000.rniFigure 4.Cmarsnofteaerg lmr elybsd nwreszn0 [6] A. Rahman and R. Reif, "System-level Performance Evaluation ofCY)

oi v Three-dimensional Integrated Circuits," IEEE Transactions on Veryvia>placementperformsthebestasATm pared to wiresizing(andviELarge Scale Integration (VLSI) Systems, Vol. 8, No. 6, pp. 671-678,

<5

-10 ~~~~~~~~~~~~~~December2000.[7] D. Stroobandt and J. van Campenhout, "Estimating Interconnection

4 5 7 0 T20 Length in Three-dimensional Computer Systems," IEICENumber of physical planes, nE Transactions on Information and Systems, Vol. 80, No.10, pp. 1024-

103 1, October 1997.

Figure 4. Comparison of the average Elmore delay based on wire sizing [8] R. Zhang et al., "Stochastic Modeling, Power Trends, andandopimuvalacmetechiqesThistnce wheretPerformance Characterization of 3-D Circuits," IEEE Transactions on

an piu i lcmn ehnqe.Teisac hrh optmu Elecrksonpeie,Vl8,pNop414-4, pp.l1963.-5,Api01

via placement performs the best as compared to wire sizing (and vice Eeto eie,Vl 8 o ,p.6 -5,Arl201versa) is also depicted. [9] V. F. Pavlidis and E. G. Friedman, "Interconnect Delay Minimization

through Interlayer Via Placement," Proceedings of the ACM GreatLakes Symposium on VLSI, pp. 20-25, April 2005.

3 45 5 710[10] C. C. Tong and C.-L. Wu, "Routing in a Three-dimensional Chip,"C3.0 El Minimum width - equal length IEEE Transactions on Computers, Vol. 44, No. 1, pp. 106-117,

and equal Wire sizing - equal length January 1995.E E Minimum width - optimum length

2.5 [11] A. Cohoon et al., "Physical Layout for Three-DimensionalMFPGAs," Proceedings of the ACMInSGDA Physical Design2Workshop, pp. 142-149, April 1996.

[12] J. Cong, J. Wei, and Y. Zhang, "A Thermal-Driven FloorplanningTh 1.5 Algorithm for 3D ICs," Proceeding of the IEEEIACM Conference onbetween theintrlayerintercnnects f3-D ircuit1Sex-IEEE/AMInterationalConfernceoComputer Aided Design, pp. 306-313, November 2004.

1.0 [13] Al. Abou-Seido, B. Nowak, and C. Chu, "Fitted Elmore Delay: ASimple and Accurate Interconnect Delay Model," IEEE Transactions

Ea0.5 on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 7, pp.z ~~~~~~~~~~~~~~~~~~~~691-696, July 2004.

4 5 10[14] J. G. Ecker, "Geometric Programming: Methods, Computations andNumber of physical planes, n Applications," SIAMReview, Vol. 22, No. 3, pp. 33 8-362, July 1980.

[15] 5. Boyd, S. J. Kim, L. Vandenberghe, and A. Hassibi, "A Tutorial on

Figur 5. ormalzedverag powr cosumpton fr minmum idthGeometric Programming," Optimization and Engineering (in press).and equal length, wire sizing and equal length, and minimum width and [16] Metal User's Guide, www.oea.com

optimum via placement. [17] J. Lofberg, "YALMIP: A Toolbox for Modeling and Optimization inMATLAB," Proceedings of IEEE International Symposium onComputer-Aided Control Systems Design, pp. 284-289, September

V. CONCLUSIONS 2004.

Theadelay savings resulting from optimally placing the vias [18] C-P. Che, H. Zhou, and D. F. Wong, "Optimal Non-Uniform Wire-The elaysavigsrsultng fom otimaly pacin theviasSizing Under the Elmore Delay Model," Proceedings of thebetween the interlayer interconnects of 3 -D circuits is ex- IEEEIACMInternational Conference on Computer-Aided Design, pp.plored. Simulation results indicate that optimum via 3 8-43, November 1996.placement considerably lowers the interconnect delay. In [19] C.C. Liu, J. Zhang, A.K. Datta, and S. Tiwari, "Heating Effects of

cuits.

4590