VHDL Project I:VHDL Project I:Introduction to Introduction to

Testbench DesignTestbench Design

Matthew MurachMatthew Murach

Slides Available at: www.pages.drexel.edu/~

mjm46

Goals for this Goals for this Lab/AnnouncementsLab/Announcements

Finish up the design of the Shift Finish up the design of the Shift Registers, Controller, and Packaging Registers, Controller, and Packaging by the end of today. by the end of today.

Start on the testbench design layout.Start on the testbench design layout. The first quiz will be given next The first quiz will be given next

week and will cover materials week and will cover materials covered in the first few labs as well covered in the first few labs as well as chapters 1,2 in the text. as chapters 1,2 in the text.

Testbench DescriptionTestbench Description

A testbench is a tool used by VHDL A testbench is a tool used by VHDL designers to ensure timing, designers to ensure timing, correctness, and to speed up testing.correctness, and to speed up testing.

Usually the testbench will contain Usually the testbench will contain several user defined test vectors. several user defined test vectors.

Previously you had to force signals Previously you had to force signals and setup the clock. A testbench sets and setup the clock. A testbench sets this up for you.this up for you.

Testbench LayoutTestbench Layout

A testbench is just a basic VHDL file with A testbench is just a basic VHDL file with a few more features.a few more features.

A major difference is that a testbench will A major difference is that a testbench will NOT have any port declarations in the NOT have any port declarations in the entity section. This is because a entity section. This is because a testbench generates all the signals for the testbench generates all the signals for the design. design.

Several constants will be needed however Several constants will be needed however such as the length of the test vectors and such as the length of the test vectors and the number of vectors in the design.the number of vectors in the design.

Architecture SectionArchitecture Section

You will most likely want to use at least three You will most likely want to use at least three vectors for testing. To accomplish this, you vectors for testing. To accomplish this, you will need to declare a logic type.will need to declare a logic type.

You’ll need an array of the std_logic_vector You’ll need an array of the std_logic_vector type. This can be declared as the following:type. This can be declared as the following:

Type my_array is array(natural range <>) of std_logic_vector(N-Type my_array is array(natural range <>) of std_logic_vector(N-1 downto 0);1 downto 0);

-- Declare test vectors for A and B-- Declare test vectors for A and B

My_A : my_array(n_of_tests-1 downto 0) := My_A : my_array(n_of_tests-1 downto 0) := ("1011","1100","0110");("1011","1100","0110");

My_B : my_array(n_of_tests-1 downto 0) := My_B : my_array(n_of_tests-1 downto 0) := ("1011","1100","0110");("1011","1100","0110");

Architecture Section Architecture Section (cont)(cont)

Just like the VHDL file you created Just like the VHDL file you created for connecting the components for connecting the components together, you must declare and together, you must declare and map this master to your testbench. map this master to your testbench.

You will also need to declare the You will also need to declare the port mappings for the master to port mappings for the master to internal wirings of the testbench. internal wirings of the testbench.

Architecture Section Architecture Section (cont) (cont)

In this design you defined a clock so In this design you defined a clock so you will need to generate this clock you will need to generate this clock signal inside the testbench. signal inside the testbench.

-- Clock Definition (place after the 1-- Clock Definition (place after the 1stst begin)begin)

clk <= not clk after 50 ns;clk <= not clk after 50 ns;

This tells the clock to operate at 100 This tells the clock to operate at 100 MHz or change states every 50 ns.MHz or change states every 50 ns.

New Features in New Features in TestbenchTestbench

User defined timing with “after”User defined timing with “after”-- Waits for a user defined time in this case 350 ns to assign b to a-- Waits for a user defined time in this case 350 ns to assign b to a

a <= b after 350 ns;a <= b after 350 ns;

Error reporting with assert/reportError reporting with assert/report

assert (condition) report “message”assert (condition) report “message”-- printout the word mismatch if a != b-- printout the word mismatch if a != b

assert ( a = b) report “mismatch”;assert ( a = b) report “mismatch”;

Notice that assert takes a boolean Notice that assert takes a boolean expression and reports only if that expression and reports only if that expression is false.expression is false.

State Machine State Machine Description Description

The testbench you will be designing The testbench you will be designing will implement 4 states:will implement 4 states:

Assign – Loads the a test vector into Assign – Loads the a test vector into the serial adder.the serial adder.

Waiting – Waits until the serial adder Waiting – Waits until the serial adder finishesfinishes

Check – Checks the answer against Check – Checks the answer against IEEE library callIEEE library call

Done – After the number of user Done – After the number of user defined test patterns is finished the defined test patterns is finished the program tells the user it is done.program tells the user it is done.

Testbench State DiagramTestbench State Diagram

Assign Waiting

CheckDone

Go = ‘1’ and Rst = ‘1’ Time < 2N clocks

Rst = ‘0’

Time >= 2N clocksTests < N_of_tests

Tests = N_of_tests