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VHDL Primer Summary (Chapter 1 - 4)

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  • 7/27/2019 VHDL Primer Summary (Chapter 1 - 4)

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    CHAPTER 1

    VHDL (Very High Speed Integrate Circuits Hardware Description Language)

    - A hardware description language that can be used to model a digital system at manylevels of abstraction ranging from the algorithmic level to the gate level

    - An amalgamation of the following language: sequential + concurrent + net-list + timingspecifications + waveform generation

    Capabilities:

    - Can be used as an exchange medium between chip vendors and CAD tool users- Can be used as a communication medium between different CAD and CAE tools- Supports hierarchy- Supports flexible design methodologies: top-down, bottom-up or mixed- Not technology-specific, but is capable of supporting technology-specific features- Supports both synchronous and asynchronous timing models- Can model finite-state machine descriptions, algorithmic descriptions and Boolean

    equaltions

    - Publicly available, human readable, machine readable and above all not proprietary- An IEEE and ANSI standard and therefore, models described using this language are

    portable

    - Supports three basic different description styles: structural, dataflow and behavioral tovery precise gate-level descriptions

    - Support a wide range, of abstraction levels ranging from abstract behavioraldescriptions to very precise gate-level descriptions

    - Arbitrarily large designs can be modeled using the language and there are no limitations- Makes large scale design modeling easier- No need to learn a different language for simulation control- Delays and timing constraints can be described- Facilitates back-annotation- Parameterized designs- Contains information about the design itself- Common language can be used to describe library components from different vendors- Precise simulation semantics are defined- Capable of being synthesized to gate-level descriptions- Capability of defining new data types

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    CHAPTER 2

    Five different types of primary contructs/design units:

    1. Entity declaration - external view of the entity2. Architecture body - internal description of the entity3. Configuration declaration - used to create a configuration for an entity4. Package declaration - encapsulates a set of related declarations such as type

    declarations, subtype declarations and subprogram declarations

    5. Package body contains the definitions of subprograms declared in a packagedeclaration

    The simulator simulates an entity, represented by an entity-architecture pair or by a configuration,

    by reading in its compiled description from the design library and then performing the followingsteps:

    1. Elaboration2. Initialization3. Simulation

    The language syntax is casc-iriSRissitive.

    The internal details of an entity are specified by an architecture body using any of the following

    modeling styles:

    1. As a set of interconnected components (to represent structure),

    2. As a set of concurrent assignment statements (to represent dataflow),

    3. As a set of sequential assignment statements (to represent behavior),

    4. Any combination of the above three.

    The architecture body is composed of two parts: the declarative part (before the keyword begin)

    and the statement part (after the keyword begin).

    A configuration declaration is used to select one of the possibly many architecture bodies that

    an entity may have, and to bind components, used to represent structure in that architecture body,

    to entities represented by an entity-architecture pair or by a configuration, that reside in a design

    library.

    A package declaration is used to store a set of common declarations like components, types,

    procedures, and functions.

    A package body is primarily used to store the definitions of functions and procedures that were

    declared in the corresponding package declaration, and also the complete constant declarations for

    any deferred constants that appear in the package declaration.

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    A simulation can be performed on either one of the following:

    - anentity declaration and an architecture body pair,- a configuration.

    Preceding the actual simulation are two major steps:

    1. Elaboration phase: In this phase, the hierarchy of the entity is expanded and linked,

    components are bound to entities in a library and the top-level entity is built as a network

    of behavioral models that is ready to be simulated. Also, storage is allocated for all data

    objects (signals, variables, and constants) declared in the design units. Initial values are

    also assigned to these objects.

    2. Initialization phase: The effective values for all explicitly declared signals are computed,

    implicit signals (discussed in later chapters) are assigned values, processes are executed

    once until they suspend, and simulation time is reset to 0 ns.

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    CHAPTER 3

    Basic Language Elements:

    1. Identifierscomposed of a sequence of one or more characters2. Data Objectshold a value of a specified type

    a. Constantb. Variablec. Signal

    3. Data Typeshold a value that belongs to a set of valuesa. Subtypea type with a constraintb. Scalar Typesrelational operators can be used on these values

    i. Enumeration has a set of user-defined values consisting of identifierand character literals

    ii. Integerset of values which fall within a specified integer rangeiii. Physicalvalues that represent measurement of some physical quantityiv. Floating point set of values in a given range of real numbersc. Composite Typesrepresents a collection of valuesi. Array Typecollection of values all belonging to a single type

    ii. Recordcollection of values that may belong to same or different typesd. Access Typespointers to a dynamically allocated objects of some other type

    i. scalar-obj-ptr-allii. array-obj-ptr (element index)

    iii. record-obj-ptr.element-namee. Incomplete Typeshas elements which are also access typesf. File Typesrepresents files in the host environment

    4.

    Operatorsa. Logical operators (and or nand nor xor not)b. Relational operators (= /= < >=)c. Adding operators (+ - &)d. Multiplying operators (* / mod rem)e. Miscellaneous operators (abs **)

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    CHAPTER 4

    Behavioral Modeling:

    1. Entity Declarationexternal interface of the entitya. in: the value of an input port can only be read within the entity modelb. out: the value of an output port can only be updated within the entity model; it

    cannot be read

    c. inout: the value of a bidirectional port can be read and updated within the entitymodel

    d. buffer: the value of a buffer port can be read and updated within the entity model2. Architecture Bodydescribes the internal view of the entity3. Process Statement contains sequential statements that describe the functionality of a

    portion of an entity in sequential terms

    4. Variable Assignment Statement5. Signal Assignment Statement

    a. Inertial Delay Modelmodels the delays often found in switching circuitsb. Transport Delay Modelmodels the delays in hardware that do not exhibit anyintertial delay

    c. Creating Signal Waveformsd. Signal Drivers

    6. Wait Statement alternate way to suspend the execution of a processa. wait onb. wait untilc. wait for

    7. If Statement selects a sequence of statements for execution based on the value of acondition8. Case Statement selects one of the branches for execution based on the value of theexpression

    9. Null Statementdoes not cause any action to take place and execution continues withthe next statement

    10.Loop Statement used to iterate through a set of sequential statement11.Exit Statement causes execution to jump out of the innermost loop or the loop whose

    label is specified

    12.Next Statement results in skipping the remaining statements in the current iterationof the specified loop and execution resumes with the first statement in the next iteration

    of this loop

    13.Assertion Statement useful in modeling constraints of an entity14.Sequential Statements

    a. Procedure call statementb. Return statement

    15.Multiple Processes


1 VHDL for Synthesis Summary notes from: Appendix A: Synthesis The Designer’s Guide to VHDL, 2 nd Ed

1 VHDL for Synthesis Summary notes from: Appendix A: Synthesis The Designer’s Guide to VHDL, 2 nd Ed

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