VHDL Material by Mohamed Adly

Digital design

Digital design using hardware description language(HDL)

Digital world

Digital world in 2050

https://www.youtube.com/watch?v=msJ0ubFlasE




Design methodologies

Ad-hoc

Structured

- Top-Down

- Bottom-Up

- Mixed

Why structured design?

Over a million-transistor designs cannot be done easily

- Today’s designs require better tools

- Today’s designs require better planning

- Today’s designs require better strategy

From concept to silicon

Algorithmic design

Architecture design

Logic (gate) design

Circuit (transistor) design

Physical (layout) design

Verification must be done at

each phase.

Tape-out

Concept

Why using HDL?

Very difficult to design directly on hardware

Exploring different design options

- Easier

- Cheaper

Lower time and cost than prototyping

CAD support from concept to silicon

Key features of HDLs

HDLs have high-level programming language constructs

HDLs allow designers to describe their designs at different levels of abstraction

HDLs allow designers to describe functionality as well as timing

HDLs are concurrent languages in nature

VHDL vs. Verilog

Government

Developed

Commercially

Developed

Ada based C based

Strongly Type Cast Mildly Type Cast

Difficult to learn Easy to Learn

More Powerful Less Powerful

Designs must be sent for expensive and time consuming fabrication in semiconductor foundry

Bought off the shelf and reconfigured by designers themselves

Two competing implementation approaches

ASIC Application Specific

Integrated Circuit

FPGA Field Programmable

Gate Array

Designed all the way from behavioral description to physical layout

No physical layout design; design ends with a bitstream used to configure a device

Low cost (but only in high volumes)

Low power

High performance

Reconfigurability

Short time to the market

Low development costs

Off-the-shelf

ASICs vs. FPGAs

ASIC and FPGA flow

Specs

Fabrication

RTL Description

Functional Verification

Synthesis

Physical Layout (Place & Route)

System Level Design

Gate Level Simulation

Front End

Back End

Configuration

ASIC FPGA

Specification

VHDL description

Functional sim.

Synthesis

Implementation

Configuration

Timing sim.

On chip testing

Post-synthesis

sim.

Logic synthesis

RTL code (Verilog/

VHDL)

Constraints

Logic synthesis

Gate-level netlist

(Verilog/ VHDL)

Area report Timing report Power consumption report

Logic synthesis(Cont.)

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY flipflop IS

PORT ( D, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC

) ;

END flipflop ;

ARCHITECTURE Behavior_1 OF flipflop IS

BEGIN

PROCESS ( Clock )

BEGIN

IF Clock'EVENT AND Clock = '1' THEN

Q <= D ;

END IF ;

END PROCESS ;

END Behavior_1 ;

D Q

Clock

Synth

esis

Review of digital system structure

Structure of a typical digital system

Execution Unit

(Data path)

Control Unit

(Control)

Data Inputs

Data Outputs

Control Inputs

Control Outputs

Control Signals

Structure of a typical digital system(Cont.)

Execution unit (Data path)

Manipulates and processes data

Interprets control signals from the Controller and generates status signals for the Controller

Provides all necessary resources and interconnects among them to perform specified task

Examples of resources

– Adders, multipliers, registers, memories, etc.

Structure of a typical digital system(Cont.)

Control Unit (Controller)

Controls data movements in an operational circuit by switching multiplexers and enabling or disabling resources

Follows some ‘program’ or schedule

Often implemented as finite state machine

or collection of finite state machines

Structure of a typical digital system(Cont.) Control Unit (Cont.)

Controller can be programmable or non-programmable

Programmable

– Has a program counter which points to next instruction

– Instructions are held in a RAM or ROM externally

– Microprocessor is an example of programmable controller

Non-Programmable

– Once designed, implements the same functionality

– Another term is a “hardwired state machine” or “hardwired instructions”

Finite state machines refresher

Any circuit with memory Is a finite state machine – Even computers can be viewed as huge FSMs

Design of FSMs involves – Defining states

– Defining transitions between states

– Optimization / minimization

Above approach is practical for small FSMs only

Finite state machines refresher(Cont.)

Moore FSM Output is a function of a present state only

Present state register

Next State function

Output function

Inputs

Present State Next State

Outputs

clock reset


Mealy FSM Output is a function of a present state and inputs

Next State function

Output function

Inputs

Present State Next State

Outputs

Present State Register

clock reset


Moore vs. Mealy FSM

Moore and Mealy FSMs can be functionally equivalent – Equivalent Mealy FSM

can be derived from Moore FSM and vice versa

Mealy FSM has richer description and usually requires smaller number of states – Smaller circuit area

state 1 / output 1

state 2 / output 2

transition condition 1

transition condition 2

state 1 state 2

transition condition 1 / output 1

transition condition 2 / output 2

Finite state machines refresher(Cont.) Moore vs. Mealy FSM(Cont.)

Mealy FSM computes outputs as soon as inputs change

– Mealy FSM responds one clock cycle sooner than equivalent Moore FSM

Moore FSM has no combinational path between inputs and outputs

– Moore FSM is more likely to have a shorter critical path


Sequence ”10” recognizer example

Moore FSM that recognizes sequence “10”

S0 / 0 S1 / 0 S2 / 1

0 0

0

1

1 1

reset

Meaning of states:

S0: No elements of the sequence observed

S1: “1” observed


Finite state machines refresher(Cont.) Sequence “10” recognizer example(Cont.)

Mealy FSM that recognizes sequence “10”

S0 S1

0 / 0 1 / 0 1 / 0

0 / 1 reset

Meaning of states:

S0: No elements of the sequence observed


Finite state machines refresher(Cont.) Sequence “10” recognizer example(Cont.)

clock

input

Moore

Mealy

0 1 0 0 0

S0 S1 S2 S0 S0

S0 S1 S0 S0 S0

C z 1 =

resetn

B z 0 = A z 0 = w 0 =

w 1 =

w 1 =

w 0 =

w 0 = w 1 =

A

w 0 = z 0 =

w 1 = z 1 = B w 0 = z 0 =

resetn

w 1 = z 0 =


Sequence ”11” recognizer example

VHDL

VHDL

VHDL is a language for describing digital hardware used by industry worldwide

VHDL is an acronym for VHSIC (Very High

Speed Integrated Circuit) Hardware

Description Language

Genesis of VHDL

Multiple design entry methods and hardware description languages in use

No or limited portability of designs between CAD tools from different vendors

Objective: shortening the time from a design concept to implementation

Different uses of VHDL

VHDL for Specification

VHDL for Simulation

VHDL for Synthesis

Features of VHDL

Technology/vendor independent

Portable

Reusable

Two points of view for a given component

External view of component as seen by others

Multiple internal views describing component function

Design entity

Design Entity - most basic building block of a design.

One entity can have

many different architectures.

Entity

Declaration

Architecture 1

Architecture 2

Architecture 3

Design Entity

Entity declaration

Entity Declaration describes the interface of the component, i.e. input and output ports.

ENTITY nand_gate IS

PORT(

a : IN STD_LOGIC;

b : IN STD_LOGIC;

z : OUT STD_LOGIC

);

END nand_gate;

Reserved words

Entity name Port names Port type

Semicolon

No Semicolon

Port modes (data flow directions)

Simplified syntax of entity declaration

ENTITY entity_name IS PORT ( port_name : signal_mode signal_type; port_name : signal_mode signal_type; …………. port_name : signal_mode signal_type); END entity_name;

Architecture

Describes an implementation of a design entity.

Architecture example:

ARCHITECTURE model OF nand_gate IS

BEGIN

z <= a NAND b;

END model;

Simplified syntax of architecture

ARCHITECTURE architecture_name OF entity_name IS [ declarations ] BEGIN code END architecture_name;

Entity declaration and architecture LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC ); END nand_gate; ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model;

nand_gate.vhd

Naming and labeling

VHDL is not case sensitive

Example:

Names or labels

databus

Databus

DataBus

DATABUS

are all equivalent

Naming and labeling (Cont.)

General rules of thumb 1. All names should start with an alphabet character (a-z or A-

Z) 2. Use only alphabet characters (a-z or A-Z) digits (0-9) and

underscore (_) 3. Do not use any punctuation or reserved characters within a

name (!, ?, ., &, +, -, etc.) 4. Do not use two or more consecutive underscore characters

(__) within a name (e.g., Sel__A is invalid) 5. All names and labels in a given entity and architecture must

be unique

Free format

VHDL is a “free format” language

No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way. Example:

if (a=b) then

or if (a=b) then

or if (a =

b) then

are all equivalent

Comments

Comments in VHDL are indicated with a “double dash”, i.e., “--”

- Comment indicator can be placed anywhere in the line

- Any text that follows in the same line is treated as a comment

- Carriage return terminates a comment

- No method for commenting a block extending over a couple of lines

Examples:

-- main subcircuit

Data_in <= Data_bus; -- reading data from the input FIFO

Comments(Cont.)

Explain function of module to other designers

Explanatory, not just restatement of code

Locate close to code described

– Put near executable code, not just in a header

INOUT mode

OUT mode

IN mode

Port modes

a

Entity Port signal

Driver resides outside the entity

Entity

Port signal

Driver resides inside the entity

Can’t read out within an entity

z

c <= z

c

Signal can be read inside the entity

Entity Port signal

Driver may reside both inside and outside the entity

a

OUT mode with signal

BUFFER mode

Port modes(Cont.)

Signal can be read inside the entity

Port signal

Entity


x

c

z

z <= x c <= x

Entity

Port signal


Port signal Z can be read inside the entity

c

z

c <= z

Port modes(Cont.)

In: Data comes in this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment.

Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment.

Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.

Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator

Library declarations

Use all definitions from the package std_logic_1164

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC ); END nand_gate; ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model;

Library declaration

Syntax of library declaration

LIBRARY library_name; USE library_name.package_name.package_parts;

Fundamental parts of a library

LIBRARY

PACKAGE 1 PACKAGE 2

TYPES CONSTANTS FUNCTIONS

PROCEDURES COMPONENTS

TYPES CONSTANTS FUNCTIONS

PROCEDURES COMPONENTS

Libraries

Ieee

Std

work

Need to be explicitly declared

Visible by default

Specifies multi-level logic system, including STD_LOGIC, and STD_LOGIC_VECTOR data types

Specifies pre-defined data types (BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc.

Current designs after compilation

STD_LOGIC type

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC ); END nand_gate; ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model;

What is STD_LOGIC you

ask?

STD_LOGIC type demystified

Value Meaning

‘U’ Not Initialized

‘X’ Forcing (Strong driven) Unknown

‘0’ Forcing (Strong driven) 0

‘1’ Forcing (Strong driven) 1

‘Z’ High Impedance

‘W’ Weak (Weakly driven) Unknown

‘L’ Weak (Weakly driven) 0.

Models a pull down.

‘H’ Weak (Weakly driven) 1.

Models a pull up.

‘-’ Don't Care

STD_LOGIC type demystified(Cont.)

‘1’

‘0’

‘X’

Contention on the bus

Value of all signals at the beginning of simulation Value of all signals that remain un-driven throughout simulation

U

X


Z

0

VDD

‘H’

‘0’

‘1’

‘L’


VDD


Do not care. Can be assigned to outputs for the case of invalid inputs(may produce significant improvement in resource utilization after synthesis). Use with caution

‘-’

Resolving of STD_LOGIC levels

X 0 1 Z W L H -

X X X X X X X X X

0 X 0 X 0 0 0 0 X

1 X X 1 1 1 1 1 X

Z X 0 1 Z W L H X

W X 0 1 W W W W X

L X 0 1 L W L W X

H X 0 1 H W W H X

- X X X X X X X X

Signals

SIGNAL a : STD_LOGIC;

SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0);

wire

a

bus

b

1

8

Standard logic vectors SIGNAL a: STD_LOGIC ; SIGNAL b: STD_LOGIC_VECTOR( 3 DOWNTO 0); SIGNAL c: STD_LOGIC_VECTOR( 3 DOWNTO 0); SIGNAL d: STD_LOGIC_VECTOR( 7 DOWNTO 0); SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL f: STD_LOGIC_VECTOR( 8 DOWNTO 0); ………. a <= ‘1’; b <= ”0000”; -- Binary base assumed by default c <= B”0000”; -- Binary base explicitly specified d <= ”0110_0111”; -- You can use ‘_’ to increase readability e <= X”AF67”; -- Hexadecimal base f <= O”723”; -- Octal base

Vectors and concatenation

SIGNAL a : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0); a <= ”0000”; b <= ”1111”; c <= a & b; -- c <= ”00001111” d <= ‘0’ & ”0001111”; -- d <= ”00001111” e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &‘1’ & ‘1’; -- e <= ”00001111”

Fixed 16-bit rotation example

a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0)

a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13)

<<< 3

a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) a(12) a(11)

<<< 5

Fixed 16-bit rotation example(Cont.)

LIBRARY ieee ;


ENTITY fixed_rotator_left_16 IS

GENERIC ( L : INTEGER := 1);

PORT ( a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

y : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

) ;

END fixed_rotator_left_16 ;

ARCHITECTURE dataflow OF fixed_rotator_left_16 IS

BEGIN

y <= a(15-L downto 0) & a(15 downto 15-L+1);

END dataflow ;

VHDL design styles

Components and interconnects

Structural

VHDL Design Styles

Dataflow

Concurrent statements

Behavioral

Registers State machines Test benches

Sequential statements

Subset most suitable for synthesis

XOR3 Example Entity

ENTITY XOR3 IS

PORT(

A : IN STD_LOGIC;

B : IN STD_LOGIC;

C : IN STD_LOGIC;

RESULT : OUT STD_LOGIC

);

END XOR3; A

B

C

RESULT XOR3

XOR3 Example(Cont.)

Dataflow architecture

ARCHITECTURE XOR3_DATAFLOW OF XOR3 IS SIGNAL U1_OUT: STD_LOGIC; BEGIN U1_OUT <= A XOR B; RESULT <= U1_OUT XOR C; END XOR3_DATAFLOW;

Dataflow description

Describes how data moves through the system and the various processing steps.

Data Flow uses series of concurrent statements to realize logic. Concurrent statements are evaluated at the same time; thus, order of these statements doesn’t matter.

Data Flow is most useful style when series of Boolean equations can represent a logic.

XOR3 Example(Cont.)

Structural architecture ARCHITECTURE XOR3_STRUCTURAL OF XOR3 IS SIGNAL U1_OUT : STD_LOGIC;

COMPONENT XOR2 IS PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT; BEGIN U1: XOR2 PORT MAP (I1 => A, I2 => B, Y => U1_OUT);

U2: XOR2 PORT MAP (I1 => U1_OUT, I2 => C, Y => RESULT); END XOR3_STRUCTURAL;

Component and instantiation

Named association connectivity (recommended)

COMPONENT XOR2 IS PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT; U1: XOR2 PORT MAP (I1 => A, I2 => B, Y => U1_OUT);

COMPONENT XOR2 IS PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT;

U1: XOR2 PORT MAP (A, B, U1_OUT);

Component and instantiation (Cont.)

Positional association connectivity

(Not recommended)

Structural description

Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions.

Components are interconnected in a hierarchical manner.

Structural descriptions may connect simple gates or complex, abstract components.

Structural style is useful when expressing a design that is naturally composed of sub-blocks.

XOR3 Example(Cont.)

Behavioral architecture ARCHITECTURE XOR3_BEHAVIORAL OF XOR3 IS BEGIN XOR3_BEHAVE: PROCESS (A,B,C) BEGIN IF ((A xor B xor C) = '1') THEN RESULT <= '1'; ELSE RESULT <= '0'; END IF; END PROCESS XOR3_BEHAVE; END XOR3_BEHAVIORAL;

Behavioral description

It accurately models what happens on the inputs and outputs of the black box (no matter what is inside and how it works).

This style uses Process statements in VHDL.

Test bench

Test bench applies stimuli (drives the inputs) to the Design Under Test (DUT) and (optionally) verifies expected outputs.

The results can be viewed in a waveform window or written to a file.

Since test bench is written in VHDL, it is not restricted to a single simulation tool (portability).

The same Test bench can be easily adapted to test different implementations (i.e. different architectures) of the same design.

Test bench(Cont.)

Test bench block diagram

Test bench Environment

TB Processes

Generating

Stimuli

Design Under Test (DUT)

Stimuli All DUT Inputs

Rule of Thumb: Usually ports from DUT entities are declared as signals within test bench

Simulated Outputs

Representative

Inputs VHDL Design

Manual Calculations

or

Reference Software

Implementation

(C, Java, Matlab )

expected results

Test bench

actual results

= ?

Test bench(Cont.)

Possible sources of expected results used for comparison

Test bench

Design entity

Architecture 1 Architecture 2 Architecture N . . . .

The same test bench can be used to test multiple implementations of the same circuit (multiple architectures)

Test bench(Cont.)

Test bench(Cont.)

Test bench anatomy Entity TB is

--TB entity has no ports

End TB;

ARCHITECTURE arch_TB OF TB IS

--Local signals and constants

COMPONENT TestComp --All Design Under Test component declarations

PORT ( );

END COMPONENT;

--------------------------------------------------------------------------------

FOR DUT:TestComp USE ENTITY WORK.TestComp(archName)--Specify entity/arch pair

--(OPTIONAL)

BEGIN

testSequence: PROCESS

--Main test process

END PROCESS;

DUT:TestComp PORT MAP( --Port map all the DUTs

);

END arch_TB;

XOR3 Example(Cont.)

Test bench LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY XOR3_TB IS END XOR3_TB; ACHITECTURE XOR3_TB_ARCHITECTURE OF XOR3_TB IS -- Component declaration of the tested unit COMPONENT xor3 PORT( A : IN STD_LOGIC; B : IN STD_LOGIC; C : IN STD_LOGIC; RESULT : OUT STD_LOGIC ); END COMPONENT; -- Stimulus signals SIGNAL TEST_VECTOR:STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL TEST_RESULT :STD_LOGIC;

BEGIN UUT : xor3 PORT MAP ( A => TEST_VECTOR(0), B => TEST_VECTOR(1), C => TEST_VECTOR(2), RESULT => TEST_RESULT); TESTING: PROCESS BEGIN TEST_VECTOR<="000"; WAIT FOR 10 ns; TEST_VECTOR<="001"; WAIT FOR 10 ns; TEST_VECTOR<="010"; WAIT FOR 10 ns; TEST_VECTOR<="011"; WAIT FOR 10 ns; TEST_VECTOR<="100"; WAIT FOR 10 ns; TEST_VECTOR<="101"; WAIT FOR 10 ns; TEST_VECTOR<="110"; WAIT FOR 10 ns; TEST_VECTOR<="111"; WAIT FOR 10 ns; END PROCESS TESTING; END XOR3_TB_ARCHITECTURE;

Execution of statements in a PROCESS

The execution of statements continues sequentially till the last statement in the process.

After execution of the last statement, the control is again passed to the beginning of the process.

Testing: PROCESS

BEGIN

test_vector<=“00”;

WAIT FOR 10 ns;


WAIT FOR 10 ns;


WAIT FOR 10 ns;


WAIT FOR 10 ns;

END PROCESS;

O

rder

of

exec

uti

on

Program control is passed to the first statement after BEGIN

PROCESS with a WAIT Statement

The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns.

This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed.

This form of WAIT can be used in a process included in a test bench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated.

Testing: PROCESS

BEGIN


WAIT FOR 10 ns;


WAIT FOR 10 ns;


WAIT FOR 10 ns;


WAIT;

END PROCESS;

Program execution stops here

Ord

er o

f ex

ecu

tio

n

WAIT FOR vs. WAIT

WAIT FOR: waveform will keep repeating itself forever

WAIT : waveform will keep its state after the last wait instruction.

0 1 2 3

…

0 1 2 3 …

Test bench signals generation Generating selected values of one

input SIGNAL test_vector : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN .......

testing: PROCESS BEGIN test_vector <= "000"; WAIT FOR 10 ns; test_vector <= "001"; WAIT FOR 10 ns; test_vector <= "010"; WAIT FOR 10 ns; test_vector <= "011"; WAIT FOR 10 ns; test_vector <= "100"; WAIT FOR 10 ns; END PROCESS testing;

........ END behavioral;

Test bench signals generation(Cont.)

Generating all values of one input

SIGNAL test_vector : STD_LOGIC_VECTOR (3 DOWNTO 0):="0000"; BEGIN ....... testing: PROCESS BEGIN WAIT FOR 10 ns; test_vector <= test_vector + 1; END PROCESS testing; ........ END behavioral;

SIGNAL test_ab : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL test_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); BEGIN .......

double_loo: PPROCESS BEGIN test_ab <="00"; test_sel <="00"; FOR I IN 0 TO 3 LOOP FOR J IN 0 TO 3 LOOP WAIT FOR 10 ns; test_ab <= test_ab + 1; END LOOPl; test_sel <= test_sel + 1; END LOOP; END PROCESS double_loo;

........ END behavioral;


Generating all possible values of two inputs


Generating periodical signals

CONSTANT clk1_period : TIME := 20 ns; CONSTANT clk2_period : TIME := 200 ns; SIGNAL clk1 : STD_LOGIC; SIGNAL clk2 : STD_LOGIC := ‘0’;

BEGIN ....... clk1_generator: PROCESS clk1 <= ‘0’; WAIT FOR clk1_period/2; clk1 <= ‘1’; WAIT FOR clk1_period/2; END PROCESS; clk2 <= not clk2 AFTER clk2_period/2; ....... END behavioral;


Generating one-time signals

CONSTANT reset1_width : TIME := 100 ns; CONSTANT reset2_width : TIME := 150 ns; SIGNAL reset1 : STD_LOGIC; SIGNAL reset2 : STD_LOGIC := ‘1’;

BEGIN ....... reset1_generator: PROCESS reset1 <= ‘1’; WAIT FOR reset_width; reset1 <= ‘0’; WAIT; END PROCESS reset1_generator; reset2_generator: PROCESS WAIT FOR reset_width; reset2 <= ‘0’; WAIT; END PROCESS; ....... END behavioral;

ASSERTs and REPORTs ASSERT

ASSERT is a non-synthesizable statement whose purpose is to write out messages on the screen when problems are found during simulation.

Depending on the SEVERITY of the problem, The simulator is instructed to continue simulation or halt.

ASSERTs and REPORTs(Cont.)

ASSERT syntax

The message is written when the condition is FALSE.

Severity_level can be: NOTE, WARNING, ERROR (default), or FAILURE.

ASSERT condition

[REPORT "message“]

[SEVERITY severity_level ];


Examples for ASSERT ASSERT initial_value <= max_value

REPORT "initial value too large"

SEVERITY ERROR;

-----------------------------------------------------------

ASSERT packet_length /= 0

REPORT "empty network packet received"

SEVERITY WARNING;

-----------------------------------------------------------

ASSERT false

REPORT "Initialization complete"

SEVERITY NOTE;


REPORT syntax

The message is always written.

Severity_level can be: NOTE (default), WARNING, ERROR, or FAILURE.

REPORT "message"

[SEVERITY severity_level ];

Asserts and reports(Cont.)

Examples for REPORT

REPORT "Initialization complete"; ------------------------------------------------------------- REPORT "Current time = " & time'image(now); ------------------------------------------------------------- REPORT "Incorrect branch" SEVERITY ERROR;

Dataflow design style


Structural

VHDL Design Styles

Dataflow


Behavioral

Registers State machines Test benches


Dataflow design style(Cont.)

Dataflow VHDL

Design Style

VHDL code synthesizable

VHDL code synthesizable

Dataflow VHDL Design Style

Concurrent signal assignment ()

Conditional concurrent signal assignment

(WHEN-ELSE)

Selected concurrent signal assignment

(WITH-SELECT-WHEN)

Generate scheme for equations

(FOR-GENERATE)



Full adder example LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT ( x : IN STD_LOGIC ; y : IN STD_LOGIC ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ; END fulladd ; ARCHITECTURE fulladd_dataflow OF fulladd IS BEGIN s <= x XOR y XOR cin ; cout <= (x AND y) OR (cin AND x) OR (cin AND y) ; END fulladd_dataflow ;

Logic operators

Logic operators

Logic operators precedence

and or nand nor xor not xnor

not

and or nand nor xor xnor

Highest

Lowest

only in VHDL-93

Wanted: y = ab + cd Incorrect y <= a and b or c and d ; equivalent to y <= ((a and b) or c) and d ; equivalent to y = (ab + c)d Correct y <= (a and b) or (c and d) ;

Logic operators(Cont.)

No Implied Precedence

Arithmetic operators To use basic arithmetic operations involving std logic vectors you need to

include the following library packages: LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

or

USE ieee.std_logic_signed.all;

You can use standard +, -, * operators to perform addition, subtraction, and multiplication:

SIGNAL a : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL b : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL c : STD_LOGIC_VECTOR (3 DOWNTO 0);

C <= A + B;

Dataflow design style(Cont.) 16-bit Unsigned adder example

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR (15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR (16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; END Behavior ;

16 16

X Y

16

Cin Cout

S

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN SIGNED (15 DOWNTO 0) ; S : OUT SIGNED (15 DOWNTO 0) ; Cout, Overflow : OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : SIGNED (16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ; END Behavior ;


16-bit Signed adder example

ENTITY adder16 IS PORT ( X, Y : IN INTEGER RANGE -32768 TO 32767 ; S : OUT INTEGER RANGE -32768 TO 32767 ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y ; END Behavior ;

Dataflow design style(Cont.) 16-bit Signed adder example(Cont.)


WHEN-ELSE target_signal <= value1 WHEN condition1 ELSE

value2 WHEN condition2 ELSE

. . .

valueN-1 WHEN conditionN-1 ELSE

valueN;

Value 1

Condition 1

Value 2

Condition 2

Value N-1

Condition N-1

Value N

Relational operators

Relational operators

Logic and relational operators precedence

= /= < <= > >=

not

= /= < <= > >=

and or nand nor xor xnor

Highest

Lowest

compare a = bc

Incorrect

… WHEN a = b and c ELSE …

equivalent to

… WHEN (a = b) and c ELSE …

Correct

… WHEN a = (b and c) ELSE …

Relational operators(Cont.)

VHDL operators


2-to-1 Multiplexer example

LIBRARY ieee ;


ENTITY mux2to1 IS

PORT ( w0, w1, s : IN STD_LOGIC ;

f : OUT STD_LOGIC

) ;

END mux2to1 ;

ARCHITECTURE Behavior OF mux2to1 IS

BEGIN

f <= w0 WHEN s = '0' ELSE w1 ;

END Behavior ;

w0 w1

f

s


Tri-state buffer example LIBRARY ieee;


ENTITY tri_state IS

PORT (

ena : IN STD_LOGIC;

input : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

);

END tri_state;

ARCHITECTURE tri_state_dataflow OF tri_state IS

BEGIN

output <= input WHEN (ena = ‘1’) ELSE

(OTHERS => ‘Z’);

END tri_state_dataflow;

ena

output input


4-bit Unsigned number comparator example

LIBRARY ieee ;


USE ieee.std_logic_unsigned.all ;

ENTITY compare IS

PORT ( A, B : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ;

AeqB, AgtB, AltB : OUT STD_LOGIC

) ;

END compare ;

ARCHITECTURE Behavior OF compare IS

BEGIN

AeqB <= '1' WHEN A = B ELSE '0' ;

AgtB <= '1' WHEN A > B ELSE '0' ;

AltB <= '1' WHEN A < B ELSE '0' ;

END Behavior ;

4

4

A

B

AeqB

AgtB

AltB

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ;


4-bit Signed number comparator example


Priority encoder example LIBRARY ieee ;


ENTITY priority IS

PORT ( w : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ;

y : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) ;

z : OUT STD_LOGIC ) ;

END priority ;

ARCHITECTURE Behavior OF priority IS

BEGIN

y <= "11" WHEN w(3) = '1' ELSE

"10" WHEN w(2) = '1' ELSE

"01" WHEN w(1) = '1' ELSE

"00" ;

z <= '0' WHEN w = "0000" ELSE '1' ;

END Behavior ;

w 0

w 3

y 0

y 1

z

w 1

w 2


WITH-SELECT-WHEN

WITH choice_expression SELECT

target_signal <= expression1 WHEN choices_1,

expression2 WHEN choices_2,

. . .

expressionN WHEN choices_N;

choices_1

choices_2

choices_N

expression1

target_signal

choice expression

expression2

expressionN

Dataflow design style(Cont.) WITH-SELECT-WHEN(Cont.)

Allowed formats of choices expressions

WHEN value WHEN value_1 to value_2 WHEN value_1 | value_2 | .... | value N

WITH sel SELECT y <= a WHEN "000", b WHEN "011" to "110", c WHEN "001" | "111", d WHEN OTHERS;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR (1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE Behavior OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Behavior ;



LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR (1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR (0 TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR (2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "1000" WHEN "100", "0100" WHEN "101", "0010" WHEN "110", "0001" WHEN "111", "0000" WHEN OTHERS ; END Behavior ;


2-to-4 Decoder example


FOR-GENERATE

label: FOR identifier IN range GENERATE

BEGIN

{Concurrent Statements}

END GENERATE;


8-Bits parity example

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0); parity_out : OUT STD_LOGIC ); END parity;

Dataflow design style(Cont.) 8-Bits parity example(Cont.)

ARCHITECTURE parity_dataflow_1 OF parity IS

SIGNAL xor_out: STD_LOGIC_VECTOR (6 DOWNTO 1); BEGIN xor_out(1) <= parity_in(0) XOR parity_in(1); G2: FOR i IN 1 TO 5 GENERATE xor_out(i+1) <= xor_out(i) XOR parity_in(i+1); END GENERATE G2; parity_out <= xor_out(6) XOR parity_in(7); END parity_dataflow_1;

Dataflow design style(Cont.) 8-Bits parity example(Cont.)

ARCHITECTURE parity_dataflow_2 OF parity IS

SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN xor_out(0) <= parity_in(0); G2: FOR i IN 0 TO 6 GENERATE xor_out(i+1) <= xor_out(i) XOR parity_in(i+1); END GENERATE G2; parity_out <= xor_out(7); END parity_dataflow_2;

Structural design style


Structural

VHDL Design Styles

Dataflow


Behavioral

Registers & counters Finite state machines Test benches


Component instantiation

(PORT MAP)

Generate scheme for component instantiations

(FOR-GENERATE)

Component instantiation with generic

(GENERIC MAP, PORT MAP)

Structural design style(Cont.)


Example

w 0

w 3

y 0

y 1

z

w 1

w 2

w 0

En

y 0

w 1

y 1

y 2

y 3

s(0)

s(1)

r(0)

r(1)

r(2)

r(3)

r(4)

r(5)

p(0)

p(1)

p(2)

p(3)

q(0)

q(1)

ena

z(0)

z(1)

z(2)

z(3)

dec2to4

priority

LIBRARY ieee ;


ENTITY priority_resolver IS

PORT (r : IN STD_LOGIC_VECTOR (5 DOWNTO 0) ;

s : IN STD_LOGIC_VECTOR (1 DOWNTO 0) ;

z : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)

) ;

END priority_resolver;

ARCHITECTURE structural OF priority_resolver IS

SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ;

SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ;

SIGNAL ena : STD_LOGIC ;

Structural design style(Cont.) Example(Cont.)

COMPONENT mux2to1 PORT (w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END COMPONENT ; COMPONENT priority PORT (w : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; y : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) ; z : OUT STD_LOGIC ) ; END COMPONENT ; COMPONENT dec2to4 PORT (w : IN STD_LOGIC_VECTOR (1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR (0 TO 3) ) ; END COMPONENT ;


BEGIN

u1: mux2to1 PORT MAP (w0 => r(0) , w1 => r(1), s => s(0), f => p(0)); p(1) <= r(2); p(1) <= r(3); u2: mux2to1 PORT MAP (w0 => r(4) , w1 => r(5), s => s(1), f => p(3)); u3: priority PORT MAP (w => p, y => q, z => ena); u4: dec2to4 PORT MAP (w => q, En => ena, y => z);

END structural;



Named association connectivity recommended in majority of cases, prevents ommisions and mistakes

Positional association connectivity allowed, especially for the cases of

– Small number of ports

– Multiple instantiations of the same component, in regular structures

CONSTANT name : type := value;

CONSTANTs

CONSTANT init_value : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0100";

CONSTANT ANDA_EXT : STD_LOGIC_VECTOR (7 DOWNTO 0) := X"B4";

CONSTANT counter_width : INTEGER := 16;

CONSTANT buffer_address : INTEGER := 16#FFFE#;

CONSTANT clk_period : TIME := 20 ns;

CONSTANT strobe_period : TIME := 333.333 ms;

CONSTANTs features

CONSTANTs can be declared in a PACKAGE, ENTITY, ARCHITECTURE

When declared in a PACKAGE, CONSTANT is truly global, for the package can be used in several entities.

When declared in an ARCHITECTURE, CONSTANT is local, i.e., it is visible only within this ARCHITECTURE.

When declared in an ENTITY declaration, CONSTANT can be used in all ARCHITECTUREs associated with this ENTITY.

ROM

LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------------------------------------------------------------------------------------ ENTITY rom IS GENERIC (bits : INTEGER:=8; -- # of bits per word words: INTEGER:=8 -- # of words in the memory ); PORT ( addr: IN INTEGER RANGE 0 TO words-1; data: OUT STD_LOGIC_VECTOR (bits – 1 DOWNTO 0) ); END rom;

ROM (Cont.)

ARCHITECTURE behavioral OF rom IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_L OGIC_VECTOR (bits – 1 DOWNTO 0); CONSTANT memory: vector_array := ("0000_0000", "0000_0010", "0000_0100", "0000_1000", "0001_0000", "0010_0000", "0100_0000", "1000_0000"); BEGIN data <= memory(addr); END rom;

Package declaration Example

LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE GatesPkg IS

COMPONENT mux2to1 PORT (w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END COMPONENT ; COMPONENT priority PORT (w : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; y : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) ; z : OUT STD_LOGIC ) ; END COMPONENT ; COMPONENT dec2to4 PORT (w : IN STD_LOGIC_VECTOR (1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR (0 TO 3) ) ; END COMPONENT ;

CONSTANT ADDAB : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";

CONSTANT ADDAM : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001";

CONSTANT SUBAB : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0010";

CONSTANT SUBAM : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0011";

CONSTANT NOTA : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0100";

CONSTANT NOTB : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0101";

CONSTANT NOTM : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0110";

CONSTANT ANDAB : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0111";

END GatesPkg;

Package declaration(Cont.) Example(Cont.)

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

USE work.GatesPkg.all;

ENTITY priority_resolver IS PORT (r : IN STD_LOGIC_VECTOR (5 DOWNTO 0) ; s : IN STD_LOGIC_VECTOR (1 DOWNTO 0) ; z : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) ; END priority_resolver; ARCHITECTURE structural OF priority_resolver IS SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ; SIGNAL ena : STD_LOGIC ;


BEGIN

u1: mux2to1 PORT MAP (w0 => r(0) , w1 => r(1), s => s(0), f => p(0)); p(1) <= r(2); p(1) <= r(3); u2: mux2to1 PORT MAP (w0 => r(4) , w1 => r(5), s => s(1), f => p(3)); u3: priority PORT MAP (w => p, y => q, z => ena); u4: dec2to4 PORT MAP (w => q, En => ena, y => z);

END structural;


Configuration declaration

CONFIGURATION SimpleCfg OF priority_resolver IS FOR structural FOR ALL: mux2to1 USE ENTITY work.mux2to1(dataflow); END FOR; FOR u3: priority USE ENTITY work.priority(dataflow); END FOR; FOR u4: dec2to4 USE ENTITY work.dec2to4(dataflow); END FOR; END FOR; END SimpleCfg;

w 8

w 11

s 1

w 0

s 0

w 3

w 4

w 7

w 12

w 15

s 3

s 2

f



LIBRARY ieee ;


ENTITY Example1 IS

PORT ( w : IN STD_LOGIC_VECTOR (0 TO 15) ;


f : OUT STD_LOGIC

) ;

END Example1 ;

Structural design style(Cont.) 16-to-1 Multiplexer example(Cont.)

Straightforward code

ARCHITECTURE Structure OF Example1 IS

COMPONENT mux4to1 PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR (1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END COMPONENT ;

SIGNAL m : STD_LOGIC_VECTOR (0 TO 3) ;

BEGIN

Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ;




Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;

END Structure ;


Straightforward code(Cont.)

ARCHITECTURE Structure OF Example1 IS

COMPONENT mux4to1

PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;


f : OUT STD_LOGIC ) ;

END COMPONENT ;

SIGNAL m : STD_LOGIC_VECTOR (0 TO 3) ;

BEGIN

G1: FOR i IN 0 TO 3 GENERATE

Muxes: mux4to1 PORT MAP (

w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ;

END GENERATE ;

Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;

END Structure ;


Modified code


Variable 16-bit rotator example LIBRARY ieee ;


ENTITY variable_rotator_16 is

PORT(

A : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

B : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0);

C : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

);

END variable_rotator_16;

16

16

4

A

B

C

A <<< B

Structural design style(Cont.) Variable 16-bit rotator example(Cont.)

LIBRARY ieee ;


ARCHITECTURE structural OF variable_rotator_16 IS

COMPONENT mux2to1_16

PORT ( w0 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

w1 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

s : IN STD_LOGIC ;

f : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)

) ;

END COMPONENT ;

COMPONENT fixed_rotator_left_16

GENERIC ( L : INTEGER := 1);

PORT ( a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

y : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

) ;

END COMPONENT ;


Variable 16-bit rotator example(Cont.)

TYPE array1 IS ARRAY (0 TO 4) OF STD_LOGIC_VECTOR (15 DOWNTO 0);

TYPE array2 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR (15 DOWNTO 0);

SIGNAL Al : array1;

SIGNAL Ar : array2;

BEGIN

Al(0) <= A;

G: FOR i IN 0 TO 3 GENERATE

ROT_I: fixed_rotator_left_16

GENERIC MAP (L => 2** i)

PORT MAP ( a => Al(i) ,

y => Ar(i));

MUX_I: mux2to1_16 PORT MAP (w0 => Al(i),

w1 => Ar(i),

s => B(i),

f => Al(i+1));

END GENERATE;

C <= Al(4);

END variable_rotator_16;

Behavioral design style


Structural

VHDL Design Styles

Dataflow


Behavioral

Registers & counters Finite state machines Test bench


Behavioral design style(Cont.)

PROCESSes PROCESSes describe sequential behavior

PROCESSes in VHDL are very powerful statements

– Allow to define an arbitrary behavior that may be difficult to represent by a real circuit

– Not every process can be synthesized

Use PROCESSes with caution in the code to be synthesized

Use PROCESSes freely in test benches

A process can be given a unique name using an optional LABEL

This is followed by the keyword PROCESS

The keyword BEGIN is used to indicate the start of the process

All statements within the process are executed SEQUENTIALLY. Hence, the order of statements is important

A process must end with the keywords END PROCESS

testing: PROCESS BEGIN test_vector<=“00”; WAIT FOR 10 ns; test_vector<=“01”; WAIT FOR 10 ns; test_vector<=“10”; WAIT FOR 10 ns; test_vector<=“11”; WAIT FOR 10 ns; END PROCESS;

A process is a sequence of instructions referred to as sequential statements.


What is a PROCESS?

The keyword PROCESS


Anatomy of a Process

[label:] PROCESS [(sensitivity list)] [declaration part] BEGIN statement part END PROCESS [label];

OPTIONAL


Process with a sensitivity list

List of signals to which the process is sensitive

Whenever there is an event on any of the signals in the sensitivity list, the process fire

Every time the process fires, it will run in its entirety.

WAIT statements are not allowed in a PROCESSes with sensitivity list.

label: PROCESS (sensitivity list)

declaration part

BEGIN

statement part

END PROCESS;


Statement Part

Contains sequential statements to be executed each time the process Is activated

Analogous to conventional programming languages

IF statement

ELSE and ELSIF are optional

IF boolean expression THEN statements ELSIF boolean expression THEN statements ELSE boolean expression THEN statements END IF;

Behavioral design style(Cont.) Statement Part(Cont.)

CASE statement

Choices have to cover all possible values of the condition

– Use OTHERS to specify all remaining cases

CASE condition IS WHEN choice_1 => statements WHEN choice_2 => statements WHEN OTHERS => statements END CASE;


Loop Statement

Repeats a section of VHDL code

FOR i IN range LOOP statements END LOOP;


Component Equivalent of a Process

All signals which appear on the left of signal assignment statement (<=) are outputs e.g. y, z

All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputs e.g. w, a, b, c

All signals which appear in the sensitivity list are inputs e.g. clk

Note that not all inputs need to be included in the sensitivity list

priority: PROCESS (clk)

BEGIN

IF w(3) = '1' THEN

y <= "11" ;

ELSIF w(2) = '1' THEN

y <= "10" ;

ELSIF w(1) = c THEN

y <= a and b;

ELSE

z <= "00" ;

END IF ;

END PROCESS ;

w a

y

z priority

b c

clk

LIBRARY ieee ;


ENTITY latch IS


Q : OUT STD_LOGIC

) ;

END latch ;

ARCHITECTURE Behavior OF latch IS

BEGIN

PROCESS ( D, Clock)

BEGIN

IF Clock = '1' THEN

Q <= D ;

END IF ;

END PROCESS ;

END Behavior;

D Q

Clock


D latch

LIBRARY ieee ;


ENTITY flipflop IS


Q : OUT STD_LOGIC

) ;

END flipflop ;


BEGIN

PROCESS ( Clock )

BEGIN

IF Clock'EVENT AND Clock = '1' THEN

Q <= D ;

END IF ;

END PROCESS ;

END Behavior_1 ;

D Q

Clock


D flip-flop

LIBRARY ieee ;


ENTITY flipflop IS


Q : OUT STD_LOGIC

) ;

END flipflop ;


BEGIN

PROCESS

BEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;

Q <= D ;

END PROCESS ;

END Behavior_2 ; D Q

Clock


Another architecture for D flip-flop

LIBRARY ieee ;


ENTITY flipflop IS

PORT ( D, Resetn, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC

) ;

END flipflop ;

ARCHITECTURE Behavior OF flipflop IS

BEGIN

PROCESS ( Resetn, Clock )

BEGIN

IF Resetn = '0' THEN

Q <= '0' ;

ELSIF Clock'EVENT AND Clock = '1' THEN

Q <= D ;

END IF ;

END PROCESS ;

END Behavior ;

D Q

Clock

Resetn


D flip-flop with asynchronous reset

LIBRARY ieee ;


ENTITY flipflop IS

PORT ( D, Resetn, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC

) ;

END flipflop ;

ARCHITECTURE Behavior OF flipflop IS

BEGIN

PROCESS

BEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;


Q <= '0' ;

ELSE

Q <= D ;

END IF ;

END PROCESS ;

END Behavior ;


D flip-flop with synchronous reset

D Q

Clock

Resetn

LIBRARY ieee ;


ENTITY reg8 IS

PORT ( D : IN STD_LOGIC_VECTOR (7 DOWNTO 0) ;

Resetn, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

) ;

END reg8 ;

ARCHITECTURE Behavior OF reg8 IS

BEGIN


BEGIN


Q <= "00000000" ;


Q <= D ;

END IF ;

END PROCESS ;

END Behavior ;

Resetn

Clock

reg8

8 8

D Q


8-bit Register with asynchronous reset

LIBRARY ieee ;


ENTITY regn IS

GENERIC ( N : INTEGER := 16 ) ;

PORT ( D : IN STD_LOGIC_VECTOR (N-1 DOWNTO 0) ;

Resetn, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC_VECTOR (N-1 DOWNTO 0)

) ;

END regn ;

ARCHITECTURE Behavior OF regn IS

BEGIN


BEGIN


Q <= (OTHERS => '0') ;


Q <= D ;

END IF ;

END PROCESS ;

END Behavior ;

Resetn

Clock

regn

N N

D Q


N-bit Register with asynchronous reset

LIBRARY ieee ;


ENTITY regn IS



Enable, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC_VECTOR (N-1 DOWNTO 0)

) ;

END regn ;

ARCHITECTURE Behavior OF regn IS

BEGIN

PROCESS (Clock)

BEGIN

IF (Clock'EVENT AND Clock = '1' ) THEN

IF Enable = '1' THEN

Q <= D ;

END IF ;

END IF;

END PROCESS ;

END Behavior ;

Q D

Enable

Clock

regn

N N


N-bit Register with enable

LIBRARY ieee ;



ENTITY upcount IS

PORT ( Clear, Clock : IN STD_LOGIC ;

Q : BUFFER STD_LOGIC_VECTOR (1 DOWNTO 0)

) ;

END upcount ;

ARCHITECTURE Behavior OF upcount IS

BEGIN

upcount: PROCESS ( Clock )

BEGIN

IF (Clock'EVENT AND Clock = '1') THEN

IF Clear = '1' THEN

Q <= "00" ;

ELSE

Q <= Q + “01” ;

END IF ;

END IF;

END PROCESS;

END Behavior ;


2-bit Up-counter with synchronous reset

2

upcount

Clock

Clear Q

LIBRARY ieee ;



ENTITY upcount IS

PORT ( Clock, Resetn, Enable : IN STD_LOGIC ;

Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)

) ;

END upcount ;

upcount

4 Enable

Clock

Resetn

Q


4-bit Up-counter with asynchronous reset

ARCHITECTURE Behavior OF upcount IS

SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;

BEGIN

PROCESS ( Clock, Resetn )

BEGIN


Count <= "0000" ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

IF Enable = '1' THEN

Count <= Count + 1 ;

END IF ;

END IF ;

END PROCESS ;

Q <= Count ;

END Behavior ;

Behavioral design style(Cont.) 4-bit Up-counter with asynchronous reset(Cont.)

upcount

4 Enable

Clock

Resetn

Q


4-bit Shift register with parallel load

D(3)

D Q

Clock

Enable

Sin D(2)

D Q

D(1)

D Q

D(0)

D Q

Q(0) Q(1) Q(2) Q(3)

Load

LIBRARY ieee ;


ENTITY shiftn IS



Enable : IN STD_LOGIC ;

Load : IN STD_LOGIC ;

Sin : IN STD_LOGIC ;

Clock : IN STD_LOGIC ;

Q : BUFFER STD_LOGIC_VECTOR (N-1 DOWNTO 0)

) ;

END shiftn ;


N-bit Shift register with parallel load

ARCHITECTURE Behavior OF shiftn IS

BEGIN

PROCESS (Clock)

BEGIN

IF (Clock'EVENT AND Clock = '1' ) THEN

IF Load = '1' THEN

Q <= D ;

ELSIF Enable = ‘1’ THEN

Genbits: FOR i IN 0 TO N-2 LOOP

Q(i) <= Q(i+1) ;

END LOOP ;

Q(N-1) <= Sin ;

END IF;

END IF ;

END PROCESS ;

END Behavior ;

Behavioral design style(Cont.) N-bit Shift register with parallel load(Cont.)

TYPE state IS (S0, S1, S2); SIGNAL Moore_state: state; U_Moore: PROCESS (clock, reset) BEGIN IF(reset = ‘1’) THEN Moore_state <= S0; ELSIF (clock = ‘1’ AND clock’EVENT) THEN CASE Moore_state IS WHEN S0 => IF input = ‘1’ THEN Moore_state <= S1; ELSE Moore_state <= S0; END IF;

WHEN S1 => IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF; WHEN S2 => IF input = ‘0’ THEN Moore_state <= S0; ELSE Moore_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;


Sequence ”10” recognizer

TYPE state IS (S0, S1); SIGNAL Mealy_state: state; U_Mealy: PROCESS(clock, reset) BEGIN IF (reset = ‘1’) THEN Mealy_state <= S0; ELSIF (clock = ‘1’ AND clock’EVENT) THEN CASE Mealy_state IS

WHEN S0 => IF input = ‘1’ THEN Mealy_state <= S1; ELSE Mealy_state <= S0; END IF;

WHEN S1 =>

IF input = ‘0’ THEN

Mealy_state <= S0;

ELSE

Mealy_state <= S1;

END IF;

END CASE;

END IF;

END PROCESS;

Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’)

ELSE ‘0’;

Behavioral design style(Cont.) Sequence ”10” recognizer(Cont.)

USE ieee.std_logic_1164.all ; ENTITY simple IS PORT ( clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END simple ; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN

CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ;

END IF ;

END PROCESS ;

z <= '1' WHEN y = C ELSE '0' ;

END Behavior ;


Sequence ”11” recognizer

ARCHITECTURE Behavior2 OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ;

WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ; PROCESS (clock, resetn) BEGIN IF resetn = '0' THEN y_present <= A ; ELSIF (clock'EVENT AND clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ; END Behavior2 ;


Alternative sequence ”11” recognizer architecture

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Mealy IS PORT ( clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END Mealy ; ARCHITECTURE Behavior OF Mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (clock'EVENT AND clock = '1') THEN

CASE y IS

WHEN A =>

IF w = '0' THEN

y <= A ;

ELSE

y <= B ;

END IF ;

WHEN B =>

IF w = '0' THEN

y <= A ;

ELSE

y <= B ;

END IF ;

END CASE ;

END IF ;

END PROCESS ;

WITH y SELECT z <= w WHEN B,

z <= ‘0’ WHEN others;

END Behavior ;

Behavioral design style(Cont.) Sequence ”11” recognizer(Cont.)


State encoding problem

State encoding can have a big influence on optimality of the FSM implementation

– No methods other than checking all possible encodings are known to produce optimal circuit

– Feasible for small circuits only

Using enumerated types for states in VHDL leaves encoding problem for synthesis tool


Types of state encoding

Binary (Sequential) – states encoded as consecutive binary numbers – Small number of used flip-flops – Potentially complex transition functions leading to

slow implementations

One-Hot – only one bit Is active – Number of used flip-flops as big as number of

states – Simple and fast transition functions – Preferable coding technique in FPGAs

Behavioral design style(Cont.) Types of state encoding(Cont.)

State Binary Code One-Hot Code

S0 000 10000000

S1 001 01000000

S2 010 00100000

S3 011 00010000

S4 100 00001000

S5 101 00000100

S6 110 00000010

S7 111 00000001

--(ENTITY declaration not shown) ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; ATTRIBUTE ENUM_ENCODING : STRING ; ATTRIBUTE ENUM_ENCODING OF State_type : TYPE IS "00 01 11" ; SIGNAL y_present, y_next : State_type ; BEGIN con’t ...


Manual state assignment using attributes

ARCHITECTURE Behavior OF simple IS SUBTYPE ABC_STATE IS STD_LOGIC_VECTOR (1 DOWNTO 0); CONSTANT A : ABC_STATE := "00" ; CONSTANT B : ABC_STATE := "01" ; CONSTANT C : ABC_STATE := "11" ; SIGNAL y_present, y_next : ABC_STATE; ------------------------------------------------------------------------------------------- BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; … con’t


Manual state assignment using constants


Arbiter circuit

Idle

000

1xx

Reset

gnt1 g 1 1 =

x1x

gnt2 g 2 1 =

xx1

gnt3 g 3 1 =

0xx 1xx

01x x0x

001 xx0

Arbiter

reset

r1

r2

r3

g1

g2

g3

clock

ARCHITECTURE ARCHITECTURE_NAME OF ENTITY_NAME IS

– Here you can declare signals, constants, functions, procedures…

– Component declarations

BEGIN

Concurrent statements:

• Concurrent simple signal assignment

• Conditional signal assignment

• Selected signal assignment

• Generate statement

• Component instantiation statement

• Process statement – inside process you can use only sequential statements

END ARCHITECTURE_NAME;

Mixed design style

Concurrent Statements

SIGNALs and concurrent statements

In fact there is no effect even if we put synchronous inputs in the sensitivity list in case of clocked processes with synchronous inputs

Inside PROCESS: If multiple assignments occur to SIGNAL X, the last assignment “X <= ?“ overrides previous ones

Multiple concurrent assignment to one signal is not allowed in tools without resolved logic support

SIGNALs and VARIABLEs

SIGNALs are global(declared outside PROCESSes) VARIABLEs live inside PROCESSes only(declared inside

PROCESSes only). VARIABLEs are sequential, their values change

intermediately. SIGNAL representing an internal wire or an

in/out/buffer signal in port. <= SIGNAL assignment. A1<= B1 or C1; • := VARIABLE assignment. A2 := B2 and C2;

Subprograms

Include

FUNCTIONs and PROCEDUREs

Commonly used pieces of code

Can be placed in a library, and then reused and shared among various projects

Abstract operations that are repeatedly performed

Type conversions

Use only sequential statements, the same as processes

Subprograms(Cont.) Typical locations of subprograms

FUNCTION / PROCEDURE

PACKAGE PACKAGE BODY

LIBRARY

global

ARCHITECTURE Declarative part

local for a given architecture

ENTITY

local for all architectures of a given entity

FUNCTIONs

FUNCTIONs always return a single value as a result FUNCTIONs are called using formal and actual parameters

the same way as components FUNNCTIONs never modify parameters passed to them Parameters can only be constants (including generics) and

signals (including ports); variables are not allowed; the default is a CONSTANT

When passing parameters, no range specification should be included (for example no RANGE for INTEGERS, or TO/DOWNTO for STD_LOGIC_VECTOR)

FUNCTIONs are always used in some expression, and not called on their own

FUNCTIONs(Cont.)

FUNCTION syntax

FUNCTION function_name (<parameter_list>)

RETURN data_type IS

[declarations]

BEGIN

(sequential statements)

END function_name;

FUNCTIONs(Cont.)

FUNCTION parameters Example

FUNCTION f1

(a, b: INTEGER; SIGNAL c: STD_LOGIC_VECTOR)

RETURN BOOLEAN IS

BEGIN

(sequantial statements)

END f1;

FUNCTIONs(Cont.)

FUNCTION calls Examples

x <= conv_integer(a);

IF x > maximum(a, b) THEN ....

WHILE minimum(a, b) LOOP

FUNCTIONs(Cont.)

Example LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

ENTITY powerOfFour IS

PORT(

X : IN INTEGER;

Y : OUT INTEGER

);

END powerOfFour;

ARCHITECTURE behavioral OF powerOfFour IS FUNCTION Pow ( SIGNAL N: INTEGER; Exp : INTEGER)

RETURN INTEGER IS VARIABLE Result : INTEGER := 1; BEGIN FOR i IN 1 TO Exp LOOP Result := Result * N; END LOOP; RETURN( Result ); END Pow; BEGIN Y <= Pow(X, 4); END behavioral;

FUNCTIONs(Cont.)

Example: PACKAGE containing a FUNCTION

LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

PACKAGE specialFunctions IS

FUNCTION Pow( SIGNAL N: INTEGER; Exp : INTEGER) RETURN INTEGER;

END specialFunctions

FUNCTIONs(Cont.) Example: PACKAGE containing a FUNCTION(Cont.)

PACKAGE BODY specialFunctions IS FUNCTION Pow (SIGNAL N: INTEGER; Exp : INTEGER) RETURN INTEGER IS

VARIABLE Result : INTEGER := 1; BEGIN FOR i IN 1 TO Exp LOOP Result := Result * N; END LOOP; RETURN( Result ); END Pow; END specialFunctions

FUNCTIONs(Cont.)

Example: Type conversion FUNCTION

LIBRARY ieee;


--------------------------------------------------------------------------------------

PACKAGE my_package IS

FUNCTION conv_integer ( SIGNAL vector: STD_LOGIC_VECTOR)

RETURN INTEGER;

END my_package;

FUNCTIONs(Cont.) Example: Type conversion FUNCTION(Cont.)

PACKAGE BODY my_package IS

FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR)

RETURN INTEGER;

VARIABLE result: INTEGER RANGE 0 TO 2**vector’LENGTH - 1;

VARIABLE carry: STD_LOGIC;

BEGIN

IF (vector(vector’HIGH)=‘1’ THEN result:=1;

ELSE result := 0;

FOR i IN (vector’HIGH-1) DOWNTO (vector’LOW) LOOP

result := result*2;

IF (vector(i) = ‘1’ THEN result := result+1;

END IF;

RETURN result;

END conv_integer;

END my_package;

FUNCTIONs(Cont.) Example: Type conversion FUNCTION(Cont.)

LIBRARY ieee;


USE work.my_package.all;

----------------------------------------------------------

ENTITY conv_int2 IS

PORT ( a: IN STD_LOGIC_VECTOR (0 TO 3);

y: OUT INTEGER RANGE 0 TO 15);

END conv_int2;

----------------------------------------------------------

ARCHITECTURE my_arch OF conv_int2 IS

BEGIN

y <= conv_integer(a);

END my_arch;

PROCEDUREs

PROCEDUREs do not return a value PROCEDUREs are called using formal and actual parameters

the same way as components PROCEDUREs may modify parameters passed to them Each parameter must have a mode: IN, OUT, INOUT Parameters can be constants (including generics), signals

(including ports), and variables; the default for inputs (mode in) is a constant, the default for outputs (modes out and inout) is a variable

When passing parameters, range specification should be included (for example RANGE for INTEGERS, and TO/DOWNTO for STD_LOGIC_VECTOR)

Procedure calls are statements on their own

PROCEDUREs(Cont.)

PROCEDURE syntax

PROCEDURE procedure_name (<parameter_list>)IS

[declarations]

BEGIN

(sequential statements)

END procedure_name;

PROCEDUREs(Cont.)

Examples: PROCEDURE parameters

PROCEDURE my_procedure

( a : IN BIT;

SIGNAL b, c: IN BIT;

SIGNAL x : OUT BIT_VECTOR(7 DOWNTO 0);

SIGNAL y : INOUT INTEGER RANGE 0 TO 99) IS

BEGIN

(sequantial statements)

END my_procedure;

PROCEDUREs(Cont.)

Examples: PROCEDURE calls

compute_min_max(in1, in2, in3, out1, out2);

divide(dividend, divisor, quotient, remainder);

IF (a > b) THEN

compute_min_max(in1, in2, in3, out1, out2);

.......

PROCEDUREs(Cont.)

Example

LIBRARY ieee;


ENTITY min_max IS

GENERIC (limit: INTEGER := 255);

PORT (

ena : IN BIT;

inp1, inp2 : IN INTEGER RANGE 0 TO limit;

min_out, max_out: OUT INTEGER RANGE 0 TO limit

);

END min_max;

PROCEDUREs(Cont.) Example(Cont.)

ARCHITECTURE my_architecture OF min_max IS PROCEDURE sort (SIGNAL in1, in2: IN INTEGER RANGE 0 TO limit; SIGNAL min, max: OUT INTEGER RANGE 0 TO limit) IS BEGIN IF (in1 > in2) THEN max <= in1; min <= in2; ELSE max <= in2; min <= in1; END IF; END sort; BEGIN PROCESS (ena) BEGIN IF (ena=‘1’) THEN sort (inp1, inp2, min_out, max_out); END IF; END PROCESS; END my_architecture;

Operator as a FUNCTION

LIBRARY ieee;

USE ieee.std_logic_1164.al;

----------------------------------------------------------

PACKAGE my_package IS

FUNCTION "+" (a, b: STD_LOGIC_VECTOR)

RETURN STD_LOGIC_VECTOR;

END my_package;

Operator as a FUNCTION(Cont.)

PACKAGE BODY my_package IS

FUNCTION "+" (a, b: STD_LOGIC_VECTOR)

RETURN STD_LOGIC_VECTOR;

VARIABLE result: STD_LOGIC_VECTOR;

VARIABLE carry: STD_LOGIC;

BEGIN

carry := ‘0’;

FOR i IN a’REVERSE_RANGE LOOP

result(i) := a(i) XOR b(i) XOR carry;

carry := (a(i) AND b(i)) OR (a(i) AND carry) OR (b(i) AND carry));

END LOOP;

RETURN result;

END "+" ;

END my_package;

Operator overloading

Operator overloading allows different argument types for a given operation (function)

The VHDL tools resolve which of these functions to select based on the types of the inputs

This selection is transparent to the user as long as the function has been defined for the given argument types.

Operator overloading(Cont.) Example

FUNCTION “+” ( L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;

FUNCTION “+” ( L: STD_LOGIC_VECTOR; R: integer) RETURN STD_LOGIC_VECTOR;

FUNCTION “+” ( L: STD_LOGIC_VECTOR; R: STD_LOGIC) RETURN STD_LOGIC_VECTOR;

Operator overloading(Cont.)

Examples

SIGNAL count: STD_LOGIC_VECTOR (7 DOWNTO 0);

You can use

count <= count + “0000_0001”;

or

count <= count + 1;

or

count <= count + ‘1’;

Read about

Array attributes

Records

Physical data types

Recommended rules for Synthesis

When implementing combinational paths do not have hierarchy

Register all outputs

Do not implement glue logic between blocks, partition them well

Separate designs on functional boundary

Keep block sizes to a reasonable size

Recommended rules for Synthesis(Cont.)

Avoid hierarchical combinational blocks

The path between reg1 and reg2 is divided between three different block

Due to hierarchical boundaries, optimization of the combinational logic cannot be achieved

Not recommended Design Practice

Combinatorial

Logic1Combinatorial

Logic2

Combinatorial

Logic3

Block A Block B Block C

reg1 reg2


Recommend way to handle Combinational Paths

All the combinational circuitry is grouped in the same block that has its output connected the destination flip flop

It allows the optimal minimization of the combinational logic during synthesis

Allows simplified description of the timing interface

Recommended practice

Combinatorial

Logic1 &

Logic2& Logic3

Block A Block C

reg1reg2



Simplifies the synthesis design environment: Inputs to the individual block arrive within the same relative delay (caused by wire delays)

Don’t really need to specify output requirements since paths starts at flip flop outputs.


Block X Block Y

reg1reg2

Block Y

reg3


NO glue logic between blocks

No Glue Logic between Blocks, no

matter what the temptation

Block X

reg1

Block Y

reg3

Top

Due to time pressures, and a bug found that can be simply be fixed by adding some simple glue logic. RESIST THE TEMPTATION!!!

At this level in the hierarchy, this implementation will not allow the glue logic to be absorbed within any lower level block.


Separate design with different goals

reg1

Slow Logic

Top

Time

critical path

reg3

reg1 may be driven by time critical function, hence will have different optimization constraints

reg3 may be driven by slow logic, hence no need to constrain it for speed


Optimization based on design requirements

reg1

Slow Logic

Top

Time

critical path

reg3

Area optimized block

Speed optimized block

Use different entities to partition design blocks

Allows different constraints during synthesis to optimize for area or speed or both.


Separate FSM with random logic

Separation of the FSM and the random logic allows you to use FSM optimized synthesis

reg1

Random

Logic

Top

FSM

reg3

Standard optimization

techniques used

Use FSM optimization tool


Maintain a reasonable block size

Larger the blocks, longer the run time -> quick iterations cannot be done.

thanks

digital design

Documents

VHDL Material by Mohamed Adly