EXPERIMENT NO. – 5

Aim:-To Design octal – to – binary encoder using VHDL.

Tool used:- Xilinx -10.2 ISE stimulator- CAD(Computer Aided Design) tool

Theory used:- Encoder is a combinational circuit which is designed to perform the inverse operation of the decoder. An encoder has n number of input lines and m number of output lines. An encoder produces an m bit binary code corresponding to the digital input number. The encoder accepts an n input digital word and converts it into an m bit another digital word.

Block diagram:

octal – to – binary encoder has eight inputs, one for each of the octal digits, and three outputs that

generate the corresponding binary number. A0 = D1+D3+D5+D7A1 = D2+D3+D6+D7A2 = D4+D5+D6+D7

VHDL Code (encoder 3 to 8)

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity encoder_8to3 isport(i:in std_logic_vector(7 downto 0); a,b,c:out std_logic);

end encoder_8to3;

architecture Behavioral of encoder_8to3 is

begina<=i(4) or i(5) or i(6) or i(7);b<=i(2) or i(3) or i(6) or i(7);c<=i(1) or i(3) or i(5) or i(7);

end Behavioral;

Fig.:-1 RTL View of 3 to 8 encoder

Fig.:-2 Block Diagram of 8 to 3 encoder

Fig.:-3 Output of 3 to 8 line encoder

Result:-

Output waveform is verified as per required design