Tutorial Disclaimer This tutorial includes one way of simulating
in Verilog XL. This is not necessarily the best way of simulating,
depending on your requirements. This tutorial is a simple
step-through designed to familiarize the user with Verilog XL, and
thus is basic in nature. More advance simulations are not found in
this tutorial.
Create Verilog FileCreate a text file with the text shown
hereThis code represents a basic circuit with delay and test
stimulusSave as example.vVerilog code files often have a .v file
extension
Enter ICFBType who am iGives xhost addresssetenv DISPLAY
{xhost}Type icfb & to start Cadence
Import Verilog File in ICFBImport the example.v Verilog file by
choosing File >> Import >> Verilog in ICFB CIW
Importing Verilog FileVerilog In window pops upSet Target
Library Name to newHighlight example.v in file selection box at the
top of the windowPress the Add button on the Verilog Files to
Import lineClick OK at the top of the Verilog In window
Verify File ImportOpen up the Library Manger from the CIW and
inspect to ensure the new library includes a cell named
circuit_with_delay
Verify File ImportOpen the Schematic view of the
circuit_with_delay from the Library Manager and verify that it
resembles the screenshot to the left
Running Verilog XLClose all windows except a terminalFrom your
home directory typeverilog +gui example.vVerilog should open with
your example loadedNote: example.v has to be saved in your home
directory for this command to function
Simulating with Verilog XLVerilog should open the SimVision
Design Browser and ConsoleThe stimcrct module should be displayed
under the simulator icon
Simulating with Verilog XLClick on the stimcrct iconThe circuit
inputs and outputs should now be visible under Signal/Variable
Simulating with VerilogWith the stimcrct highlighted choose
Select>>Signals
Simulating with Verilog XLNow that the signals are highlighted,
send them to the logic display by clicking on the indicated button
Click Here
Simulating with Verilog XLClick the Play button to run the
simulationRun Button
Simulating with Verilog XLSince the simulation has no initial
stop point the output will appear similar to the window to the
left
Simulating with Verilog XLTo rerun the simulation it must first
be resetReset the simulation by choosing Reinvoke Simulator from
the simulation menu
Simulation with Verilog XLRun the simulation by pressing the Run
buttonRun Button
Simulation with Verilog XLSimulation output should look like
this
ConclusionThis concludes the Verilog XL TutorialThis tutorial
was derived from the SMU Cadence Verilog XL
Tutorialhttp://engr.smu.edu/~mitch/class/3381/verilog_intro.pdf
