Verilog Updated Programs

8/18/2019 Verilog Updated Programs

http://slidepdf.com/reader/full/verilog-updated-programs 1/47

4 - bit adders

4 Bit Ripple Carry Adder in Verilog

Structural Model : Half Adder

module half_adder(

output S,C,

input A,B

);

xor(S,A,B);

and(C,A,B);

endmodule

Structural Model : Full Adder

module full_adder(

output S,Cout,

input A,B,Cin

);

wire s1,c1,c2;

half_adder HA1(s1,c1,A,B);

half_adder HA2(S,c2,s1,Cin);

or !1(Cout,c1,c2);

endmodule

Structural Model : 4 Bit Ripple Carry Adder

module ripple_adder_"#it(

output $%&' Sum, output Cout,

input $%&' A,B,

input Cin

);

wire c1,c2,c%;

full_adder A1(Sum$',c1,A$',B$',Cin),

A2(Sum$1,c2,A$1,B$1,c1),

http://tjeyamy.blogspot.in/2012/02/4-bit-ripple-carry-adder-in-verilog.html

http://tjeyamy.blogspot.in/2012/02/4-bit-ripple-carry-adder-in-verilog.html



A%(Sum$2,c%,A$2,B$2,c2),

A"(Sum$%,Cout,A$%,B$%,c%);

endmodule

Test Bench : 4 Bit Ripple Carry Adder

module test_ripple_adder_"#it;

** +nputs

re $%&' A;

re $%&' B;

re Cin;

** utputs wire $%&' Sum;

wire Cout;

** +nstantiate the -nit -nder .est (--.)

ripple_adder_"#it uut (

/Sum(Sum),

/Cout(Cout),

/A(A),

/B(B),

/Cin(Cin)

); initial #ein

** +nitiali0e +nputs

A ';

B ';

Cin ';

** ait 1'' ns for lo#al reset to finish

31'';

** Add stimulus here

A"4#'''1;B"4#'''';Cin14#';

31' A"4#1'1';B"4#''11;Cin14#'; 31' A"4#11'1;B"4#1'1';Cin14#1;

end

initial #ein

5monitor(6time6,5time,, 6A7# B7# Cin7# & Sum7# Cout

7#6,A,B,Cin,Sum,Cout);

end



8ndmodule

4 Bit Carry Look Ahead Adder in Verilog

DataFlow Model : 4 Bit CLA

module C9A_"#it(

output $%&' S,

output Cout,:!,!!, input $%&' A,B,

input Cin

);

wire $%&' !,:,C;

assin ! A B; **!enerate

assin : A < B; **:ropaate

assin C$' Cin;

assin C$1 !$' = (:$' C$');

assin C$2 !$1 = (:$1 !$') = (:$1 :$' C$');

assin C$% !$2 = (:$2 !$1) = (:$2 :$1 !$') =

(:$2 :$1 :$' C$');

assin Cout !$% = (:$% !$2) = (:$% :$2 !$1) =

(:$% :$2 :$1 !$') =(:$% :$2 :$1 :$' C$');

assin S : < C;

assin :! :$% :$2 :$1 :$';

assin !! !$% = (:$% !$2) = (:$% :$2 !$1) = (:$%

:$2 :$1 !$');

endmodule

Test Bench : 4 Bit CLA

module .est_C9A_"#it;

** +nputs

re $%&' A;



re $%&' B;

re Cin;

** utputs

wire $%&' S;

wire Cout;

wire :!;

wire !!;


C9A_"#it uut (

/S(S),

/Cout(Cout),

/:!(:!),

/!!(!!),/A(A),

/B(B),

/Cin(Cin)

);

initial #ein


A '; B '; Cin ';

** ait 1'' ns for lo#al reset to finish 31'';


A"4#'''1;B"4#'''';Cin14#';

31' A"4#1'';B"4#''11;Cin14#';

31' A"4#11'1;B"4#1'1';Cin14#1;

31' A"4#111';B"4#1''1;Cin14#';

31' A"4#1111;B"4#1'1';Cin14#';

end

initial #ein

5monitor(6time6,5time,, 6A7# B7# Cin7# & Sum7# Cout7# :!7#

!!7#6,A,B,Cin,S,Cout,:!,!!);

end

endmodule



Simulation Results

time ' A'''' B'''' Cin' & Sum'''' Cout' :!' !!'

time 1'' A'''1 B'''' Cin' & Sum'''1 Cout' :!' !!'

time 11' A'1'' B''11 Cin' & Sum'111 Cout' :!' !!'time 12' A11'1 B1'1' Cin1 & Sum1''' Cout1 :!' !!1

time 1%' A111' B1''1 Cin' & Sum'111 Cout1 :!' !!1

time 1"' A1111 B1'1' Cin' & Sum1''1 Cout1 :!' !!1

Verilog code for Carry Save Adder:

module carrysave(p0,p1,p2,p3,p4,p5,s,c,a,b);output [5:0]p0,p1,p2,p3,p4,p5;

output [10:0]s;

output [7:0]c;

iput [5:0]a,b;

!ire

d,d1,d2,d3,d4,d5,d",d7,d#,d$,d10,d11,d12,d13,d14,d15,d1",d17,e1,e2,e3,e4,e5,e",e7,e#,e$,e10,e11,e13,e14,e15,e1",e17;

assi% p0&b[0]'a:0;assi% p1&b[1]'a:0;

assi% p2&b[2]'a:0;

assi% p3&b[3]'a:0;

assi% p4&b[4]'a:0;

assi% p5&b[5]'a:0;

assi% s[0]&p0[0];

*1(s[1],d,p0[1],p1[0]);

*2(e5,d5,p1[5],p2[4]);

+ m1(e1,d1,p0[2],p1[1],p2[0]);

+ m2(e2,d2,p0[3],p1[2],p2[1]);

+ m3(e3,d3,p0[4],p1[3],p2[2]);

+ m4(e4,d4,p0[5],p1[4],p2[3]);

*3(e",d",p3[1],p4[0]);

*4(e11,d11,p4[5],p5[4]);



+ m5(e7,d7,p3[2],p4[1],p5[0]);

+ m"(e#,d#,p3[3],p4[2],p5[1]);

+ m7(e$,d$,p3[4],p4[3],p5[2]);

+ m#(e10,d10,p3[5],p4[4],p5[3]);

*5(s[2],d12,d,e1);

+ m$(e13,d13,d1,e2,p3[0]);

+ m10(e14,d14,d2,e3,e");+ m11(e15,d15,d3,e4,e7);

+ m12(e1",d1",d4,e5,e#);

+ m13(e17,d17,d5,e",p2[5]);

*"(s[3],c[0],d12,e13);

*7(s[4],c[1],d13,e14); *#(s[$],c["],d10,e11);

*$(s[10],c[7],d11,p5[5]);

+ m14(s[5],c[2],d",d14,e15);

+ m15(s["],c[3],d7,d15,e1");

+ m1"(s[7],c[4],d#,d1",e17);

+ m17(s[#],c[5],d$,d17,e10);

edmodule

Address Decoders a) 2 to 4 decoder

b) 3 to # decoder

c) priority ecoder

2 : 4 DECODER

VERILOG CODE:

module >ecoder(A, B, >);

input A, B; output $%&' >; re $%&' >;

alwa?s @ (A or B) #ein



if( A ' B ' ) > "4#'''1;

else if ( A ' B 1 ) > "4#''1';

else if ( A 1 B ' ) > "4#'1'';

else > "4#1'''; end

endmodule

.8S. B8CH&

module .est#ench;

re A_t, B_t; wire $%&' >_t;

>ecoder >ecoder_1(A_t, B_t, >_t);

initial #ein

**case ' A_t '; B_t '; 31 5displa?(6>_t 7#6, >_t);

**case 1

A_t '; B_t 1; 31 5displa?(6>_t 7#6, >_t);

**case 2

A_t 1; B_t '; 31 5displa?(6>_t 7#6, >_t);

**case %

A_t 1; B_t 1; 31 5displa?(6>_t 7#6, >_t);

end

endmodule



3 : 8 DECODER

Function Table

Input Output

enable A1 A1 A0 Z7 Z Z! Z" Z# Z$ Z1 Z0

0 % & % 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 1

1 0 0 1 0 0 0 0 0 0 1 0

1 0 1 0 0 0 0 0 0 1 0 0

1 0 1 1 0 0 0 0 1 0 0 0

1 1 0 0 0 0 0 1 0 0 0 0

1 1 0 1 0 0 1 0 0 0 0 0

1 1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0

Block Diagram 3-8 line Decoder

Z7

Enable

3 to 8 line

decoder

Z6

Z5

Z4

Z3

Z2

Z1Z0

A0

A1A2



Circuit Diagram 3-8 line Decoder

Verilog Code for # to ' line decoder

(odule dec)bin*decout*en+,

input -0:$. bin,

input en,

output -7:0. decout,

reg decout,

al/ay )en or bin+

begin

decout20,

if)en+



begin

cae)bin+

#3b000:decout2'3o001,

#3b001:decout2'3o00$,

#3b010:decout2'3o00",

#3b011:decout2'3o010,

#3b100:decout2'3o0$0,

#3b101:decout2'3o0"0,

#3b110:decout2'3o100,

#3b111:decout2'3o$00,

endcae

end

end

end4odule

(OR)

VERILOG CODE

module decodermod(e, a, b, d);

input e;

input a;

input b;

output [7:! d;



a""i#n d[!$(%e)&(%a)&(%b);

a""i#n d['!$(%e)&(%a)&(b);

a""i#n d[!$(%e)&(a)&(%b);

a""i#n d[!$(%e)&(a)&(b);

a""i#n d[*!$(e)&(%a)&(%b);

a""i#n d[+!$(e)&(%a)&(b);

a""i#n d[!$(e)&(a)&(%b);

a""i#n d[7!$(e)&(a)&(b);

endmodule

TEST BENCH

module decodert-b;

re# e;

re# a;

re# b;

.ire [7:! d;

decodermod uut ( /e(e),/a(a),/b(b),/d(d) );

initial be#in

0' e$'1b;a$'1b;b$'1b;



0' e$'1b;a$'1b;b$'1b';

0' e$'1b;a$'1b';b$'1b;

0' e$'1b;a$'1b';b$'1b';

0' e$'1b';a$'1b;b$'1b;

0' e$'1b';a$'1b;b$'1b';

0' e$'1b';a$'1b';b$'1b;

0' e$'1b';a$'1b';b$'1b';

0'2"top;

end

endmodule

4 Bit Priority Encoder in Verilog

3riorit4 Encoder i" an encoder circuit t5at include" a priorit4 6unction/ 5e operation i""uc5 t5at i6 t.o or more input" are e8ual to ' at t5e "ame time, t5e input 5a9in# t5e5i#5e"t priorit4 .ill tae precedence/ere, t5e priorit4 decrea"e" 6rom ri#5t to le6t in t5e input/ D[! 5a" t5e 5i#5e"t priorit4/ Vindicate t5e 9alidit4 o6 t5e input (atlea"t one input "5ould be ') and t5e < #i9e" t5eoutput/(' mean" ', ' mean" lie t5at///)

http://tjeyamy.blogspot.in/2012/05/4-bit-priority-encoder-in-verilog.html

http://tjeyamy.blogspot.in/2012/05/4-bit-priority-encoder-in-verilog.html



Behaioural Model : 4 Bit !riority "ncoder

module :riorit?8ncoder_"Bit(

input $'&% >,

output $1&' ,

output D

);

re $1&' ;

re D;

alwa?s @(>)

#ein

$1 >$2 = >$%;

$' >$% = >$1 E>$2;

D >$' = >$1 = >$2 = >$%;

end

endmodule

Test Bench : 4 Bit !riority "ncoder

module :riorit?8ncoder_"Bit_.est;

** +nputs

re $%&' >;

** utputs



wire $1&' ;

wire D;


:riorit?8ncoder_"Bit uut (

/>(>),

/(),

/D(D)

);

initial #ein


> ';

** ait 1'' ns for lo#al reset to finish

31'';


31' > "4#''''; 31' > "4#1''';

31' > "4#'1'';

31' > "4#''1';

31' > "4#'''1;

31' > "4#1'1';

31' > "4#1111;

end

initial #ein

5monitor(6time6,5time,, 6>7# & 7# D7#6,>,,D);

endendmodule

Si#ulation Results

time ''', >'''' & '' D'

time 12', >1''' & '' D1

time 1%', >'1'' & '1 D1

time 1"', >''1' & 1' D1

time 1F', >'''1 & 11 D1time 1G', >1'1' & 1' D1

time 1', >1111 & 11 D1



I-9.+:98J8KS

4 : 1 MULTIPLEXER

Function Table

Selection

Inputs

Output

S1 S0

0 0 D0

0 1 D1

1 0 D2

1 1 D3

Block Diagram 4:1 Multiplexer

Circuit Diagram 4:1 Multiplexer



Verilog code " to 1 for 4ultiple%er

module mu4to1(-, .0,.1,.2,.3, sel);

output -;

iput .0,.1,.2,.3;

iput [1:0] sel;

re% -;

al!ays / (sel or .0 or .1 or .2 or .3)

case (sel)

2b00:-&.0;

2b01:-&.1;

2b10: -&.2;

2b11: -&.3;



deault: -&2b00;

edcase

edmodule

(OR)

$"R%&O' CO":

module mu=*bit(a, ", o);

input [:! a;

input [':! ";

output o;

re# o;

al.a4" >(a or ")

be#in

ca"e (")

1b:o$a[!;

1b':o$a['!;

1b':o$a[!;

1b'':o$a[!;

de6ault:o$;

endca"e



end

endmodule

TEST BENCH:

module mu=t-b;

re# [:! a;

re# [':! ";

.ire o;

mu=*bit uut (/a(a), /"("),/o(o));

initial be#in

0' a$*1b'';

0' "$1b;

0' "$1b';

0' "$1b';

0' "$1b'';

0' 2"top;

end

endmodule



1:4 Demultiplexer

Function table

5ata

Input

Selection

Input

Output

5 S1 S0 6# 6$ 61 60

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

Function Table

Input Output

S1 S0

0 0 6025

0 1 6125

1 0 6$25

1 1 6#25

Block Diagram 1:4 Demultiplexer



Circuit Diagram 1:4 Demultiplexer

Verilog code for 1 to " de4ultiple%er

4odule de4u%)S*5*6+,

Input -1:0. S,

Input 5,

Output -#:0. 6,

reg 6,

al/ay )S O 5+

cae)85*S9+

#3b100:62"3b0001,

#3b101:62"3b0010,



#3b110:62"3b0100,

#3b111:62"3b1000,

default:62"3b0000,

endcae

end4odule

E? @EAC:

0' "$1b;

0' "$1b';

0' "$1b';

0' "$1b'';

0' 2"top;

end

endmodule

C-.8KS

";it ;inary ipple Counter

Function Table

Output(count 0-15)



A B C D

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit 5iagra4

Verilog Code for ipple Counter

4odule ripple)cl<r*t**t*A*;*C*5+,

input cl<*rt*t,

output A*;*C*5,



Tff T0)5*cl<*rt*t+,

Tff T1)C*cl<*rt*t+,

Tff T$);*cl<*rt*t+,

Tff T#)A*cl<*rt*t+,

end4odule

4odule Tff)=*cl<*rt*t+,

input cl<*rt*t,

output =,

reg =,

al/ay )poedge cl<+

begin

if)rt+

=>213b0,

ele

if)t+

=>2?=,

end

end4odule

"bit @p5o/n Counter

Count Table

Output)count Output )count up+



do/n+

0 1 $ #

0

1 $ #

1 1 1 1 0 0 0 0

1 1 1 0 0 0 0 1

1 1 0 1 0 0 1 0

1 1 0 0 0 0 1 1

1 0 1 1 0 1 0 0

1 0 1 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 0 0 0 1 1 1

0 1 1 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 0 1 1 0 1 0

0 1 0 0 1 0 1 1

0 0 1 1 1 1 0 0

0 0 1 0 1 1 0 1

0 0 0 1 1 1 1 0

0 0 0 0 1 1 1 1



Circuit diagra4

Verilog code for updo/n counter

module updowncount (R, Cloc, cl!, ", up#down, $)%

p&!&mete! n ' %

input n-1*0+ R%

input Cloc, cl!, ", up#down%

output n-1*0+ $%

!e n-1*0+ $%

intee! di!ection%

&lw&s .(posede Cloc)

/ein

i (up#down) di!ection ' 1%

else di!ection ' -1%

i (cl!) $ ' R%

else i (") $ ' $ di!ection%



end

endmodule

)O+

UP-DOWNCOUNTER VERIOLG CODE

module updo.ncountermod(cl, clear, updo.n, 8);

input cl;

input clear;

input updo.n;

output [:! 8;

re# [:! 8;

al.a4">(po"ed#e clear or po"ed#e cl)

be#in

i6(clear)

8 B$*1b;

el"e i6(updo.n)

8 B$ 8'1b';

el"e

8 B$ 8'1b';



end

endmodule

TEST BENCH

module updo.ncountert-b;

re# cl;

re# clear;

re# updo.n;

.ire [:! 8;

updo.ncountermod uut (/cl(cl),/clear(clear), /updo.n(updo.n), /8(8) );

initial be#in

cl $ ;

clear $ ;

updo.n $ ;

0+ clear$'1b';

0+ clear$'1b;

0' updo.n$'1b';



end

al.a4" 0+ cl$%cl;

initial 0'+ 2"top;

endmodule

ing Counter

Circuit 5iagra4 for ring counter



Count Table

Verilog code for ring counter

module ring_count (Resetn !loc" #$%

&arameter n ' 5%

in&ut Resetn !loc"%

out&ut n)1*0+ #%

reg n) 1*0+ #%

al,a-s .(&osedge !loc"$

i/ (Resetn$

begin

#4*1+ ' 0%

cl" #a #b #c #d

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1



#0+ ' 1%

end

else

# ' #3*0+ #4+%

endmodule

Bonon Counter

Circuit 5iagra4 for Bonon counter

1 2 3 ( 5 4

6101112131(

A B C D

$A $B $C $D7cc C891

outputs

4(8S65

2 1

A1A



Count Table

Verilog code

module stc(cl"clrrst$%

iput cl,clr;out&ut rst%

reg rst%

al,a-s.(negedge cl"$

begin

i/(clr$

begin

'1b0%

end

else

begin

't%

r'%

s'r%

t's%

end

end



endmodule

Pseudo Random Sequence Generator in Verilog

3"eudo Random ?e8uence i" .idel4 u"ed in "pread "pectrum communication, to "preadand de"pread t5e in6ormation "e8uence/ 5e 6ollo.in# dia#ram "5o." a 3A "e8uence

#enerator .5ic5 5a" memor4 element", lead" to proce""in# #ain 7 ( ')/ Fccordin#to t5e dia#ram, i6 t5e initial "tate i" all ero, t5en t5e "e8uence .ill al"o be all ero".5ic5 i" not u"able/

Behaioural Model

module :SeL!en( input clM, reset, output s% ); re s1, s2, s%;

http://tjeyamy.blogspot.in/2012/05/pseudo-random-sequence-generator-in.html

http://tjeyamy.blogspot.in/2012/05/pseudo-random-sequence-generator-in.html



wire s'; ** I>-9 2 A>>+.+ assin s' s1 < s%; ** S.A.8 IACH+8

alwa?s @ (posede clM or reset) #ein** ++.+A9 S.A.8 SH-9>4. B8 ''' N 1'' if(reset) #ein s1 1; s2 '; s% '; end else #ein

s1 s'; s2 s1; s% s2; end end

endmodule

Test Bench

module .est_:SeL!en; ** +nputs re clM; re reset; ** utputs

wire s%; ** +nstantiate the -nit -nder .est (--.) :SeL!en uut ( /clM(clM),/reset(reset),/s%(s%)

); initial #ein ** +nitiali0e +nputs clM '; reset '; ** ait 1'' ns for lo#al reset to finish

31''; ** Add stimulus here 31' reset 1; 31' reset '; 32'' 5finish; end alwa?s #ein 3F clM EclM; end



** :K+. S8O-8C8 alwa?s @ (posede clM) 5write(67#6,s%);

endmodule

Output

''111'1''111'1''111'1

ACCUMULATOR VERILOG CODE

module accumod (in, acc, cl, re"et);

input [7:! in;

input cl, re"et;

output [7:! acc;

re# [7:! acc;

al.a4">(cl) be#in

i6(re"et)

acc B$ H1b;

el"e

acc B$ acc in;

end

endmodule



TEST BENCH

module accumt-b;

re# [7:! in;

re# cl;

re# re"et;

.ire [7:! acc;

accumod uut ( /in(in), /acc(acc),/cl(cl),/re"et(re"et) );

initial be#in

0+ re"etB$'1b';

0+ re"etB$'1b;

cl $'1b;

in $ H1b';

0+ in $ H1b';

0+ in $ H1b'';

end

al.a4" 0' cl $ %cl;

initial0'H 2"top;



endmodule

I4ple4entation of "bit (agnitude Co4parator

osider t!o 4bit biary umbers ad 6 suc* t*at

A & A3 A2 A1 A0

B & B3 B2 B1 B0

( A ' B$ ' x3 x2 x1 x0

Circuit 5iagra4



Verilog code)Abtract level+

4odule co4pare)A*;*y+,

input -#:0. A*;,

output -$:0. y,

reg y,

al/ay )A or ;+

if)A22;+

y2#3b001,

ele if)A>;+

y2#3b010,



ele

y2#3b100,

end4odule

Verilog code for "bit 4agnitude co4parator

4odule co4pare)A*;*%*y*D+,

input -#:0. A*;,

output %* y*D,

/ire %0*%1*%$*%#,

aign %02))?A-0.E;-0.+ )A-0.E?;-0.++,

aign %12))?A-1.E;-1.+ )A-1.E?;-1.++,

aign %$2))?A-$.E;-$.+ )A-$.E?;-$.++,

aign %#2))?A-#.E;-#.+ )A-#.E?;-#.++,

aign %2%0E%1E%$E%#,

aign y2))A-#.E?;-#.)%#EA-$.E?;-$.+)%#E%$EA-1.E?;-1.+)%#E%$E%1EA-0.E?;-0.++,

aign D2))?A-#.E;-#.)%#E?A-$.E;-$.+)%#E%$E?A-1.E;-1.+)%#E%$E%1E?A-0.E;-0.++,

end4odule

DESIGN F MDIFIED BT! M"LTI#LIER

AIM:

:o desin & modiied /oot; multiplie! in 7e!ilo &nd to simul&te < snt;esis t;e s&me usin =I8I>= IS" :ool?

T!ER$:

Bit @&i! "ncodin (B@") is & modiied /oot; multiplic&tion tec;niue w;e!e t;e num/e! o &dditions (no o p&!ti&l

p!oducts so ene!&ted) is !educed !om n to n2 o! &n n /it multiplie!?

Bit p&i! encodin o & multiplie! eE&mines 3 /its &t & time &nd c!e&tes & 2-/it code w;ose F&lues dete!mines

w;et;e! to



Add t;e multiplic&nd

S;it t;e multiplic&nd / 1 /it &nd t;en &dd

Su/t!&ct t;e multiplic&nd (&ddin 2s complement o t;e multiplic&nd to t;e p!oduct)

S;it t;e 2s complement o t;e multiplic&nd to t;e let / 1 /it &nd t;en &dd

:o onl s;it t;e multiplic&nd to t;e loc&tion co!!espondin to t;e neEt /it-p&i!?

:;e i!st step o B@" &lo!it;m is seeded wit; & F&lue o 0 in t;e !eiste! cell to t;e !i;t o t;e 8SB o t;e multiplie!

wo!d? Su/seuent &ctions depend on t;e F&lue o t;e !ecoded /it-p&i!? :;e indeE i inc!ements / two until t;e wo!d

is eE;&usted? I t;e wo!d cont&ins &n odd num/e! o /its, its sin /it must /e eEtended / one /it to &ccommod&te

t;e !ecodin sc;eme? Recodin diFides t;e multiplie! wo!d / 2, so t;e num/e! o possi/le &dditions is !educed / &

&cto! o 2? :;e !ules o! /it-p&i! encodin &!e summ&!iGed in t;e t&/le p!oFided in t;e let?

S"RCE CDE:

module booth #(parameter WIDTH=4)

( input clk,

input enable,

input [WIDTH-1!" multiplier,

input [WIDTH-1!" multiplicand,

output re [$%WIDTH-1!" product)&

parameter ID' = $b!!, // state encodings

*DD = $b!1,

+HIT = $b1!,

.T/.T = $b11&

re [1!" current0tate, ne2t0tate& // state registers.

re [$%WIDTH31!" a0re,0re,p0re,um0re& // computational values.

re [WIDTH-1!" iter0cnt& // iteration count for determining when done.

ire [WIDTH!" multiplier0ne& // negative value of multiplier

ala5 6(poede clk)

i7 (8enable) current0tate = ID'&

ele current0tate = ne2t0tate&

ala5 6% bein

ne2t0tate = $b2&

cae (current0tate)

ID' i7 (enable) ne2t0tate = *DD&

ele ne2t0tate = ID'&

*DD ne2t0tate = +HIT&

+HIT i7 (iter0cnt==WIDTH) ne2t0tate = .T/.T&

ele ne2t0tate = *DD&

.T/.T ne2t0tate = ID'&



endcae

end

// negative value of multiplier.

ain multiplier0ne = -9multiplier[WIDTH-1",multiplier:&

// algorithm implemenation details.

ala5 6(poede clk) bein

cae (current0tate)

ID' bein

a0re ;= 9multiplier[WIDTH-1",multiplier,9(WIDTH31)91b!:::&

0re ;= 9multiplier0ne,9(WIDTH31)91b!:::&

p0re ;= 99(WIDTH31)91b!::,multiplicand,1b!:&

iter0cnt ;= !&

end

*DD bein cae (p0re[1!")

$b!1 um0re ;= p0re3a0re&

$b1! um0re ;= p0re30re&

$b!!,$b11 um0re ;= p0re&

endcae

iter0cnt ;= iter0cnt 3 1&

end

+HIT bein

p0re ;= 9um0re[$%WIDTH31",um0re[$%WIDTH311":&

end

.T/.T product = p0re<<1&

endcae

end //always ends

endmodule //end of source code

TEST BENC!:

module tetbench&

Input

re clk&

re enable&

re [>!" multiplier&

re [>!" multiplicand&

utput

ire done&

ire [?!" product&



Intantiate the .nit .nder Tet (..T)

booth uut (

@clk(clk),

@enable(enable),

@multiplier(multiplier), @multiplicand(multiplicand),

@product(product)

)&

initial

clk=1b!&

ala5

#A clk=Bclk&

initial bein

enable = !& multiplier = !&

multiplicand = !&

#$A! enable = 1&

multiplier = 4b!!11&

multiplicand = 4b!!11&

#$A! enable = 1&

multiplier = 4b1!1!&

multiplicand = 4b!1!!&

#$A! enable = 1&

multiplier = 4b!!1!&

multiplicand = 4b1!!1&

#$A! enable = 1&

multiplier = 4b1!1!&

multiplicand = 4b11!!&

#$A!&

end

endmodule //end of testbench

)O+

BOOTHS MULTIPLIER



VERILOG CODE:

module multi&lier(&rod bus- mc m& cl" start$%

out&ut 15*0+ &rod%

out&ut bus-%

in&ut 7*0+ mc m&%

in&ut cl" start%

reg 7*0+ A # %

reg #_1%

reg 3*0+ count%

,ire 7*0+ sum dierence%

al,a-s .(&osedge cl"$

begin

i/ (start$ begin

A ' 8b0%

' mc%

# ' m&%

#_1 ' 1b0%

count ' 4b0%

end

else begin

case (#0+ #_1$

2b0_1 * A # #_1 ' sum7+ sum #%

2b1_0 * A # #_1 ' dierence7+ dierence #%



de/ault* A # #_1 ' A7+ A #%

endcase

count ' count 9 1b1%

end

end

alu adder (sum A 1b0$% );//MODULE INSTANTIATION

::alu subtracter (dierence A 1b1$% );//MODULE INSTANTIATION

assign &rod ' A #%

assign bus- ' (count 8$%

endmodule

//The followin i! "n "l#$

//I% i! "n "&&e'( #% *"+"le of !#%'"*%ion:

//Re*"ll %h"% !#%'"*%ion ,e"n! "&&in %he %wo-! *o,+le,en%..

//" . " 0 1.) " 0 1in2e'%e& 0 3)

//The 3 will e *o,in in "! *in 1*"''4.in)

module alu(out a b cin$%

out&ut 7*0+ out%

in&ut 7*0+ a%

in&ut 7*0+ b%

in&ut cin%

assign out ' a 9 b 9 cin%

endmodule



TEST BENCH:

module testbenc;%

reg cl" start%

reg 7*0+ a b%

,ire 15*0+ ab%

,ire bus-%

multi&lier multi&lier1(ab bus- a b cl" start);//MODULE INSTANTIATION

initial begin

cl" ' 0%

<dis&la-(=>rst e?am&le* a ' 3 b ' 17=$%

a ' 3% b ' 17% start ' 1% @50 start ' 0%

@80 <dis&la-(=>rst e?am&le done=$%

<dis&la-(=second e?am&le* a ' 7 b ' 7=$%

a ' 7% b ' 7% start ' 1% @50 start ' 0%

@80 <dis&la-(=second e?am&le done=$%

<>nis;%

end

al,a-s @5 cl" ' cl"%

al,a-s .(&osedge cl"$ <strobe(=ab* d bus-* d at time't= ab bus- <stime$%

endmodule

O!"!:

irst eample: a & 3 b & 17

ab: 17 busy: 1 at time& 5



ab: 17 busy: 1 at time& 15ab: 17 busy: 1 at time& 25



ab: "51"0 busy: 1 at time& 55ab: 1$" busy: 1 at time& "5

ab: $# busy: 1 at time& 75

ab: 4$ busy: 1 at time& #5ab: "517" busy: 1 at time& $5



irst eample doe

secod eample: a & 7 b & 7ab: 7 busy: 1 at time& 135


ab: 7 busy: 1 at time& 1"5ab: 7 busy: 1 at time& 175

ab: "4"43 busy: 1 at time& 1#5

ab: "50#$ busy: 1 at time& 1$5ab: "5312 busy: 1 at time& 205

ab: 7#4 busy: 1 at time& 215

ab: 3$2 busy: 1 at time& 225ab: 1$" busy: 1 at time& 235

ab: $# busy: 1 at time& 245

ab: 4$ busy: 0 at time& 255secod eample doe





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