DATE: / / EX NO: PAGE NO:LOGIC GATES Aim: To write verilog code
to verify the function of all logic gates by simulating the
programme. Software used:Xilinx 14.3Isim simulator Theory:Logic
gates are the basic building blocks of any digital electronic
circuite.We have seven types of logic gates in which three gates
which are AND,ARE,NOT gates are called basic logic gates and other
type of logic gates are NOR,NAND,XOR,XNOR gates in which NOR,NAND
gates are called universal gates because by using these gates we
can develop any logic gate.XOR gate is called odd number of ones
detector. Programing code:`timescale 1ns / 1psmodule logic_gates(
input a,b, output and_op, or_op, not_op, nand_op, nor_op, xor_op,
xnor_op );assign not_op=~a; NOT Gateassign and_op=a&b; AND
Gateassign or_op=a|b; OR Gateassign nand_op=~(a&b); NAND Gate
assign nor_op=~(a|b); NOR Gateassign xor_op=a^b; XOR Gateassign
xnor_op=~(a^b); XNOR Gateendmodule
Simulation results:
Synthesis results:
Result:Hence, we verified the function of all logic gates and
got output results exactly by simulating the programme and also
obtained the synthesis result.FOUR BIT FULL ADDER Aim:To write
verilog code to verify the function of four bit full adder by
simulating the programme. Software used:Xilinx 14.3Isim simulator
Theory:Full adder is a combinational circuite, where it adds two
one bits and carry bit at a time. In order to add two numbers which
are n bit we use n full adders. To add two numbers of four bit we
use four full adders. Tis is called four bit full adder.
Programing code:`timescale 1ns / 1psmodule fa ( input a,b,c,
output sum, Full adder output carry );assign sum=a^b^c;assign
carry=(a&b)|(b&c)|(c&a);endmodulemodule fbfa (input
[3:0] a,input [3:0] b,input c,output [3:0] sum,output carry); Four
bit full adderwire c1,c2,c3; fa fa1 (a[0],b[0],c,sum[0],c1); fa fa2
(a[1],b[1],c1,sum[1],c2); fa fa3 (a[2],b[2],c2,sum[2],c3); fa fa4
(a[3],b[3],c3,sum[3],carry);endmodule
Simulation results: Synthesis results:
Result:Hence, we verified the function of four bit full adder
and got output results exactly by simulating the programme and also
obtained the synthesis result.
FOUR BIT FULL SUBTRACTOR Aim:To write verilog code to verify the
function of four bit full subtractor by simulating the programme.
Software used:Xilinx 14.3Isim simulator Theory:Full subtractor is a
combinational circuite, where it subtracts two one bits and carry
bit at a time. In order to subtract two numbers which are n bit we
use n full subtractors. To subtract two numbers of four bit we use
four full subtractors. Tis is called four bit full subtractor.
Programing code:`timescale 1ns / 1psmodule fs ( input a,b,c,
output diff, Full subtractor output barrow ); assign
diff=a^b^c;assign
barrow=(~a&b)|(~a&c)|(b&c);endmodulemodule fbfs ( input
[3:0] a, input [3:0] b, input c, output [3:0] diff, output bar );
Four bit full subtractor wire b1,b2,b3;fs fs1
(a[0],b[0],c,diff[0],b1);fs fs2 (a[1],b[1],b1,diff[1],b2);fs fs3
(a[2],b[2],b2,diff[2],b3);fs fs4
(a[3],b[3],b3,diff[3],bar);endmodule
Simulation results: Synthesis results: Result:Hence, we verified
the function of four bit full subtractor and got output results
exactly by simulating the programme and also obtained the synthesis
result.
UP COUNTER Aim:To write verilog code to verify the function of
up counter by simulating the programme. Software used:Xilinx
14.3Isim simulator Theory:Counter is a sequential circuite which
countes the number of clock pulses applied and can also be used as
square wave form generator,to measure the distance and as frequency
dividers. For n bit counter we have to use n T_flip flops. In this
the flip flop to which the external clock is applied will act as
LSB bit and the clocks to all other higher bit flip flops is
applied from the outputs of lower bit flip flops. It is ,
therefore, called as asynchronoun counter. In up conter the counter
data will be increased by one for every negative edge clock pulse
Programing code: `timescale 1ns / 1psmodule dffuc ( output reg q,
input d,clk,rst ); D-Flip Flopalways @ (negedge clk or posedge rst)
if (rst= =1)q=1'b0; elseq=d;endmodulemodule tffuc (output q, input
t,clk,rst); T-Flip Flop wire w; assign w=t^q;dffuc dffuc1
(q,w,clk,rst);endmodulemodule counter_up ( input t,clk,rst, output
[3:0]q ); Up counterwire [2:0]w; tffuc tffuc1
(w[0],t,clk,rst);tffuc tffuc2 (w[1],t,w[0],rst);tffuc tffuc3
(w[2],t,w[1],rst);tffuc tffuc4 (q[3],t,w[2],rst);assign
q[0]=w[0];assign q[1]=w[1];assign q[2]=w[2];endmodule
Simulation results:
Synthesis results:
Result:Hence, we verified the function of up counter and got
output results exactly by simulating the programme and also
obtained the synthesis result.DOWN COUNTER Aim:To write verilog
code to verify the function of down counter by simulating the
programme. Software used:Xilinx 14.3Isim simulator Theory:Counter
is a sequential circuite which countes the number of clock pulses
applied and can also be used as square wave form generator,to
measure the distance and as frequency dividers. For n bit counter
we have to use n T_flip flops. In this the flip flop to which the
external clock is applied will act as LSB bit and the clocks to all
other higher bit flip flops is applied from the outputs of lower
bit flip flops. It is , therefore, called as asynchronoun counter.
In down conter the counter data will be decreased by one for every
positive edge clock pulse Programing code: `timescale 1ns /
1psmodule dffdc( output reg q, input d,clk,rst ); D-Flip Flopalways
@ (posedge clk or posedge rst) if (rst= =1)q=1'b0;
elseq=d;endmodulemodule tffdc (output q, input t,clk,rst); T-Flip
Flop wire w; assign w=t^q;dffdc dffdc1
(q,w,clk,rst);endmodulemodule counter_dn ( input t,clk,rst, output
[3:0]q ); Down counterwire [2:0]w;tffdc tffdc1
(w[0],t,clk,rst);tffdc tffdc2 (w[1],t,w[0],rst);tffdc tffdc3
(w[2],t,w[1],rst);tffdc tffdc4 (q[3],t,w[2],rst);assign
q[0]=w[0];assign q[1]=w[1];assign q[2]=w[2];endmodule
Simulation results: Synthesis results:
Result:Hence, we verified the function of down counter and got
output results exactly by simulating the programme and also
obtained the synthesis result.CARRY LOOK AHEAD ADDER Aim:To write
verilog code to verify the function of carry look ahead adder by
simulating the programme. Software used:Xilinx 14.3Isim simulator
Theory:In order to avoid the propagation delay of carry from input
to output present in parallel adder we go for carry look ahead
adder.This is faster than parallel adder. Programing
code:`timescale 1ns / 1psmodule cla ( output [3:0]sum, output
carry, input [3:0]a, input [3:0]b, input c );wire
p0,p1,p2,p3,g0,g1,g2,g3,c0,c1,c2,c3;assign p0=a[0]^b[0];assign
p1=a[1]^b[1]; Propagation termassign p2=a[2]^b[2];assign
p3=a[3]^b[3];
assign g0=a[0]&b[0];assign g1=a[1]&b[1];assign
g2=a[2]&b[2]; Generation termassign g3=a[3]&b[3];
assign sum[0]=p0^c;assign sum[1]=p1^c0;assign sum[2]=p2^c1; Sum
termassign sum[3]=p3^c2;
assign c0=(p0&c)|g0;assign c1=(p1&c0)|g1;assign
c2=(p2&c1)|g2; Carry termassign c3=(p3&c2)|g3;
assign carry=c3;endmodule
Simulation results:
Synthesis results:
Result:Hence, we verified the function of carry look ahead adder
and got output results exactly by simulating the programme and also
obtained the synthesis result.SISO REGISTER Aim:To write verilog
code to verify the function of siso register by simulating the
programme. Software used:Xilinx 14.3Isim simulator Theory:Register
is a sequential circuite. An n bit register requires n number of
D_flip flops to store n bits. In register all flip flops are
applied with same clock frequency from external clock. It is,
therefore, called as synchronous circuite. In siso register the
data is entered sequentially at the input and comes out
sequentially at the output. Siso takes seven clock pulses to appear
the data at the output which is given at the input. Programing
code:`timescale 1ns / 1psmodule dffsiso ( output reg q, input
d,clk,rst );always @(posedge clk or posedge rst) D_Flip Flop if
(rst= =1)q=1'b0; elseq=d;endmodulemodule siso (out,in,clk,rst);
input in,clk,rst; output out; wire [2:0]w; SISO Registerdffsiso d1
(w[2],in,clk,rst);dffsiso d2 (w[1],w[2],clk,rst);dffsiso d3
(w[0],w[1],clk,rst);dffsiso d4 (out,w[0],clk,rst);endmodule
Simulation results:
Synthesis results:
Result:Hence, we verified the function of siso register and got
output results exactly by simulating the programme and also
obtained the synthesis result.SIPO REGISTER Aim:To write verilog
code to verify the function of sipo register by simulating the
programme. Software used:Xilinx 14.3Isim simulator Theory:Register
is a sequential circuite. An n bit register requires n number of
D_flip flops to store n bits. In register all flip flops are
applied with same clock frequency from external clock. It is,
therefore, called as synchronous circuite. In sipo register the
data is entered sequentially at the input and comes out paralally
at the output. Sipo takes four clock pulses to appear the data at
the output which is given at the input. Programing code:`timescale
1ns / 1psmodule dffsipo ( output reg q, input d,clk,rst );always@
(posedge clk or posedge rst) D_Flip Flop if (rst= =1)q=1'b0;
elseq=d;endmodulemodule sipo ( input in,clk,rst, output [3:0] out
SIPO Register ); wire w1,w2,w3,w4;dffsipo d1
(w4,in,clk,rst);dffsipo d2 (w3,w4,clk,rst);dffsipo d3
(w2,w3,clk,rst);dffsipo d4 (w1,w2,clk,rst);assign
out={w4,w3,w2,w1};endmodule Simulation results:
Synthesis results:
Result:Hence, we verified the function of siso register and got
output results exactly by simulating the programme and also
obtained the synthesis result.PISO REGISTER Aim:To write verilog
code to verify the function of piso register by simulating the
programme. Software used:Xilinx 14.3Isim simulator Theory:Register
is a sequential circuite. An n bit register requires n number of
D_flip flops to store n bits. In register all flip flops are
applied with same clock frequency from external clock. It is,
therefore, called as synchronous circuite. In piso register the
data is entered paralally at the input and comes out sequentially
at the output. Piso takes four clock pulses to appear the data at
the output which is given at the input. Programing code:`timescale
1ns / 1psmodule dffsipo ( output reg q, input d,clk,rst );always@
(posedge clk or posedge rst) D_Flip Flop if (rst= =1)q=1'b0;
elseq=d;endmodulemodule piso (input i0,i1,i2,i3,sl,clk,rst,output q
PISO Register);wire [2:0]w,p;assign
p[0]=(w[0]&sl)|(i0&~sl);assign
p[1]=(w[1]&sl)|(i1&~sl);assign
p[2]=(w[2]&sl)|(i2&~sl);dffpiso d1
(w[2],i3,clk,rst);dffpiso d2 (w[1],p[2],clk,rst);dffpiso d3
(w[0],p[1],clk,rst);dffpiso d4 (q,p[0],clk,rst);endmodule
Simulation results:
Synthesis results:
Result:Hence, we verified the function of piso register and got
output results exactly by simulating the programme and also
obtained the synthesis result.PIPO REGISTER Aim:To write verilog
code to verify the function of pipo register by simulating the
programme. Software used:Xilinx 14.3Isim simulator Theory:Register
is a sequential circuite. An n bit register requires n number of
D_flip flops to store n bits. In register all flip flops are
applied with same clock frequency from external clock. It is,
therefore, called as synchronous circuite. In pipo register the
data is entered paralally at the input and comes out paralally at
the output. Pipo takes two clock pulses only to appear the data at
the output which is given at the input. Programing code:`timescale
1ns / 1psmodule dffsipo ( output reg q, input d,clk,rst );always@
(posedge clk or posedge rst) D_Flip Flop if (rst= =1)q=1'b0;
elseq=d;endmodulemodule pipo (input i0,i1,i2,i3,clk,rst,output
[3:0]q PIPO Register );dffpipo d1 (q[0],i0,clk,rst);dffpipo d2
(q[1],i1,clk,rst);dffpipo d3 (q[2],i2,clk,rst);dffpipo d4
(q[3],i3,clk,rst);endmodule Simulation results:
Synthesis results:
Result:Hence, we verified the function of pipo register and got
output results exactly by simulating the programme and also
obtained the synthesis result.ENCODER Aim:To write verilog code to
verify the function of encoder by simulating the programme.
Software used:Xilinx 14.3Isim simulator Theory:Encoder is a
combinational circuite, which is used to convert decimal or octal
or hexadecimal numbers to binary or bcd codes. It hase n input
lines and m output lines and one enable pin. The disadvantage in
this is that at a time only one input is activated. If more than
one input is activated at a time then it can not give the
corresponding binary or bcd code. Programing code:`timescale 1ns /
1psmodule encoder ( input d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,e, output
[3:0] y );assign
y[0]=(e&d1)|(e&d3)|(e&d5)|(e&d7)|(e&d9);assign
y[1]=(e&d2)|(e&d3)|(e&d6)|(e&d7);assign
y[2]=(e&d4)|(e&d5)|(e&d6)|(e&d7);assign
y[3]=(e&d8)|(e&d9);endmodule Simulation results:
Synthesis results:
Result:Hence, we verified the function of encoder and got output
results exactly by simulating the programme and also obtained the
synthesis result.
PRIORITY ENCODER Aim:To write verilog code to verify the
function of priority encoder by simulating the programme. Software
used:Xilinx 14.3Isim simulator Theory:Encoder is a combinational
circuite, which is used to convert decimal or octal or hexadecimal
numbers to binary or bcd codes. It hase n input lines and m output
lines and one enable pin. The disadvantage in encoder is overcome
by priority encoder. When more than one input is activated at a
time then it gives binary code corresponding to highest priority
input. Programing code:`timescale 1ns / 1psmodule pri_encoder(input
d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,e,output [3:0]y);assign
y[0]=(e&d9)|(e&~d9&~d8&d7)|(e&~d9&~d8&~d7&~d6&d5)|
(e&~d9&~d8&~d7&~d6&~d5&~d4&d3)|
(e&~d9&~d8&~d7&~d6&~d5&~d4&~d3&~d2&d1);assign
y[1]=(e&~d9&~d8&d7)|(e&~d9&~d8&~d7&d6)|
(e&~d9&~d8&~d7&~d6&~d5&~d4&d3)|
(e&~d9&~d8&~d7&~d6&~d5&~d4&~d3&d2);assign
y[2]=(e&~d9&~d8&d7)|(e&~d9&~d8&~d7&d6)|
(e&~d9&~d8&~d7&~d6&d5)|
(e&~d9&~d8&~d7&~d6&~d5&d4);assign
y[3]=(e&d9)|(e&~d9&d8);endmodule
Simulation results:
Synthesis results: Result:Hence, we verified the function of
priority encoder and got output results exactly by simulating the
programme and also obtained the synthesis result.
DECODER Aim:To write verilog code to verify the function of
decoder by simulating the programme. Software used:Xilinx 14.3Isim
simulator Theory:Decoder is a combinational circuite, which is used
to convert binary or bcd codes to decimal or octal or hexadecimal
number. It hase n input lines and m output lines and one enable
pin. Programing code:`timescale 1ns / 1psmodule decoder (input
i0,i1,i2,i3,e,output [9:0]d );assign
d[0]=e&~i3&~i2&~i1&~i0;assign
d[1]=e&~i3&~i2&~i1&i0;assign
d[2]=e&~i3&~i2&i1&~i0;assign
d[3]=e&~i3&~i2&i1&i0;assign
d[4]=e&~i3&i2&~i1&~i0;assign
d[5]=e&~i3&i2&~i1&i0;assign
d[6]=e&~i3&i2&i1&~i0;assign
d[7]=e&~i3&i2&i1&i0;assign
d[8]=e&i3&~i2&~i1&~i0;assign
d[9]=e&i3&~i2&~i1&i0;endmodule
Simulation results:
Synthesis results:
Result:Hence, we verified the function of decoder and got output
results exactly by simulating the programme and also obtained the
synthesis result.
ARITHMETIC LOGIC UNIT Aim: To write verilog code to verify the
function of ALU by simulating the programme. Software used:Xilinx
14.3Isim simulator Theory:The function of arithmetic logic unit is
to perform all arithmetic operations (sum,addition,multiplication
e.t.c) and logical operations (logical and,logical or,logical not
e.t.c). Every processor has its own alu. Programing code:`timescale
1ns / 1psmodule alu_4btbyvector (x,y,s,z); input [2:0] x,y; input
[3:0] s; output [7:0] z; reg [7:0] z; always @ (s,x,y) case
(s)4'b0000 : z = x+y;4'b0001 : z = x-y;4'b0010 : z = x*y;//4'b0011
: z = x/y;4'b0100 : z = ~x;4'b0101 : z = x&y;4'b0110 : z =
x|y;4'b0111 : z = x^y;4'b1000 : z = ~(x&y);4'b1001 : z =
~(x|y);4'b1010 : z = ~(x^y);4'b1011 : z = x z < = "1111110"
;when "0001" = > z < = "0110000" ;when "0010" = > z < =
"1101101" ;when "0011" = > z < = "1111001" ;when "0100" =
> z < = "0100111" ;when "0101" = > z < = "1011011"
;when "0110" = > z < = "1011111" ;when "0111" = > z < =
"1110000" ;when "1000" = > z < = "1111111" ;when "1001" =
> z < = "1111011" ;when others = > z < = "0000000" ;end
case ;end process ;end Behavioral ;
Simulation results:
Synthesis results:
Result:Hence, we verified the function of bcd to 7 segment
display decoder and got output results exactly by simulating the
programme and also obtained the synthesis result.
ENCODER Aim:To write VHDL code to verify the function of encoder
by simulating the programme. Software used:Xilinx 14.3Isim
simulator Theory:Encoder is a combinational circuite, which is used
to convert decimal or octal or hexadecimal numbers to binary or bcd
codes. It hase n input lines and m output lines and one enable pin.
The disadvantage in this is that at a time only one input is
activated. If more than one input is activated at a time then it
can not give the corresponding binary or bcd code. Programing
code://Using VHDLlibrary IEEE ;use IEEE.STD_LOGIC_1164.ALL ;entity
vh_encoder isport ( d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, enable
: in std_logic ; y : out std_logic_vector ( 3 downto 0 ) ) ;end
vh_encoder ;architecture Behavioral of vh_encoder isbeginprocess (
d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 )variable sel :
std_logic_vector ( 9 downto 0 ) ;beginsel : = d9 & d8 & d7
& d6 & d5 & d4 & d3 & d2 & d1 & d0 ;if
enable = '1' thencase sel is when "0000000001" = > y < =
"0000" ;when "0000000010" = > y < = "0001" ;when "0000000100"
= > y < = "0010" ;when "0000001000" = > y < = "0011"
;when "0000010000" = > y < = "0100" ;when "0000100000" = >
y < = "0101" ;when "0001000000" = > y < = "0110" ;when
"0010000000" = > y < = "0111" ;when "0100000000" = > y
< = "1000" ;when "1000000000" = > y < = "1001" ;when
others = > y < = "ZZZZ" ;end case ;elsey < = "ZZZZ" ;end
if ;end process ;end Behavioral ;
Simulation results:
Synthesis results:
Result:Hence, we verified the function of encoder and got output
results exactly by simulating the programme and also obtained the
synthesis result.
DECODER Aim:To write VHDL code to verify the function of decoder
by simulating the programme. Software used:Xilinx 14.3Isim
simulator Theory:Decoder is a combinational circuite, which is used
to convert binary or bcd codes to decimal or octal or hexadecimal
number. It hase n input lines and m output lines and one enable
pin. Programing code://Using VHDLlibrary IEEE;use
IEEE.STD_LOGIC_1164.ALL ;entity vh_decoder isport ( i0, i1, i2, i3,
enable : in std_logic ; D : out std_logic_vector ( 0 to 9 ) ) ;end
vh_decoder ;architecture Behavioral of vh_decoder isbeginprocess (
i0, i1, i2, i3 )variable sel : std_logic_vector ( 0 to 3) ;beginsel
: = i3 & i2 & i1 & i0 ;if enable = '1' thencase sel
iswhen "0000" = > D < = "0000000001" ;when "0001" = > D
< = "0000000010" ;when "0010" = > D < = "0000000100" ;when
"0011" = > D < = "0000001000" ;when "0100" = > D < =
"0000010000" ;when "0101" = > D < = "0000100000" ;when "0110"
= > D < = "0001000000" ;when "0111" = > D < =
"0010000000" ;when "1000" = > D < = "0100000000" ;when "1001"
= > D < = "1000000000" ;when others = > D < =
"ZZZZZZZZZZ" ;end case ;elseD < = "ZZZZZZZZZZ" ;end if ;end
process ;end Behavioral ; Simulation results:
Synthesis results:
Result:Hence, we verified the function of decoder and got output
results exactly by simulating the programme and also obtained the
synthesis result.
MULTIPLEXER Aim:To write VHDL code to verify the function of
multiplexer by simulating the programme. Software used:Xilinx
14.3Isim simulator Theory:Multiplexer is a combinational
circuite,which has many inputs and single output.It acts as
parallel to serial converter and also called as many to one
circuit.It has n selection lines for 2n input lines.It selects one
input at a time and connects it to output line. Programing
code://Using VHDLlibrary IEEE ;use IEEE.STD_LOGIC_1164.ALL ;entity
Vh_mux isport (d0,d1,d2,d3,s0,s1 : in std_logic ; y:out std_logic )
;end Vh_mux;architecture Behavioral of Vh_mux isbeginprocess
(d0,d1,d2,d3,s0,s1)variable sel : std_logic_vector (1 downto 0)
;beginsel : = s1& s0 ;case sel iswhen "00" = > y < = d0
;when "01" = > y < = d1 ;when "10" = > y < = d2 ;when
"11" = > y < = d3 ;when others = > y < = ' Z ' ;end
case ;end process ;end Behavioral ; Simulation results: Synthesis
results:
Result:Hence, we verified the function of multiplexer and got
output results exactly by simulating the programme and also
obtained the synthesis result.
