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Verilog forSequentialCircuits
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Verilo for Se uential Circuits
Sequential circuits are modeled in an alwaysblock
Example of an implied memoryelement
The gated D latch
Verilog assumes the value of Qmust be maintained if Clk is 0
andtherefore synthesizes a latch
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Verilo for D Fli -Flo
Sensitivity list needs to specify clock edge, not just
change in level Can specify: posedge or negedge
Verilog will use flip-flops to synthesizecircuits that are
edge-triggered
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Verilo for T and JK Fli -Flo s
Negative edge triggered versions
Also provides complemented outputs
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Verilo Exam le
=
x3
D Q
Q
gx1
x2
D Q f
Clock Q
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Verilo Exam le: Reversed Order
Order matters inside an always block!
D Q
Q
gx3
x1
Clock Q
x2
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Blockin Assi nments
The order of statements inside an always block can
affect the synthesized design All previous examples use blocking
assignments
order in which they are written
D QD Q1
Q
2
treated as Q2 = D since Q1 = D
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Non-Blockin Assi nments
What if you wanted a cascaded design for the
previous example? The assignment to Q2 should be from the
previous Q1
clock edge
The LHS of a non-blocking assignment is updated after allRHS
values for all assi nments have been evaluated
D Q
QClock
D Q
Q
D
non-blocking assignment
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Non-Blockin Exam le
Compare this to the earlier exampleusing blocking
assignments
D Q
Q
gx3
D fx1
Clock Q
x2
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Addin As nchronous Clear
The sensitivity list cannot mix edge triggered and
level sensitive events Must make resetedge-triggered, but on a
different edge
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S nchronous Clear
The only change is in the sensitivity list
ResetN overrides the input
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Verilo for N-Bit Re ister
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Verilo for N-Bit Re ister With Load
Add a load enable input
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Verilo for 4-Bit Shift Re ister
One technique: build a Q3 Q2 Q1 Q0
Parallel output
simple 2X1 MUXcontrolled D flip-flop
D QQ
D QQ
D QQ
D QQ
ClockShift/LoadSerial npu
Provide arallel access includinload) and shift right
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4-Bit Shift Re ister: Continued
behavioral and structural styles
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N-Bit Shift Re ister: Behavioral St le
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N-Bit U Counter
Provide an n-bit up counter with asynchronous clearand an enable
control
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N-Bit U Counter With Load
Provide an n-bit up counter with asynchronous clear,an enable
control, and parallel load
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N-Bit U /Down Counter With Load
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Alternate Version of U/D Counter
blocking assignments are executede ore non- oc ng ones
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Good Codin St le
As a matter of good coding style
Do not mix blocking and non-blocking assignments in thesame
always block
It may work, but you may confuse yourself!
Use separate always blocks when you need both types
Repeating earlier rules
Use blocking assignments for combinational logic
Use non-blocking assignments for sequential logic,
andlatches
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Best Version of U/D Counter
This style separatesblockin and non-blockin
assignments into separatealways blocks
