Verilog _combinational Circuit

8/3/2019 Verilog _combinational Circuit

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Verilog for Combinational Circuits


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Verilog includes ways to specify

era s n var ous ases

Binary literals 8b0000_0000

8b0xx0_1xx14b10_11 Hexadecimal literals 32h0a34_def1

Underscoresare ignored

Decimal literals 32d42

Base format(d,b,o,h)

Decimal number

representing size in bitsWell learn how to

actually assign literals tonets a little later


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Histor of hardware desi n lan ua es

Data types Structural Verilog

Functional Verilog Gate level

High-level behavioralFA FA FA FA

mo u e a er npu : , ,

output cout,

output [3:0] S );

wire c0, c1, c2;

FA fa0( A[0], B[0], 1b0, c0, S[0] );

FA fa1( A[1], B[1], c0, c1, S[1] );

FA fa2( A[2], B[2], c1, c2, S[2] );

FA fa3( A[3], B[3], c2, cout, S[3] );

endmodule


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A Verilog module includes a module

name an a por s

module adder( A, B, cout, sum );

input [3:0]A;input [3:0] B;

out ut cout

4 4

adderoutput [3:0] sum;

// HDL modeling of

sumcout

a er unc ona y

endmodule

4

Note thesemicolon at thePorts must have

a direction orbe bidirectional)

and a bitwidth


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A Verilog module includes a module

Traditional Verilog-1995 Syntax

name an a por s

module adder( A, B, cout, sum );

input [3:0]A;

input [3:0] B;

4 4

output cout;

output [3:0] sum;adder

ANSI C Style Verilog-2001 Syntax

module adder( input [3:0]A,

input [3:0] B,sumcout

4

output cout,output [3:0] sum );


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A module can instantiate other modules

crea ng a mo u e erarc y

module FA( input a, b, cin

output cout, sum );ba cin

// HDL modeling of 1 bit

// adder functionalityFAcout

c


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A B

adder FA FA FA FA

module adder( input [3:0]A, B,output cout,

output [3:0] S );

wire c0, c1, c2;

a ... ;

FA fa1( ... );FA fa2( ... );

FA fa3( ... );

endmodule


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A B

adder FA FA FA FA

module adder( input [3:0]A, B,output cout,

output [3:0] S );

wire c0, c1, c2;

a , , , c , ;

FA fa1( A[1], B[1], c0, c1, S[1] );FA fa2( A[2], B[2], c1, c2, S[2] );

FA fa3( A[3], B[3], c2, cout, S[3] );

endmodule Carry Chain


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Verilog supports connecting ports by

pos on an y name

Connectin orts b ordered list

FA fa0( A[0], B[0], 1b0, c0, S[0] );

Connectin orts b name com act

FA fa0( .a(A[0]), .b(B[0]),

.cin(1b0), .cout(c0), .sum(S[0]) );

Connecting ports by name

FA fa0

For all but the smallest

.a (A[0]),

.b (B[0]),

.cin (1b0),

modules, connecting portsby name yields clearer and

.cou c ,

.sum (S[0])

);

.


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Lets review how to turn our schematic

agram n o s ruc ura er og

FA FA FA FA


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Lets review how to turn our schematic

agram n o s ruc ura er og

FA FA FA FA

module adder( ... );module adder( input [3:0]A, B,module adder( input [3:0]A, B,module adder( input [3:0]A, B,output cout,

output [3:0] S );

output cout,

output [3:0] S );

output cout,

output [3:0] S );

wire c0, c1, c2;

a ... ;

FA fa1( ... );FA fa2( ... );

FA fa3( ... );

a , , , c , ;

FA fa1( A[1], B[1], c0, c1, S[1] );FA fa2( A[2], B[2], c1, c2, S[2] );

FA fa3( A[3], B[3], c2, cout, S[3] );

endmoduleendmoduleendmoduleendmodule


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Histor of hardware desi n lan ua es

Data types Structural Verilog

Functional Verilog Gate level

High-level behavioralFA FA FA FA

mo u e a er npu : , ,

output cout,

output [3:0] S );

wire c0, c1, c2;

FA fa0( A[0], B[0], 1b0, c0, S[0] );

FA fa1( A[1], B[1], c0, c1, S[1] );

FA fa2( A[2], B[2], c1, c2, S[2] );

FA fa3( A[3], B[3], c2, cout, S[3] );

endmodule

G


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Gate-level Verilog uses structural

modulemux4( input a, b, c, d, input [1:0] sel, output out );

er og o connec pr m ve ga es

wire [1:0] sel_b;

not not0( sel_b[0], sel[0] );not not1( sel_b[1], sel[1] );

sel[0]sel[1]cadb

, , ,

and and0( n0, c, sel[1] );

and and1( n1, a, sel_b[1] );

and and2( n2, d, sel[1] );

, , _

wire x0, x1;

nor nor0( x0, n0, n1 );

nor nor1( x1, n2, n3 );

wire y0, y1;or or0( y0, x0, sel[0] );

or or1( y1, x1, sel_b[0] );

, ,

endmodule out

S i hi h k


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So is this how we make

a c es an p- ops

(

input clk,

input d,

(

input clk,

input d,

output reg q

);

output q

);

begin

if ( clk )

d = q;

begin

d = q;

end

end

endmoduleendmodule Edge-triggered

always block

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Verilog _combinational Circuit