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A Digital Circuit Toolbox

A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

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Page 1: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

A Digital Circuit Toolbox

Page 2: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Verilog Hierarchy

• Each design identifier creates a new branch of the hierarchy tree

Page 3: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Tristate Signals and Busses

• Tristate busses are allowed by most FPGA architectures on devices output pins

• If tristate are not allowed,the synthesis may have

control to automatically substitutes with MUXes

Page 4: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Schematics for Internal Tristate Buffer Design

Page 5: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

MUX version of Tristate Buffer Design

Page 6: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Bidirectional Busses

• The signals is divided into two parts:

the driver part

input part• The two parts are then

wired together

Page 7: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Bidirectional Busses

Page 8: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

If/else Priority Encoder

• Implied priority with precedence assigned to the first instruction encountered in a begin/end block

Page 9: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

If/else Priority Encoder

Page 10: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Case Priority Encoder

• The cases aremutually exclusive and do not overlap

Page 11: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree
Page 12: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

State Machines

• Use a set of registers,

to determine current machine state

• Moore style : the output depends only on the state

• Mealy style: the output depends on the state and some input signals

Page 13: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

State Machines

Page 14: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

State Machines

Page 15: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Converting Binary to Gray Code

Page 16: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Converting Gray Code to Binary

Page 17: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

State Assignment

• Make a big difference in how efficiently your logic will be synthesize

• use parameters, ‘define and ‘ifdef

to select between encoding assignments

Page 18: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

State Assignment

• One-hot state assignment means that each state is assigned a single state flip-flop which is active only in the assigned state

• One-could state assignment means that a flip-flop is inactive only in the assigned state

Page 19: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

AddersHalf-Adder

• The synthesis tool will examine each instance of the + operator and will try to implement the logic with a preoptimized module

Page 20: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Half-Adder

Page 21: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Full Adder

• To turn the half adder into a full adder, we take the output of a half adder and connect it into another half adder

Page 22: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Full Adder

Page 23: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Full Adder

Page 24: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Full Adder

Page 25: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Subtractor

• Similar to the adder

Page 26: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Full-Subtractor

Page 27: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Hard-Wired Multipliers

• Multiply value by a constant

• The multiplication process shifts and adds

Page 28: A Digital Circuit Toolbox. Verilog Hierarchy Each design identifier creates a new branch of the hierarchy tree

Generic Multipliers

• We must create logic which allows all the shift and adds to be used


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