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This file of mine projects the verilog code of various combinational circuits and also their test benches for "MODEL SIM". I hope you will find it informative. Do comment if you have any doubt. Thanks
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Exp.No.1 Design and Implementation of Combinational Circuits
Aim:
To design and implement the following combinational circuit using data flow or gate level
modelling along with their test bench.
a. Basic Gates
b. Half-Adder and Full-Adder
c. Half-Subtractor and Full-Subtractor
d. 2:4 Decoder
e. 8:3 Encoder
f. Parity Checker
g. 8:1 Multiplexer
h. 1:4 De-multiplexer
i. Binary to gray converter
j. Gray to binary convertor
k. 2 bit magnitude comparator
Software Details: For design Fuctional Simulation Result: ModelSim
For design Synthesis: Quartus II
For design Implementation: Quartus II
a. Basic Gates :-
module basicgate(a,b,c);
input a;
input b;
output [6:0]c;
and(c[0],a,b);
or(c[1],a,b);
not(c[2],a);
nand(c[3],a,b);
nor(c[4],a,b);
xor(c[5],a,b);
xnor(c[6],a,b);
endmodule
Test Bench :
module gate_tst();
reg a;
reg b;
wire [6:0]c;
basicgate x1(.a(a),.b(b),.c(c));
initial
begin
a=1'b0;
b=1'b0;
#200;
a=1'b0;
b=1'b1;
#200;
a=1'b1;
b=1'b0;
#200;
a=1'b1;
b=1'b1;
end
endmodule
Functional Simulation Result of logic gates:
b. Half-Adder and Full-Adder :-
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
wire sum,carry;
xor(sum,a,b);
and(carry,a,b);
endmodule
module full_adder(a,b,cin,sum,carryout);
input a,b,cin;
output sum,carryout;
wire w1,w2,w3;
half_adder a1(.a(a), .b(b), .sum(w1), .carry(w2));
half_adder a2(.a(w1), .b(cin), .sum(sum), .carry(w3));
or(carryout,w2,w3);
endmodule
Test Bench :-
module adder_tst();
wire sum,carryout;
reg a,b,cin;
full_adder a1(.a(a),.b(b),.cin(cin),.sum(sum),.carryout(carryout));
initial
begin
a=1'b0;
b=1'b0;
cin=1'b0;
#200;
a=1'b0;
b=1'b0;
cin=1'b1;
#200;
a=1'b0;
b=1'b1;
cin=1'b0;
#200;
a=1'b0;
b=1'b1;
cin=1'b1;
#200;
a=1'b1;
b=1'b0;
cin=1'b0;
#200;
a=1'b1;
b=1'b0;
cin=1'b1;
#200;
a=1'b1;
b=1'b1;
cin=1'b0;
#200;
a=1'b1;
b=1'b1;
cin=1'b1;
end
endmodule
Functional Simulation Result of Adder:
c. Half-Subtractor and Full-Subtractor :-
module half_subtractor(a,b,diff,borrow);
output diff,borrow;
input a,b;
assign diff=a^b;
assign borrow=(~a)&b;
endmodule
module full_subtractor(a,b,c,diff,borrow);
output diff,borrow;
input a,b,c;
assign diff=a^b^c;
assign borrow= ((~a)&b)|(b&c)|(c&(~a));
endmodule
Test Bench:
module subtractor_tst();
wire diff,borrow;
reg a,b,c;
full_subtractor a1(.a(a),.b(b),.c(c),.diff(diff),.borrow(borrow));
initial
begin
a=1'b0;
b=1'b0;
c=1'b0;
#200;
a=1'b0;
b=1'b0;
c=1'b1;
#200;
a=1'b0;
b=1'b1;
c=1'b0;
#200;
a=1'b0;
b=1'b1;
c=1'b1;
#200;
a=1'b1;
b=1'b0;
c=1'b0;
#200;
a=1'b1;
b=1'b0;
c=1'b1;
#200;
a=1'b1;
b=1'b1;
c=1'b0;
#200;
a=1'b1;
b=1'b1;
c=1'b1;
end
endmodule
Functional Simulation Result of Full Subtractor:
d. 2:4 Decoder :-
module two_four_decoder(a,b,w,x,y,z);
output w,x,y,z;
input a,b;
assign w=(~a)&(~b);
assign x=(~a)&b;
assign y=a&(~b);
assign z=a&b;
endmodule
Test Bench for 2:4 DECODER:
module two_four_decoder_tst();
wire w,x,y,z;
reg a,b;
two_four_decoder a1(.a(a),.b(b),.w(w),.x(x),.y(y),.z(z));
initial
begin
a=1'b0;
b=1'b0;
#200;
a=1'b0;
b=1'b1;
#200;
a=1'b1;
b=1'b0;
#200;
a=1'b1;
b=1'b1;
end
endmodule
Fuctional Simulation Result of 2:4 Decoder:
e. 8:3 Encoder :-
module eight_three_encoder(a,b,c,d,e,f,g,h,x,y,z);
output x,y,z;
input a,b,c,d,e,f,g,h;
or(x,c,b,d,g);
or(w,f,e,b,a);
or(z,g,e,c,a);
endmodule
Test Bench for 8:3 ENCODER:
module eight_three_encoder_tst();
wire x,y,z;
reg a,b,c,d,e,f,g,h;
eight_three_encoder a1(.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.x(x),.y(y),.z(z));
initial
begin
a=3'b001;
b=3'b000;
c=3'b000;
d=3'b000;
e=3'b000;
f=3'b000;
g=3'b000;
h=3'b000;
#200;
a=3'b000;
b=3'b001;
c=3'b000;
d=3'b000;
e=3'b000;
f=3'b000;
g=3'b000;
h=3'b000;
#200;
a=3'b000;
b=3'b000;
c=3'b001;
d=3'b000;
e=3'b000;
f=3'b000;
g=3'b000;
h=3'b000;
#200;
a=3'b000;
b=3'b000;
c=3'b000;
d=3'b001;
e=3'b000;
f=3'b000;
g=3'b000;
h=3'b000;
#200;
a=3'b000;
b=3'b000;
c=3'b000;
d=3'b000;
e=3'b001;
f=3'b000;
g=3'b000;
h=3'b000;
#200;
a=3'b000;
b=3'b000;
c=3'b000;
d=3'b000;
e=3'b000;
f=3'b001;
g=3'b000;
h=3'b000;
#200;
a=3'b000;
b=3'b000;
c=3'b000;
d=3'b000;
e=3'b000;
f=3'b000;
g=3'b001;
h=3'b000;
#200;
a=3'b000;
b=3'b000;
c=3'b000;
d=3'b000;
e=3'b000;
f=3'b000;
g=3'b000;
h=3'b001;
#200;
a=3'b000;
b=3'b000;
c=3'b000;
d=3'b000;
e=3'b000;
f=3'b000;
g=3'b000;
h=3'b001;
end
endmodule
Fuctional Simulation Result of Encoder:
f. Parity Checker :-
module parity_check (in,even_out,odd_out);
input in;
output even_out,odd_out;
reg temp,even_out,odd_out;
always@(in)
begin
temp <=^(in);
if(temp)
begin
even_out <= 1'b1;
odd_out <= 1'b0;
end
else
begin
even_out <= 1'b0;
odd_out <= 1'b1;
end
end
endmodule
Test Bench for parity checker:
module paritycheck_tst();
reg in;
wire temp,even_out,odd_out;
parity_check a1(.in(in),.even_out(even_out),.odd_out(odd_out));
initial
begin
in=4'b1100;
#200;
in=4'b1011;
#200;
in=4'b1111;
#200;
in=4'b0000;
end
endmodule
RTL Schematic of parity generator:
g. 8:1 Multiplexer :-
module two_one_mux(I0,I1,s0,y);
input I0,I1,s0;
output y;
wire w0,w1,w2;
not(w0,s0);
and(w1,w0,I0);
and(w2,s0,I0);
or(y,w1,w2);
endmodule
module four_one_mux(I0,I1,I2,I3,s0,s1,y);
input I0,I1,I2,I3,s0,s1;
output y;
wire w0,w1,w2,w3,s01,s11;
not(s01,s0);
not(s11,s1);
and(w0,I0,s01,s11);
and(w1,I1,s01,s1);
and(w2,I2,s0,s11);
and(w3,I3,s0,s1);
or(y,w0,w1,w2,w3);
endmodule
module eight_one_mux(I0,I1,I2,I3,I4,I5,I6,I7,s0,s1,s2,y);
input I0,I1,I2,I3,I4,I5,I6,I7,s0,s1,s2;
output y;
wire w1,w2;
four_one_mux a1(.I0(I0),.I1(I1),.I2(I2),.I3(I3),.s0(s0),.s1(s1),.y(w1));
four_one_mux a2(.I0(I4),.I1(I5),.I2(I6),.I3(I7),.s0(s0),.s1(s1),.y(w2));
two_one_mux a3(.I0(w1),.I1(w2),.s0(s2),.y(y));
endmodule
Test bench Code for 8:1 Multiplexer:
module mux_tst();
reg I0,I1,I2,I3,I4,I5,I6,I7,s0,s1,s2;
wire y;
eight_one_mux
a1(.I0(I0),.I1(I1),.I2(I2),.I3(I3),.I4(I4),.I5(I5),.I6(I6),.I7(I7),.s0(s0),.s1(s1),.s2(s2),.
y(y));
initial
begin
I0=3'b000;
I1=3'b001;
I2=3'b010;
I3=3'b011;
I4=3'b100;
I5=3'b101;
I6=3'b110;
I7=3'b111;
s0=1'b0;
s1=1'b0;
s2=1'b0;
#200;
s0=1'b0;
s1=1'b1;
s2=1'b0;
#200;
s0=1'b1;
s1=1'b0;
s2=1'b0;
#200;
s0=1'b1;
s1=1'b1;
s2=1'b0;
#200;
s0=1'b0;
s1=1'b0;
s2=1'b1;
#200;
s0=1'b0;
s1=1'b1;
s2=1'b1;
#200;
s0=1'b1;
s1=1'b0;
s2=1'b1;
#200;
s0=1'b1;
s1=1'b1;
s2=1'b1;
end
endmodule
Fuctional Simulation Result of Multiplexer:
h. 1:4 Demultiplexer :-
module demultiplexer1_4 (din,sel,dout);
output [3:0] dout ;
input din ;
input [1:0] sel ;
assign dout[3] = (sel==2'b00) ? din : 1'b0;
assign dout[2] = (sel==2'b01) ? din : 1'b0;
assign dout[1] = (sel==2'b10) ? din : 1'b0;
assign dout[0] = (sel==2'b11) ? din : 1'b0;
endmodule
Test bench Code for 1:4 Demultiplexer:
module demux_tst();
wire [3:0]dout;
reg D;
reg [1:0]s;
demultiplexer1_4 a1 (.din(D),.sel(s),.dout(dout));
initial
begin
D=4'b0011;
s=2'b00;
#200;
s=2'b01;
#200;
s=2'b10;
#200;
s=2'b11;
end
endmoduleRTL Schematic of De-multiplexer:
i. Binary to gray code converter :-
module binary_gray(w,x,y,z,a,b,c,d);
input w,x,y,z;
output a,b,c,d;
wire w1,w2;
assign a=w;
assign b=w^x;
assign w1=b;
assign c=w1^y;
assign w2=c;
assign d=c^z;
endmodule
Test bench Code for binary to gray code converter:
module binary_gray_tst();
wire a,b,c,d;
reg w,x,y,z;
binary_gray a1(.a(a),.b(b),.c(c),.d(d),.w(w),.x(x),.y(y),.z(z));
initial
begin
w=1'b0;
x=1'b0;
y=1'b0;
z=1'b0;
#200;
w=1'b0;
x=1'b0;
y=1'b0;
z=1'b1;
#200;
w=1'b0;
x=1'b0;
y=1'b1;
z=1'b0;
#200;
w=1'b0;
x=1'b0;
y=1'b1;
z=1'b1;
#200;
w=1'b0;
x=1'b1;
y=1'b0;
z=1'b0;
#200;
w=1'b0;
x=1'b1;
y=1'b0;
z=1'b1;
#200;
w=1'b0;
x=1'b1;
y=1'b1;
z=1'b0;
#200;
w=1'b0;
x=1'b1;
y=1'b1;
z=1'b1;
#200;
w=1'b1;
x=1'b0;
y=1'b0;
z=1'b0;
#200;
w=1'b1;
x=1'b0;
y=1'b0;
z=1'b1;
#200;
w=1'b1;
x=1'b0;
y=1'b1;
z=1'b0;
#200;
w=1'b1;
x=1'b0;
y=1'b1;
z=1'b1;
#200;
w=1'b1;
x=1'b1;
y=1'b0;
z=1'b0;
#200;
w=1'b1;
x=1'b1;
y=1'b0;
z=1'b1;
#200;
w=1'b1;
x=1'b1;
y=1'b1;
z=1'b0;
#200;
w=1'b1;
x=1'b1;
y=1'b1;
z=1'b1;
end
endmodule
RTL Schematic of binary to gray code converter:
j. Gray to binary code converter :-
module gray_to_binary(a,b,c,d,w,x,y,z);
input a,b,c,d;
output w,x,y,z;
wire x,y,z,w;
assign w=a;
assign x=a^b;
assign y=b^c;
assign z=c^d;
endmodule
Test bench Code for gray to binary code converter:
module gray_binary_tst();
reg a,b,c,d;
wire w,x,y,z;
gray_to_binary a1(.a(a),.b(b),.c(c),.d(d),.w(w),.x(x),.y(y),.z(z));
initial
begin
a=1'b0;
b=1'b0;
c=1'b0;
d=1'b0;
#200;
a=1'b0;
b=1'b0;
c=1'b0;
d=1'b1;
#200;
a=1'b0;
b=1'b0;
c=1'b1;
d=1'b0;
#200;
a=1'b0;
b=1'b0;
c=1'b1;
d=1'b1;
#200;
a=1'b0;
b=1'b1;
c=1'b0;
d=1'b0;
#200;
a=1'b0;
b=1'b1;
c=1'b0;
d=1'b1;
#200;
a=1'b0;
b=1'b1;
c=1'b1;
d=1'b0;
#200;
a=1'b0;
b=1'b1;
c=1'b1;
d=1'b1;
#200;
a=1'b1;
b=1'b0;
c=1'b0;
d=1'b0;
#200;
a=1'b1;
b=1'b0;
c=1'b0;
d=1'b1;
#200;
a=1'b1;
b=1'b0;
c=1'b1;
d=1'b0;
#200;
a=1'b1;
b=1'b0;
c=1'b1;
d=1'b1;
#200;
a=1'b1;
b=1'b1;
c=1'b0;
d=1'b0;
#200;
a=1'b1;
b=1'b1;
c=1'b0;
d=1'b1;
#200;
a=1'b1;
b=1'b1;
c=1'b1;
d=1'b0;
#200;
a=1'b1;
b=1'b1;
c=1'b1;
d=1'b1;
end
endmodule
RTL Schematic of gray to binary code converter:
k. 2-bit magnitude comparator :-
module two_bit_magnitude_comparator(a,b,equal,greater,lower);
output equal,greater,lower;
input [1:0]a,b;
wire w0,w1,w2,w3,w4,w5;
wire [1:0]a1,b1;
xnor(w0,a[0],b[0]);
xnor(w1,a[0],b[1]);
not(b1[0],b[0]);
not(b1[1],b[1]);
not(a1[0],a[0]);
not(a1[1],a[1]);
and(w2,a[1],b1[1]);
and(w3,a[0],b1[0],w0);
or(greater,w2,w3);
and(w4,a1[1],b[1]);
and(w5,a1[0],b[0],w0);
or(lower,w4,w5);
and(equal,w0,w1);
endmodule
Test bench Code for gray to 2-bit magnitude comparator:
module magnitude_comparator_tst();
wire equal,greater,lower;
reg [1:0]a,b;
two_bit_magnitude_comparator
a1(.a(a),.b(b),.equal(equal),.greater(greater),.lower(lower));
initial
begin
a=2'b00;
b=2'b00;
#200;
a=2'b10;
b=2'b00;
#200;
a=2'b00;
b=2'b10;
#200;
a=2'b11;
b=2'b11;
end
endmodule
RTL Schematic of gray to 2 bit magnitude comparator:
