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Validation of 30 nm process simulation using 3D TCAD for FinFET devices

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2006 Semicond. Sci. Technol. 21 1111

(http://iopscience.iop.org/0268-1242/21/8/023)

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INSTITUTE OF PHYSICS PUBLISHING SEMICONDUCTOR SCIENCE AND TECHNOLOGY

Semicond. Sci. Technol. 21 (2006) 1111–1120 doi:10.1088/0268-1242/21/8/023

Validation of 30 nm process simulationusing 3D TCAD for FinFET devicesMuhammad Nawaz1, Wolfgang Molzer1, Patrick Haibach1,Erhard Landgraf1, Wolfgang Roesner1, Martin Staedele1,Hannes Luyken1 and Alp Gencer2

1 Infineon Technologies AG, Am Campeon 1-12, D-81726 Munich, Germany2 Synopsys, Inc., Karl-Hammerschmidt-Strasse 34, D-85609 Aschheim/Dornach, Germany

E-mail: muhammad.nawaz@infineon.com

Received 8 March 2006, in final form 4 May 2006Published 10 July 2006Online at stacks.iop.org/SST/21/1111

AbstractThis paper targets to show feasibility of a three-dimensional processsimulation flow in the context of optimization of the device design and theunderlying fabrication processes. The simulation is based on and refers tothe development of the SOI-based 30 nm FinFET devices. The major goalof the simulation work is to implement a complete FinFET process flow intoa commercially available 3D process simulation environment. Furthermore,all important three-dimensional geometrical features, such as cornerroundings and 3D facets, have been introduced into the simulation set-up.After the successful demonstration of a functional 3D process simulationflow, detailed issues of process simulation methodology are assessed, suchas the usage of different dopant diffusion models or the modelling ofspecific oxidation processes plus assessment of different annealingconditions. Finally, a comparison of the simulation results with electricalmeasurement data is performed which shows fairly good agreement.

(Some figures in this article are in colour only in the electronic version)

1. Introduction

As the scaling of the classical CMOS (i.e., bulk siliconand partially depleted/fully depleted silicon on insulator) isapproaching a palpable limit, alternative nonclassical devicestructures having thin, fully depleted (FD) Si bodies are beingexamined. Such devices include the double-gate FinFETs andtriple-gate or multigate field effect transistors (MuGFETs)and allow scaling down to sub-50 nm gate length [1–10].FinFET devices with gate lengths of 18 and 10 nm and gateoxide thicknesses of 2 and 1.7 nm have been experimentallydemonstrated with acceptable short channel characteristics[1, 2]. One of the main advantages of FinFETs is that they offersuperior scalability with manufacturability of conventionalplanar transistors. The self-aligned gates wrapping aroundboth sides of the fin can be fabricated with a single lithographyand etch step. On the other hand, the fabrication process ofFinFETs suffers from some process challenges such as thenon-uniformity of the gate oxide on the etched sidewall of thefin, which is difficult to control. Similarly, the channel–oxide

interface condition is determined by the sidewall roughnessof the fin, and large parasitic resistance between the channeland source/drain is another challenge to the performance ofFinFET devices [4–6].

Most of the results reported so far on FinFETs are basedon experiments or 2D/3D device simulation [7–17]. Forexample, Pei et al [8] have presented a design considerationbased on 3D analytical modelling using the Laplace equation.Short channel effects (SCE) and subthreshold behaviour ofFinFETs were studied with different fin heights, fin thicknessesand channel lengths. Similarly, Xiong and Bokor [11] haveevaluated the sensitivity of threshold voltage variation torandom dopant fluctuation in the Si body, variation in thegate length, fin body thickness and gate dielectric thicknessusing the density gradient method. Recently, Yang et al[7] have analysed scaling behaviour of double- and triple-gate-based FinFET devices with doped and undoped ultrathinSi bodies using 3D numerical simulation. Results of 3Dnumerical simulation reveal that much more stringent bodyscaling for SCE control is needed for undoped bodies relative

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to the doped ones. Due to the relatively small increase in ION

of triple-gate FinFETs, over the double-gate counterparts witha moderate aspect ratio, the advantage of triple-gate FinFETsin gate layout-area efficiency is not significant, and hencetriple-gate FinFETs are not feasible [7]. The 3D numericalsimulations of Park [13] and Burenkov [14, 16] have pointedout that the triple-gate FinFETs’ design is beneficial since ION

is enhanced (i.e., positive influence of the corner effect) and theleakage current is suppressed. More recently, Kranti [17] hassuggested that the electrical isolation of the top gate electroderesults in increased parasitic gate capacitance for double-gateFinFETs, thus resulting in severely degraded intrinsic delayvalues. For 45 nm node and below, the choice of triple-gateFinFETs with a low aspect ratio of the fin as used in thiswork is therefore critical since it provides better designflexibility and minimum intrinsic delay values than double-gate FinFETs.

Since real devices go through many processing steps,reliable evaluation or design optimization of final devicesdepends on the optimized unit process development. TCADor technology CAD process simulation is therefore aprerequisite for device optimization or device design throughdevice simulation. Due to the inherent link betweenprocess simulation and device simulation enabling the fulloptimization loop from unit process to device characteristics,one can correlate the electrical behaviour of the device withsmall changes in the unit processes (e.g., time, temperature,doses and energies). Since the process simulation enablesvirtual processing and in this way explores the parameterspace of processing options, a necessary prerequisite isthat the processes to be modelled have been adequatelyimplemented in the modelling software and that the requiredparameters have been calibrated. With process developmentdriven by new materials and new processing techniques,process simulation lags in general behind these technicaldevelopments. Therefore, the process modelling toolshave to be tweaked in many cases and results have tobe validated carefully versus state-of-the-art physical andelectrical characterizations.

Because of the three-dimensional geometry of FinFETsand the complex channel profile required to adjust thethreshold voltage beyond 50 nm gate length, conventional 1Dor 2D TCAD simulations (i.e., process and device simulation)are not directly applicable and hence not suited well fromthe point of view of accuracy and predictability. Accurateprediction of device performance and structure optimizationtherefore depends on the availability of reliable and accurateprocess models in three dimensions. Most importantly, thedoping profile is required at various stages during the devicefabrication. Particularly, for reliable 3D process simulationfor FinFETs, state-of-the-art diffusion, ion implantation andactivation models are needed for critical process steps. Suchmodels are not widely available for 3D process simulation.Although 3D process simulation is computationally intensive,and requires high memory/speed for dense mesh/gridding,it not only gives good insight into the device physics butalso provides timely and cost-effective optimization of unitprocesses. Because of the 3D nature in vertical FinFETs,direct characterization of the doping profile is extremelydifficult, if not impossible. Validation of process simulation is

therefore only possible through electrical characterization ofreal devices.

This work focuses on the implementation of a completeFinFET process flow into a commercially available 3D processand device simulation environment. Similar to real devices,all important three-dimensional geometrical features, such ascorner roundings and 3D facets, have been introduced intothe simulation set-up. After the successful demonstrationof a functional 3D process simulation flow, detailed issuesof process simulation methodology are assessed, such as theusage of different dopant diffusion models or the modellingof specific oxidation processes and different annealingconditions. The simulation results are finally compared withthe experimental data.

2. FinFET structure and process flow

The TAURUS process and device simulator from Synopsys[18] has been used in this work because of its 3D process anddevice capability and the compatibility with the mainstream2D TCAD framework TSUPREM4/MEDICI (also fromSynopsys) which has been well calibrated with all advancedCMOS logic technologies. The critical process steps forInfineon FinFETs on standard SOI are channel implant, finformation (20–30 nm), gate oxide growth (2–3 nm), gateformation or patterning, spacer formation (25 nm), Si epitaxygrowth in the source–drain region and source–drain implantbefore final junction anneal. All necessary thermal stepshave been included in the process simulation. No haloimplants were used for setting threshold voltage, nor werethere any angled implants used anywhere in the processflow. This is in contrast to other double gate structures[6] while similar to triple-gate FinFETs [19]. The well-known equilibrium diffusion model (PD Fermi, equilibriumpoint defect concentrations) and the dual Pearson implantationmodel were used in the process simulation using default modelparameters. Table 1 lists the complete process flow used inour simulations. The total number of mesh points for halfof the device was approximately 120 000. Only quarter ofthe device was used in the process simulation flow, and theprocessing time was 7–8 h using 3D TCAD. The devicewas then reflected at the end of the process flow to gethalf of the device for device simulation. The grid accuracyat the Si/SiO2 interface was 0.1 nm and in the Si channelregion was 1.5 nm. Since the gate oxide growth using a3D TAURUS process simulator is unstable for thin layers,the first part of the process simulation (i.e., fin definition,sacrificial oxide growth and gate oxide growth) was carriedout using the 2D Tsuprem4 process simulator [18]. The finalresults of the gate oxide growth process along with the fin wereextruded into the 3D TAURUS process flow. A 2D view of apatterned fin along with the boron channel profile is shown infigure 1. Figure 2 shows the complete process-simulateddevice, along with its internal view indicating 30 nm gatearound the fin. Figure 3 shows the TEM cross-section of areal Infineon FinFET perpendicular and parallel to the source–drain direction.

Device simulations have been performed using the driftdiffusion model taking into account the quantum confinementeffects (modified local density approximation: MLDA model)

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Table 1. Simulated process flow for FinFET devices.

SOI material: 45 nm Si on 100 nm BOX60 nm TEOS hardmaskPatterning of fin, dry etchedImplantation of channel doping (B, energy = 20 keV, dose = 4.5 × 1013 cm−2, rot = 0, tilt = 0)Sacrificial oxidation, 8 nm, 1100 ◦C (optional)Gate oxide: 2 nm or 3 nmGate-poly-Si (phosphorus doped at 4 × 1020 cm−3, 100 nm)65 nm TEOS hardmaskPatterning of gateNitride-spacer, 25 nmSelective Si-epitaxy for S/D regions, 60 nmS/D-implantation (As, energy = 50 keV, dose = 3.0 × 1015 cm−2, rot = 0, tilt = 0)Anneal 1000 ◦C, 10 sFinal anneal 950 ◦C, 10 s (ZOX, SiO2/BPSG process step)

Figure 1. A 2D view of a patterned fin along with the boron profile directly after channel implant.

Figure 2. A complete FinFET device (left) and internal view with30 nm gate around the fin (right).

[20], bandgap narrowing effects, low field (doping andtemperature dependence) and high field mobility models (i.e.Caughey Thomas model) [21] including the Lombardi surfacescattering mobility model [22]. Because of the ultra-shortchannel (20–40 nm) of FinFETs, quasi-ballistic effects were

Figure 3. TEM cross-section of a real FinFET perpendicular (left)and parallel (right) to the source–drain direction.

included in the device simulation using a gate length dependentvelocity saturation model, valid in the high-field region of the

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Figure 4. Boron channel profile for the basic fin with gate oxide around (a) and complete structure with the net doping profile(b) generated from two models.

device operation. This modified drift diffusion approach hasearlier been validated for ultra-short channel lengths downto 10 nm for planar MOSFETs [23, 24]. A more accuratesemiconductor transport simulation such as Monte Carlo wasintentionally avoided because of time consumption, whilehydro-dynamic transport simulation [23] fairly overestimatesthe drain current for a sub-50 nm channel length—an aspectwhich is well known to many readers [23, 25]. Other physicaleffects such as SRH recombination and Auger recombinationwere also included in the device simulation. Since the gatewas heavily P-doped (table 1), and the polysilicon was treatedas a semiconductor, so the gate depletion effects were includedin the device simulation. The threshold voltage was definedat a drain current of 1.0 × 10−7 A, while IOFF was defined at

VGS = −0.3 V and VDS = 1.2 V. Similarly, ION was defined atVGS = 0.9 V, VDS = 1.2 V. Since our devices are normally on(i.e., VGS = 0 V), IOFF was therefore taken at VGS = −0.3 V.

3. Results and discussion

Although all our nominal simulations deal with using a simpleequilibrium Fermi level dependent diffusion model (wherethe interstitial and vacancy concentrations are only Fermilevel dependent), we separately evaluated the more advancedbut time-consuming point defect mediated diffusion model(i.e., non-equilibrium diffusion of interstitials and vacancies).In TAURUS, the Fermi level dependent model is called

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Figure 5. Transfer characteristics of 30 nm FinFETs using thePD.Fermi and PD.Full models.

‘PD.Fermi’, while the point defect dependent diffusion modelis called ‘PD.Full’. Figure 4 illustrates the two basic fin cross-sections with gate oxide around (a) and a complete structurealong with a net doping profile (b) generated with the twomodels. Note that the boron concentration is lower in theSi region with the PD.Full model than with the PD.Fermimodel, while the diffused amount of boron is larger in the gateoxide region with the PD.Full model than with the PD.Fermimodel. Since the diffusivity of boron in the PD.Full model ishigher (due to transient-enhanced diffusion), a large amount ofboron is exposed to the segregation effects from the Si regiontowards the oxide. The maximum amount of boron was 1.2 ×1018 cm−3 in the Si fin region (central area) with the PD.Fermimodel, while 3 × 1017 cm−3 was obtained with the PD.Fullmodel. The electrical characteristics of the FinFETs with thePD.Fermi and the PD.Full models are shown in figure 5 fordifferent drain–source biases. Note the shift in the thresholdvoltage (Vth decreases) of 99 and 102 mV at a drain biasof 0.05 and 1.2 V, respectively, obtained with the PD.Fullmodel. A DIBL (drain-induced barrier lowering) of 82 and86 mV V−1 was obtained with the PD.Fermi and the PD.Fullmodel, respectively. A subthreshold voltage swing of82 mV dec−1 has been obtained for both models. Although thePD.Full model gives excellent insight into the device physicswith accurate predictability, the slow process simulations(32–36 h: complete process simulation for half device)with the PD.Full model are not well suited for an industrialenvironment where many splits and process parameters needto be optimized. We therefore limited our simulations to thesimpler but reasonably good PD.Fermi model.

Similar to real devices, the influence of sacrificialoxidation on the FinFET process and electrical results hasbeen investigated. To remove the Si surface damage causedduring the plasma dry etching of the fin stack, a thin sacrificialoxidation layer is usually required after the fin patterning andbefore the gate oxide growth. This oxidation is removed priorto the gate oxidation so that the clean Si surface with betterinterface quality becomes available for the gate oxide growth.This step further reduces the fin thickness (initial fin thicknesswas 30 nm, after sacrificial oxide fin thickness was 22 nm)and makes the corners more rounded. The main motivation in

this process step was to assess whether the process simulationaccurately reproduces the fin geometry like real devices withsacrificial oxide growth. As discussed earlier, due to theinstability of the thin layer of the gate oxide growth in 3DTCAD, we therefore simulated the first few process steps (finformation, sacrificial oxide growth and etching, and final gateoxide growth) with 2D process simulation using TSUPREM4.Similar to the real Infineon FinFET process [3], the simulatedprocess shows more rounded corners after sacrificial oxidationas well. This effect is shown in figure 6 where a 2D view ofa Si fin along with the boron profile and a 3D view of acomplete FinFET device with and without sacrificial oxide aredemonstrated.

Transfer characteristics of a FinFET device with andwithout the sacrificial oxidation step in the process flow areshown in figure 7. Note that the boron concentration is fairlyhigh (3 × 1018 without sacrificial oxide versus 1.2 × 1018 cm−3

with sacrificial oxide) in the Si fin body without sacrificialoxidation. As expected, an extra body doping in the Si finregion increases the threshold voltage of the device. Theadditional thermal budget during the sacrificial oxidation ofthe devices leads to more diffusion of the boron out of theSi fin body into the oxide. This corresponds to a shift in thethreshold voltage of the device. A shift (Vth increases withoutsacrificial oxidation) in the threshold voltage of 224 mV wasobtained in reasonable agreement with processed devices (i.e.,roughly 200 mV) [3]. From the geometrical shape of thefin (corner rounding), along with the doping profile from theprocess simulation and finally the electrical characteristics,we see that the 3D process simulation accurately reflects thebehaviour of the real devices.

The source/drain resistance can be a significantcomponent of parasitic series resistance. Two commonmethods of reducing this component of series resistance areraised S/D and self-aligned silicided S/D. Raised S/D (RSD)through selective Ge [4], and SiGe growth [1] and CoSi2 onS/D [6] has earlier been implemented in FinFETs. SelectiveSi epitaxy was used in the process flow to increase the finthickness in the regions outside the spacer. These thickenedsource/drain regions help to decrease the overall parasiticresistance by providing more silicon for the source–drainsilicide formation. The raised source–drain (RSD) epitaxyprocess step in our real FinFETs follows a sequence of standardcleaning, an HF-dip and an H2 prebake at 900 ◦C beforeepitaxially growth of 60 nm undoped silicon in a selectivereduced pressure CVD-process at 840 ◦C. This results infacets at the border of the silicon area, whereby the heightof the additional silicon is much reduced in the narrow regionsnear the fin. The motivation in this part was to see whetherthe raised source–drain area with Si epitaxy, along with thechanged doping profile (i.e., alternatively any influence on thechannel length), has any effect on the electrical characteristicsof the devices or not. Figure 8 illustrates a 3D view of the twostructures with and without Si epitaxy. Note that the boronand arsenic concentrations in the interior region of the finbody remain approximately unaffected (figure 8 (left view)).The simulated electrical transfer characteristics of the FinFETsare shown in figure 9(a) at drain biases of 0.05 and 1.2 V. Avery little change in the drain–source current was noticed withand without Si epitaxy devices (the two curves overlap each

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Figure 6. 2D (a) and 3D (b) views of a 30 nm FinFET device with and without sacrificial oxidation.

other on the log scale). This finding (i.e., negligible effecton the drain–source characteristics) is also supported by theresults from 3D device simulation from Fraunhofer Instituteof Integrated System and Device Technology at Erlangen onsimilar structures. The series resistance effect is fairly small,which is explained by our simple analysis as follows.

One divides the total resistance of a structure (figure 9(b))into two sections as

Rtotal = Rext + Rfin. (1)

We split this into two equations (with raised source–drain andwithout raised source-drain epitaxy); then

Rtotal wrsd = Rext wrsd + Rfin (2)

and

Rtotal worsd = Rext worsd + Rfin. (3)

Taking typical values in our test structures, we get

Rext wrsd ≈ 560 �. (4)

This value is extracted from direct measurement of ourresistance structures. Similarly, we have for the other case(i.e., without RSD)

Rext worsd ≈ (t1/t2) × 560 ≈ 746 � (5)

where t1 = 60 nm (with RSD) and t2 = 45 nm (without RSD)are the thicknesses of Si in the raised source–drain areas.

We finally get

|Rext wrsd − Rext worsd| ≈ 186 �. (6)

This difference (equation (6)) is much less than the totaltransistor resistance (i.e., Rtotal = 19 k� taken at VDS = 1.2 V

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Figure 7. Transfer characteristics of 30 nm FinFETs with andwithout sacrificial oxidation in the process flow.

and ION of 63 µA: the values are taken from figure 10(b) fora nominal 30 nm gate). This difference is mostly due to thegeometrical shape (butterfly shaped layout) of the external part,with a pronouncedly increasing cross-section. It is thereforeobvious that due to very small change in series resistance, oneshould get very small influence in ION. This is in contrastto the experimental finding [6] where a noticeable differencein ION (IOFF remains unaffected) was found with and withoutSi epitaxy growth in source–drain areas (RSD). Note that thelayout of the structure [6] is quite different and Rext wrsd isquite large (i.e., 1.5 k�/square); see figures 7 and 4 in [6]. Wemainly focused on the 3D facet and any resulting influenceon the doping profile with raised source–drain Si epitaxy.Furthermore, the CoSi2 silicide process in the gate and source–drain areas has not been implemented in our process flow.

Finally, we investigated the junction-annealing step (i.e.,RTA) for FinFETs with different gate lengths. An optimum

Figure 8. 3D view of a FinFET with Si epitaxy growth in the source–drain regions.

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Figure 9. Transfer characteristics of FinFETs (a) with and withoutSi epitaxy growth in the process flow and simple transistor structure(b) for resistance evaluation.

anneal temperature and time (thermal budget) is generallyneeded for dopant activation in order to get improved parasiticresistance and short channel effects. From a device fabricationpoint of view, the control of overlap between the extensionsand gates is a critical issue, since adequate overlap is necessaryto prevent current crowding and obtain sufficient drain current.On the other hand, excess overlap length gives rise to increasein overlap capacitance, gate leakage current due to directtunnelling in the off state and GIDL (gate-induced drainleakage) current. Figure 10 illustrates the influence ofannealing temperature on the device performance. The net

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Figure 10. Short channel effects (a) and ION–IOFF behaviour ((b) and(c)) as a function of anneal temperature for different gate lengths.

doping profile along the lateral direction (source–drain) isshown in figure 11. Source–drain anneal was performed fora period of 10 s. ION and IOFF currents increase with theincrease in temperature. Similarly, short channel effects (i.e.,DIBL and S) are enhanced at higher anneal temperature. Themost important reason for increased short channel effects is theoverlap for the whole fin. With lower temperature budget, partsof the vertical channel are in underlap and hardly contributeto the current. Thus, with increasing anneal temperature, ION

increases accordingly. IOFF increases because of increasedshort channel effects. These changes are more pronouncedat smaller gate lengths. For a given gate length, increasingthe anneal temperature leads to more lateral diffusion ofdopants and hence increases the overlap region under thegate. Thus, the effective channel length reduces at highertemperature. As a result, the threshold voltage decreases andincreases the DIBL and subthreshold voltage swing S. Withthe variation of anneal temperatures from 960 to 1040 ◦C, theincrease in the transconductance was approximately 21 and16% at a drain bias of 1.2 V for 18 and 40 nm gate length,

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Figure 11. Net doping profile along the lateral direction(source–drain) at z = 5 nm (vertical Si/SiO2 interface sidewalls ofthe fin) and y = 2 nm (top gate oxide surface) from the gate surface.Current flow is along the x-direction (lateral), z is along the widthside of the fin and y is the vertical coordinate. The gate length was30 nm.

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Figure 12. Comparison of simulation with experimental data ofFinFETs in terms of ION and IOFF currents from different wafers withdifferent fin thicknesses (i.e., 20 and 30 nm).

respectively. Although we have better ION—IOFF behaviour athigh temperatures (figure 10(c)), the nominal device tends toget too small as seen by the short channel effects (figure 10(a)).On the basis of our simulation findings and support fromthe real FinFET process flow [3], an anneal temperature of1000 ◦C is therefore a reasonable choice.

The simulated process flow of FinFETs is finally validatedby comparing with the experimental data. Random devices

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Validation of 30 nm process simulation using 3D TCAD for FinFET devices

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Figure 13. Transfer characteristics of simulation and experimentaldata at a drain bias of 1.2 V for different fin thicknesses (i.e., 20 and30 nm). The experimental gate length was 40 nm and gate widthwas 120 nm.

were picked from the wafer with fin thicknesses from 15 to30 nm and gate lengths ranging from 20 to 1000 nm and gateoxide thicknesses of 2 and 3 nm. Figure 12 demonstrates thecomparison with the experimental data in terms of the IOFF

versus ION current. IOFF was defined at VGS = −0.3 V, andVDS = 1.2 V, while ION was defined at VGS = 0.9 V and VDS

= 1.2 V. At constant fin thickness, the gate length was variedto get the ION versus IOFF behaviour. Figure 12(a) shows thedata with 3 nm gate oxide and figure 12(b) deals with thedata from a different wafer with 2 nm gate oxide. Note thatthe comparison was made with the exact process flow of ourreal FinFETs [3] using default modelling parameters. BothION and IOFF increase with the increase in fin thickness. Withincreasing fin thickness, IOFF increases because of increasedshort channel effects, while ION increases due to decreasedextension resistance and threshold voltage. For example, at agiven gate length of 20 nm and increasing fin thickness from20 to 30 nm, the threshold voltage decreases from −0.252to −0.327 V and subthreshold swing S increases from 74to 94 mV dec−1. Although the data become more scatteredwith reducing gate lengths and fin thicknesses, a reasonableagreement was obtained with the experimental data. Thetransfer characteristics are presented in figure 13 indicating areasonable agreement with the experimental points and hencevalidating our simulation results.

4. Conclusion

The simulated process flow of Infineon FinFETs is qualified interms of comparing with electrical data of processed devices.Different diffusion models have been evaluated. Comparedto the PD.Fermi model, a shift in the threshold voltage of102 mV was obtained with the PD.Full model. Similar toreal devices, the process simulation accurately reproduces thefin shape after the sacrificial gate oxide process and furthersupported by the shift in the threshold voltage of devices withand without sacrificial oxide growth. Selective Si epitaxyin the source–drain region (raised source–drain area) wasevaluated in the process flow and little/no difference wasfound in terms of the drain–source current for devices with and

without Si epitaxy growth in the source–drain areas. Finally,the simulated devices show good agreement with the measureddata of devices picked randomly from different wafers.

Acknowledgment

This work has been partly supported by the EuropeanCommission’s Information Society Technologies Program(IST) under contract number IST-507585 (NANOCMOS).

References

[1] Huang X et al 2001 Sub-50 nm P-channel FinFET IEEETrans. Electron Devices 48 880–6

[2] Yu B et al 2002 FinFET scaling to 10 nm gate length Tech.Dig. IEDM pp 251–4

[3] Landgraf E et al 2005 FinFET devices: gate length down to18 nm Deliverable Document no. del 3208 ec p6 CMOSbackbone for 2010 European Commission, Nano CMOSproject from 45 nm node down to the limits, InformationSociety Technologies (IST)

[4] Lindert N et al 2001 Quasi-planar FinFETs with selectivelygrown germanium raised source/drain IEEE Int. SOI Conf.pp 111–2

[5] Kedzierski J et al 2002 Metal-gate FinFET and fully-depletedSOI devices using total gate silicidation IEDM Dig.pp 247–50

[6] Kedzierski J, Ieong M, Nowak E, Kanarsky T S, Zhang Y,Roy R, Fried D and Wong H S P 2003 Extension andsource/drain design for high performance FinFET devicesIEEE Trans. Electron Devices 50 952–8

[7] Yang J W and Fossum J G 2005 On the feasibility of nanoscaletriple-gate CMOS transistors IEEE Trans. ElectronDevices 52 1159–64

[8] Pei G, Kedzierski J, Oldiges P, Ieong M and Kan E C C 2002FinFET design considerations based on 3-D simulation andanalytical modeling IEEE Trans. Electron Devices49 1411–9

[9] Fossum J G, Yang J W and Trivedi V P 2003 Suppression ofcorner effects in triple gate MOSFETs IEEE ElectronDevice Lett. 24 745–7

[10] Hisamoto D, Lee W C, Kedzierski J, Takeuchi H, Asano K,Kuo C, Anderson R, King T J, Bokor J and Hu C 2000FinFET a self-aligned double gate MOSFET scalable to20 nm IEEE Trans. Electron Devices 47 2320–5

[11] Xiong S and Bokor J 2003 Sensitivity of double-gate andFinFET devices to process variations IEEE Trans. ElectronDevices 50 2255–61

[12] Stadele M et al 2004 A comprehensive study of corner effectsin tri-gate transistors ESSDERC 2004 pp 165–8

[13] Park J T, Colinge J P and Diaz C H 2001 Pi-Gate SOIMOSFET IEEE Electron Device Lett. 22 405–06

[14] Burenkov A and Lorenz J 2003 Corner effect in double andtriple gate FinFETs Proc. ESSDERC 2003 pp 135–8

[15] Granzner R et al 2002 A simulation study onthree-dimensional device design of wire-MOSFETs Proc.European Workshop on Ultimate Integration of Silicon(ULIS) pp 95–8

[16] Burenkov A and Lorenz J 2003 On the role of corner effect inFinFETs Proc. European Workshop on Ultimate Integrationof Silicon (ULIS) pp 31–4

[17] Kranti A and Armstrong G A 2006 Performance assessment ofnanoscale double and triple gate FinFETs Semicond. Sci.Technol. 21 409–21

[18] Taurus-TSUPREM-4TM, Taurus-ProcessTM andTaurus-DeviceTM Simulator, Version. V-2004.09, Synopsys

[19] Doyle B S, Datta S, Doczy M, Hareland S, Jin B, Kavalieros J,Linton T, Murthy A, Rios R and Chau R 2003 High

1119

M Nawaz et al

performance fully depleted tri-gate CMOS transistors IEEEElectron Device Lett. 24 263–5

[20] Paasch G and Ubensee H 1982 A modified local densityapproximation: electron density in inversion layers Phys.Status Solidi b 113 165–78

[21] Caughey D M and Thomas R E 1967 Carrier mobility insilicon empirically related to doping and field Proc. IEEE55 2192–3

[22] Lombardi C, Manzini S, Saporito A and Vanzi M 1988 Aphysically based mobility model for numerical simulationof nonplanar devices IEEE Trans. Comput. AidedDes. 7 1164–70

[23] Bude J D 2000 MOSFET modeling into the ballisticregime IEEE Conf. Proc. SISPAD (Simulation ofSemiconductor Processes and Devices)pp 23–6

[24] Granzner R, Polyakov V M, Schwierz F, Kittler M,Luyken R J, Rosner W and Stadele M 2006 Simulation ofnanoscale MOSFETs using modified drift–diffusion andhydrodynamic models and comparison with Monte Carloresults Microelectron. Eng. 82 241–6

[25] Kawamoto A, Sato S and Omura Y 2004 Engineering S/Ddiffusion for sub-100 nm channel SOI MOSFETs IEEETrans. Electron Devices 51 907–13

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