VA304 C 1 2 17 G N D 18 G N D DIGITAL VARIA LE … · Rev. 0.4 eRex ... ±20MHz offset, PAR 9.81 at 0.01% Prob. , –50dc) ... • 3G/4G Wireless infrastructure and other high performance

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BeRex website: www.berex.com email: [email protected]

Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.

All other trademarks are the property of their respective owners. © 2017 BeRex

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DIGITAL VARIABLE GAIN AMPLIFIER 50-4000 MHz

BVA304

24-lead 4x4 mm QFN

• Small 24-Pin 4 x 4 mm QFN Package

• Intergrate DSA to Amp Functionality

• Wide Power supply range of +2.7 to +5.5V(DSA)

• Single Fixed +3.3V supply(Amp)

• 50-4000MHz Broadband Performance

• 12.3dB Gain at 1.9GHz (No Matching Circuit)

• 3.6dB Noise Figure at 1.9GHz with max gain setting

• 19.3dBm P1dB at 1.9GHz (No Matching Circuit)

• 31.5dBm OIP3 at 1.9GHz(- 3dBm per tone, No Matching Circuit)

• 7.8dBm LTE 20MHz ACLR at 1.9GHz (FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. , –50dBc)

• Attenuation: 0.5 dB steps to 31.5 dB

• Safe attenuation state transitions

• Monotonicity: 0.5 dB up to 4 GHz

• High attenuation accuracy(DSA to Amp)

±(0.15 + 5% x Atten) @ 1.9 GHz

• 1.8V control logic compatible

• Programming modes - Direct Parallel - Latched Parallel - Serial

• Unique power-up state selection

• 3G/4G Wireless infrastructure and other high performance RF application

• Microwave and Satellite Radio

• General purpose Wireless

The BVA304 is a digitally controlled variable gain amplifier (DVGA) is featuring high linearity using the voltage 3.3V supply with a broad-band frequency range of 50 to 4000 MHz. The BVA304 integrates with a high performance digital step attenua-tor and a high linearity broadband gain block. It using the small package(4x4mm QFN package), and operating VDD 3.3V voltage. Also it designed for use in 3G/4G wireless infrastructure and other high performance RF applications. Amplifier used in BVA304 is a high performance InGaP/ GaAs HBT MMIC amplifier, internally matched to 50 Ohms and uses a patented temperature compensation circuit to provide stable current over the operating temperature range without the need for external compo-nents. A serial output port enables cascading with other serial controlled devices. An integrated digital control interface supports both serial and paral-lel programming of the attenuation, including the capability to program an initial attenuation state at power-up. Covering a 31.5 dB attenuation range in 0.5 dB steps. The BVA304 is targeted for use in wireless infrastructure, point-to-point, or can be used for any general purpose wireless application

1GND

C1

6-Bit

Digital Step

Attenuator

2

3

4

5

6

7 8 1110 12

13

14

15

16

17

18

192021222324

9

C0.5

C16

GND

LE

GN

D

GN

D

AM

PIN

RF

1

DA

TA

CL

OC

K

PUP1

PUP2

VDD

GND

GND

VS

S/G

ND

RF

2

P/S

C8

C4

C2

AMPOUT

Gain Block

AMPLIFIER

Figure 1. Functional Block Diagram

Device Features

Figure 2. Package Type Product Description

Application

http://www.berex.com

mailto:[email protected]

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BVA304

1 Device performance _ measured on a BeRex Evaluation board at 25°C, 50 Ω system, VDD=+3.3V, measure on Evaluation Board (DSA to AMP)

2 Gain data has PCB & Connectors insertion loss de-embedded

3 OIP3 _ measured with two tones at an output of –3 dBm per tone separated by 1 MHz.

Parameter Condition Min Typ Max Unit

Operational Frequency Range 50 4000 MHz

Gain2 Attenuation = 0dB, at 1900MHz 11.3 12.3 13.3 dB

Attenuation Control range 0.5dB step 31.5 dB

Attenuation Step 0.5 dB

Attenuation Accuracy

50MHz — 1GHz

Any bit or bit combination

±(0.15 + 3% of atten setting)

dB

>1GHz — 2.2GHz ±(0.15 + 5% of atten setting)

>2.2GHz — 3GHz ±(0.15 + 8% of atten setting)

>3GHz — 4GHz ±(0.15 + 11% of atten setting)

Return loss 1GHz — 2.2GHz

Attenuation = 0dB

11 15

dB (input or output

port) >2.2GHz — 4GHz 12 17

Output Power for 1dB Compression Attenuation = 0dB , at 1900MHz 19.3 dBm

Output Third Order Intercept Point3

Attenuation = 0dB, at 1900MHz

31.5 dBm two tones at an output of –3 dBm per tone separated by 1 MHz.

Noise Figure Attenuation = 0dB, at 1900MHz 3.6 dB

Switching time 50% CTRL to 90% or 10% RF 500 800 ns

Supply voltage DSA 2.7 5.5 V

AMP 3.3 V

Supply Current 21 26 31 mA

Control Interface Serial / parallel mode 6 Bit

Control Voltage Digital input high 1.17 3.6 V

Digital input low -0.3 0.6 V

Impedance 50 Ω

Table 1. Electrical Specifications1



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Table 2. Typical RF Performance1 : 3.3V operating

Parameter Frequency Unit

703 900 4 1900 5 2140 5 2650 5 35005 MHz

Gain8 25.3 17.5 12.3 11.6 10.5 7.2 dB

S11 -13.8 -21.6 -11.8 -11.9 -20 -13.1 dB

S22 -14.9 -15.6 -12.8 -13.4 -14.7 -9.8 dB

OIP32 32.3 29.5 31.5 31.9 33 32 dBm

P1dB 20.4 19.9 19.3 19.3 19.2 18.4 dBm

WCDMA ACLR6 -9.7 2.3 5 6.9 6.2 3.8 dBm

LTE 20M ACLR7 0 3.6 7.8 8.8 8.2 6.3 dBm

N.F 3.5 3.5 3.6 3.6 3.7 4.6 dB 1

Device performance _ measured on a BeRex evaluation board at 25°C, VDD=+3.3V,50 Ω system. measure on Evaluation Board (DSA to AMP) 2 OIP3 _ measured with two tones at an output of –3 dBm per tone separated by 1 MHz. 3 70MHz measured with 50-500MHz application circuit refer to Table12. 4 900MHz measured with 500-1700MHz application circuit refer to Table 14. 5

1900MHz,2140MHz,2650MHz,3500MHz measured with 1700-4000MHz application circuit refer to Table 16. 6

WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob, @ACLR –50dBc 7

LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. @ACLR –50dBc 8 Gain data has PCB & Connectors insertion loss de-embedded

Table 3. Typical RF Performance1 : 4V operating

parameter Frequency Unit

17003 19003 21403 26503 35003 MHz

Gain 13 13.3 12.7 11.3 8.3 dB

S11 -16.3 -15.5 -16.9 -20.0 -18.5 dB

S22 -12.5 -10.6 -12.0 -14.8 -10.5 dB

OIP32 32.5 33.6 33.8 33.4 33 dBm

P1dB 20.6 20.8 20.6 20.6 20.8 dBm

WCDMA ACLR4 7.3 7.9 7.9 7.5 2.7 dBm

LTE 20M ACLR5 9.2 9.8 9.4 5.2 9.6 dBm

Noise Figure 4.4 4.4 4.4 4.8 5.9 dB 1

Device performance _ measured on a BeRex evaluation board at 25°C, VDD=+4V,50 Ω system. measure on Evaluation Board (DSA to AMP) 2 OIP3 _ measured with two tones at an output of –3 dBm per tone separated by 1 MHz. 3

1700MHz,1900MHz,2140MHz,2650MHz,3500MHz measured with 1700-4000MHz application circuit refer to Table 20. 4

WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob, @ACLR –50dBc 5

LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. @ACLR –50dBc



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Table 4. Absolute Maximum Ratings

Operation of this device above any of these parameters may result in permanent damage.

Parameter Condition Min Typ Max Unit

Supply Volatge(VDD) Amp/DSA 5.0/5.5 V

Supply Current Amp 110 mA

Digital input voltage -0.3 3.6 V

Maximum input power Amp/DSA +24/+30 dBm

Operating Temperature Amp/DSA -40 85/105

Storage Temperature -55 150

Junction Temperature 220



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Programming Options

Parallel/Serial Selection

Either a parallel or serial interface can be used to control the BVA303.

The P/S bit provides this selection, with P/S = LOW selecting the paral-

lel interface and P/S = HIGH selecting the serial interface.

Parallel Mode Interface

The parallel interface consists of six CMOS compatible control lines

that select the desired attenuation state, as shown in Table 5.

The parallel interface timing requirements are defined by Figure 4

(Parallel Interface Timing Diagram), Table 8 (Parallel Interface AC

Characteristics), and switching speed (Table 1).

For latched parallel programming the Latch Enable (LE) should be held

LOW while changing attenuation state control values, then pulse LE

HIGH to LOW (per Figure 4) to latch the new attenuation state into

the device.

For direct parallel programming, the Latch Enable (LE) line should be

pulled HIGH. Changing attenuation state control values will change

device state to new attenuation. Direct Mode is ideal for manual

control of the device (using hardwire, switches, or jumpers).

P/S C16 C8 C4 C2 C1 C0.5 Attenuation state

0 0 0 0 0 0 0 Reference Loss

0 0 0 0 0 0 1 0.5 dB

0 0 0 0 0 1 0 1 dB

0 0 0 0 1 0 0 2 dB

0 0 0 1 0 0 0 4 dB

0 0 1 0 0 0 0 8 dB

0 1 0 0 0 0 0 16 dB

0 1 1 1 1 1 1 31.5 dB

Table 5. Truth Table

Serial Interface

The serial interface is a 6-bit serial-in, parallel-out shift register buff-

ered by a transparent latch. It is controlled by three CMOS-

compatible signals: Data, Clock, and Latch Enable (LE). The Data and

Clock inputs allow data to be serially entered into the shift register, a

process that is independent of the state of the LE input.

The LE input controls the latch. When LE is HIGH, the latch is transpar-

ent and the contents of the serial shift register control the attenuator.

When LE is brought LOW, data in the shift register is latched.

The shift register should be loaded while LE is held LOW to prevent

the attenuator value from changing as data is entered. The LE input

should then be toggled HIGH and brought LOW again, latching the

new data. The timing for this operation is defined by Figure 3 (Serial

Interface Timing Diagram) and Table 7 (Serial Interface AC Character-

istics).

Power-up Control Settings

The BVA303 always assumes a specifiable attenuation setting on

power-up. This feature exists for both the Serial and Parallel modes of

operation, and allows a known attenuation state to be established

before an initial serial or parallel control word is provided.

When the attenuator powers up in Serial mode (P/S = 1), the six con-

trol bits are set to whatever data is present on the six parallel data

inputs (C0.5 to C16). This allows any one of the 64 attenuation

settings to be specified as the power-up state.

When the attenuator powers up in Parallel mode (P/S = 0) with LE = 0,

the control bits are automatically set to one of four possible values.

These four values are selected by the two power-up control bits,

PUP1 and PUP2, as shown in Table 6

(Power-Up Truth Table, Parallel Mode).

P/S LE PUP2 PUP1 Attenuation state

0 0 0 0 Reference Loss

0 0 1 0 8 dB

0 0 0 1 16 dB

0 0 1 1 31.5 dB

0 1 X X Defined by C0.5-C16

Table 6. Parallel PUP Truth Table

Note: Not all 64 possible combinations of C0.5-C16 are shown in table Note: Power up with LE = 1 provides normal parallel operation with C0.5-C16, and PUP1 and PUP2

are not active



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1

7 12

18

13

24 19

C1 2

3

4

5

6

C0.5

GND

AMPOUT

GND

C16

8 9 10 11

14

15

16

17

20212223

GND

GND

PUP2

PUP1

LE

VDD

GN

D

AM

PIN

GN

D

RF

1

Da

ta

Clo

ck

C2

C4

C8

RF

2

P/S

VS

S/G

ND

EXPOSED

Grounnd Pad

Note: 1. RF pins 10 and 21 must be at 0V DC. The RF pins do not require DC blocking capacitors for proper Operation if the 0V DC requirement is met 2. Use VssEXT (pin 19) to bypass and disable internal negative voltage generator. Connect VssEXT (pin 19, VssEXT = GND) to enable internal negative voltage generator 3.Place a 10 kΩ resistor in series, as close to pin as possible to avoid frequency resonance 4. This pin has an internal 2 MΩ resistor to internal positive digital supply 5. This pin has an internal 200 kΩ resistor to GND

Figure 3. Serial Interface Timing Diagram

Figure 4. Parallel Interface Timing Diagram

Pin Pin name Description 1,5,7,9,17,18 GND Ground

2 C1 Attenuation control bit, 1dB

3 C0.55 Attenuation control bit, 0.5dB

4 C163,5 Attenuation control bit, 16dB 6 AMPOUT RF Amp out Port

8 AMPIN RF Amp in port 10 RF11 RF port(DSA output)

11 DATA3 Serial interface data input

12 Clock Serial interface clock input 13 LE4 Latch Enable input

14 PUP15 Power-up selection bit 1

15 PUP2 Power-up selection bit 2 16 VDD Supply voltage (nominal 3V)

19 VSS/GND2 External VSS negative voltage control or ground

20 P/S Parallel/Serial mode select

21 RF21 RF port(DSA input)

22 C8 Attenuation control bit, 8dB 23 C4 Attenuation control bit, 4dB 24 C2 Attenuation control bit, 2dB

Table 10. Pin Description

Table 7. Serial Interface AC Characteristics VDD = 3.3V with DSA only, -40°C < TA < 105°C, unless otherwise specified

Symbol Parameter Min Max Unit

fClk Serial data clock frequency 10 MHz

tClkH Serial clock HIGH time 30 ns

tClkL Serial clock LOW time 30 ns

tLESUP LE set-up time after last clock falling edge

10 ns

tLEPW LE minimum pulse width 30 ns

tSDSUP Serial data set-up time before clock rising edge

10 ns

tSDHLD Serial data hold time after clock falling edge

10 ns

Table 9. 6-Bit Attenuator Serial Programming Register Map

B5 B4 B3 B3 B1 B0

C16 C8 C4 C2 C1 C0.5

MSB (first in) LSB (Last in)

Table 8. Parallel Interface AC Characteristics VDD = 3.3V with DSA only, -40°C < TA < 105°C, unless otherwise specified

Symbol Parameter Min Max Unit

tLEPW LE minimum pulse width 10 ns

tPDSUP Data set-up time before rising edge of LE

10 ns

tPDHLD Data hold time after falling edge of LE

10 ns

Figure 5. Pin Configuration(Top View)

Note: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern

are clocked at 10 MHz to verify fclk specification



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Figure 7. Gain vs Frequency @ Major Attenuation Steps

Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and Application Circuit refer to Table12

Figure 6. Gain1 vs Frequency @ Temperature (Max Gain State)

Figure 8. Input Return Loss vs Frequency @ Max Gain & Min Gain State

Figure 9. output Return Loss vs. Frequency @ Max Gain & Min Gain State


50 70 200 MHz

Gain1 25.3 25.3 23.6 dB

S11 -12.4 -13.8 -17.0 dB

S22 -12.6 -14.9 -20.0 dB

OIP32 31.9 32.3 29.2 dBm

P1dB 19.9 20.4 21.0 dBm

Noise Figure 3.5 3.5 3.4 dB

Table 12. 50~500MHz IF Application Circuit

Application Circuit

Values

Freq. IF Circuit

50MHz ~ 500MHz

C1/C3 2.2nF

L3(1005 Chip Ind) 330nH


2 OIP3 _ measured with two tones at an output of -3 dBm per tone separated by 1 MHz.

Table 11. Typical RF Performance(50~500MHz)

Note: 1. Gain data has PCB & Connectors insertion loss de-embedded

U1_AmpC1

L3

C3

C5C4 C6

U1_DSA

Typical RF Performance Plot - BVA304 EVK - PCB (Application Circuit:50~500MHz)



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Figure 11. P1dB vs Frequency @ Temperature (Max Gain State)

Figure 10. OIP3 vs Frequency @ Temperature (Max Gain State)

Figure 12. Noise Figure vs Frequency @ Temperature (Max Gain State)

Figure 13. Attenuation Error vs Frequency @ Major Attenuation Steps

Figure 14. Attenuation Error vs Attenuation Setting @Major Frequency (Max Gain State)

Figure 15. 0.5dB Step Attenuation vs Attenuation Setting @Major Frequency (Max Gain State)





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Figure 16. OIP3 @ 70MHz vs Temperature Figure 17. OIP3 @ 200MHz vs Temperature

Figure 18. Device performance Pin-Pout-Gain @70MHz


Figure 20. ACLR@WCDMA 4FA1, 70MHz, -50dBc Figure 21. ACLR @LTE20MHz1 70MHz, -50dBc

Note: 1 . WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob Note: 1. LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob.





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Figure 22. Gain1 vs Frequency @ Temperature (Max Gain State)




700 800 900 1000 1100 MHz

Gain1 18.9 18.2 17.5 16.8 16.3 dB

S11 -25.5 -24.7 -21.6 -19.1 -17.2 dB

S22 -14.8 -15.2 -15.6 -15.8 -16.1 dB

OIP32 29.2 28.7 29.5 30.7 31.1 dBm

P1dB 20.4 20.1 19.9 19.8 19.7 dBm

Noise Figure 3.6 3.5 3.5 3.5 3.5 dB

Table 14. 500~1700MHz RF Application Circuit

Application Circuit

Values

Freq. RF Circuit A

500MHz ~ 1700MHz

C1/C3 56pF

L3(1005 Chip Ind) 22nH


Note: 1. Gain data has PCB & Connectors insertion loss de-embedded

U1_AmpC1

L3

C3

C5C4 C6

U1_DSA







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Figure 30. Attenuation Error vs Attenuation Setting @Major Frequency (Max Gain State)

Figure 31. 0.5dB Step Attenuation vs Attenuation Setting





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Figure 34. Device performance Pin-Pout-Gain @ 700MHz

Figure 35. Device performance Pin-Pout-Gain @ 900MHz







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3 WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob

4 LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob.

Figure 38. Gain vs Frequency @ Temperature (Max Gain State)




Application Circuit

Values

Freq. RF Circuit B

1700MHz ~ 4000MHz

C1/C3 10pF

L3(1005 Chip Ind) 7.5nH


1700 1900 2140 2650 3500 MHz

Gain1 15 12.3 11.6 10.5 7.2 dB

S11 -20.3 -11.8 -11.9 -20 -13.1 dB

S22 -10.8 -12.8 -13.4 -14.7 -9.8 dB

OIP32 30.4 31.5 31.9 33 32 dBm

P1dB 19.9 19.3 19.3 19.2 18.4 dBm

WCDMA ACLR3 6.4 5 6.9 6.2 3.8 dBm

LTE 20M ACLR4

8.6 7.8 8.8 8.2 6.3 dBm Noise Figure 3.6 3.6 3.6 3.7 4.6 dB


U1_AmpC1

L3

C3

C5C4 C6

U1_DSA





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Figure 46. Attenuation Error vs Attenuation Setting @ Major Frequency (Max Gain State)

Figure 47. 0.5dB Step Attenuation vs AttenuationSetting





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Figure 60. ACLR@WCDMA 4FA1, 2650MHz, -50dBc Figure 61. ACLR @LTE20MHz1, 2650MHz, -50dBc








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1900 2140 MHz

Gain1 11.9 10.6 dB

S11 -16.5 -13.8 dB

S22 -7.6 -7.1 dB

OIP32 33.8 33.7 dBm

P1dB 19.1 19.5 dBm

Noise Figure 3.9 4.4 dB

U1_AmpC1

L3

C3

C5C4 C6

U1_DSAC7

Table 18. 1700~2140MHz High OIP3 Matching Application Circuit

Application Circuit

Values

Freq. RF Matching Circuit C

1700MHz ~ 2140MHz

C1/C3 10pF

C7 1.2pF











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U1_AmpC1

L3

C3

C5C4 C6

U1_DSA


Application Circuit

Values

Freq. RF Circuit D

1700MHz ~ 4000MHz

C1/C3 10pF



1700 1900 2140 2650 3500 MHz

Gain4 13 13.3 12.7 11.3 8.3 dB

S11 -16.3 -15.5 -16.9 -20.0 -18.5 dB

S22 -12.5 -10.6 -12.0 -14.8 -10.5 dB

OIP31 32.5 33.6 33.8 33.4 33 dBm

P1dB 20.6 20.8 20.6 20.6 20.8 dBm WCDMA ACLR2 7.3 7.9 7.9 7.5 2.7 dBm LTE 20M ACLR3 9.2 9.8 9.4 5.2 9.6 dBm

Noise Figure 4.4 4.4 4.4 4.8 5.9 dB





3 WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob .

4 LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob.




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Figure 82. Attenuation Error vs Attenuation Setting @ Major Frequency (Max Gain State)

Figure 83. 0.5dB Step Attenuation vs Attenuation Setting





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Figure 96. ACLR@WCDMA 4FA1, 2650MHz, -50dBc Figure 97. ACLR @LTE20MHz1, 2650MHz, -50dBc








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Evaluation Board PCB Information

Figure 100. Evaluation Board PCB Layer Information

Figure 101. Evaluation Board PCB

COPPER :1oz + 0.5oz (plating), Top Layer

COPPER :1oz (GND), Inner Layer

COPPER :1oz + 0.5oz (plating), Bottom Layer

P.P : (0.2+0.06+0.06) TOTAL = 0.32mm

CORE : 0.73mm FINISH TICKNESS :1.55T

P.P : (0.2+0.06+0.06) TOTAL = 0.32mm

COPPER :1oz, Inner Layer

EM825B ER: 4.6~4.8

MTC Er:4.6

EM825B Er:4.6~4.8



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Figure 102. Evaluation Board Schematic

Table 22. Bill of Material - Evaluation Board

No. Ref Des Part

Qty Part Number REMARK

1 C1,C3 2 CAP 0402 10pF J 50V Another circuit refer to table 21

2 C4,C15 2 CAP 0402 100pF J 50V

3 C5 1 CAP 0402 1000pF J 50V

4 C6 1 TANTAL 3216 10UF 16V

5 C22 1 TANTAL 3216 0.1uF 35V

6 L3 1 IND 1608 7.5nH Another circuit refer to table 21

7 R2,R3 2 RES 1005 J 10K

8 R1,R4,R6 3 RES 1608 J 0ohm

9 CON1 1 15P-MALE-D-sub con-

nector

10 U1 1 QFN4X4_24L_BVA303

11 J1,J3 2 SMA_END_LAUNCH

Application Circuit Values Example

Freq. RF Circuit

1.7GHz~4GHz

RF Circuit

1.7GHz~2.14GHz

IF Circuit

50~500MHz

RF Circuit

500MHz~1.7GHz

C1/C3 10pF 10pF

(C7:1.2pF) 2.2nF 56pF

L3(1005 Chip Ind) 7.5nH 7.5nH 330nH 22nH

Table 21. Application Circuit

Notice: Evaluation Board for Marketing Release was set to 1.7GHz to 4GHz application circuit (Refer to Table 16)



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Figure 103. Application Circuit schematic*

(Use only Serial mode)

* notice. The serial mode PUP state of this Figure 103. is setting in Reference Loss (Refer to Table 6.) and each combinations of C0.5-C16 are shown in

the Table 5. Truth Table.



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BVA304

Figure 104. Package Outline Dimension

Figure 105. Recommend Land Pattern



29

Rev. 0.4

29




Pre

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Dat

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BVA304

BVA304YYWWXX

Figure 106. Tape & Reel

NATO CAGE code:

2 N 9 6 F

Figure 107. Package Marking

Marking information:

BVA304 Device Name

YY Year

WW Work Week

XX LOT Number

Lead plating finish

100% Tin Matte finish

MSL / ESD Rating

ESD Rating:

Value:

Test:

Standard:

MSL Rating:

Standard:

Class 1C

Passes ≤ 2000V

Human Body Model(HBM)

JEDEC Standard JESD22-A114B

Level 1 at +265°C convection reflow

JEDEC Standard J-STD-020 Proper ESD procedures should be followed when handling this device.

C a u t i o n : ESD SensitiveAppropriate precautions in handling, packaging

and testing devices must be observed.

Packaging information: Tape Width 12mm

Reel Size 7”

Device Cavity Pitch 8mm

Devices Per Reel 1K



Documents

VA304 C 1 2 17 G N D 18 G N D DIGITAL VARIA LE … · Rev. 0.4 eRex ... ±20MHz offset, PAR 9.81 at 0.01% Prob. , –50dc) ... • 3G/4G Wireless infrastructure and other high performance