Embed Size (px)
Citation preview
V5 cluster search
USB
RxU
SB T
x
DSPCore
DSPController
Clus
ter F
IFO
ADC Data
PC data
HIP core
State MachineFIFO RD
FIFO WR Register 1..N
Line FIFO
L0,C0 Ctrl
DSP Channel
Cluster list FIFO
SM control
SM control
Data out Cluster list
DATA
L0, C0
DATA
To USB
From USB
Raw/list data sel.
Mask for image processing
Line delay
Line delay
Line delay
Line delay
P-2,-2 P-2,-1 P-2,0 P-2,1 P-2,2
DataIn
P-1,-2 P-1,-1 P-1,0 P-1,1 P-1,2
P0,-2 P0,-1 P0,0 P0,1 P0,2
P1,-2 P1,-1 P1,0 P1,1 P1,2
P2,-2 P2,-1 P2,0 P2,1 P2,2
Complete block diagram
Search Matrix
Matrix DataDataIn Clustering
Channel Control logicL0C0
Pedestal memory Gain Noise
(Optional)
Reconstructed image
+
-x
Bad pixel mask
0
Matrix Data
...
Clustervalidation
Sub pixel (COG)
Th Neig.
32MB @400fps 32MB @400fps 32MB @400fps 2x 64MB @ N fps2MB @400fps
>> nCluster Matrix Size Charge Length Width
Digital pixel
Bad pixel List
Divide by 2^n
SeedLogic
Th Seed
FPGA systemD
DR3
DD
R3
mController
DSP
Ethe
rnet
FPGA
Display jtag
ADCs
Control packge received by the FPGA system
ID (4 bits) Type (2 bits) Size (10 bits)
DATA (0)
DATA (1)
.
.
.
Data (Size -1)
ID refers to the submodule that the package is being sent.TYPE could be write register, read register, write data…Size is this package size, we want small for read/write register but big ones to download data such as the pedestal.
DSPD
DR3
DD
R3
DSPController
DSPCore
Bias
& C
lock
DSP
Display jtag
ADCs
mController block diagram
NiosII SG DMA TSE core DDR3ctrl PIO
1 channel for the whole frame
Maskline0line1line2line3line4
MaskInFIFO
DataIn Seedlogic
DataOut
channel
Control logicL0C0
Two channel system
Maskline0line1line2line3line4
MaskInFIFO
DataIn Seedlogic
DataOut
left channel
Control logicL0C0
Maskline0line1line2line3line4
MaskInFIFO
DataIn Seedlogic
DataOut
right channel
Control logicL0C0
Shared data
Three or more channels
Maskline0line1line2line3line4
MaskInFIFO
DataIn Seedlogic
DataOut
left channel
Control logic
L0C0
Maskline0line1line2line3line4
MaskInFIFODataIn
Seedlogic
DataOut
center channel 1 .. n
Control logic
L0C0
Shared data
Maskline0line1line2line3line4
MaskInFIFO
DataIn Seedlogic
DataOut
right channel
Control logicL0C0
Shared data
