UWB Communications

8/9/2019 UWB Communications

1/4

EEE/OSA/APR nteational Conference on nfoatics, Electronics & Vision

A Low Power, High Data Rate IR-UWB PulseGenerator with BPSK Modulation in 90nm CMOS

Technology for On-Chip Wireless InterconnectsMohammad Nahidul Karim*, SM stiaque Hossain and Pran Kanai Sahl

Departent of Electrical and Electronic EngineeringBangladesh University of Engineering and Tecnology

Dhaka, Bangladesh.

*[email protected]#saap @eee.buet.ac.bd

Abstract CMOSIR UWB

pulse generator for ultra wide-band

on-chip wireless communication using simple triangular pulse

generation technique has been proposed. This architectureenables low power operation for generation of BPSK modulated

ultra short Gaussian monocycle pulses of average duration of

125ps with amplitude of 800mV p-p. The generator's pulse rate is

5 Gbps with an energy eciency of .0455pJ/pulse and a -3dB

Bandwidth of GHz with a center frequency at GHz. The

circuit was implemented and simulated in HSPICE using IBM

90nm RF CMOS technology with a supply voltage of 1.2V. Monte

Carlo and Corner simulations were performed to evaluate the

performance under variation of different parameters.

Keywords Impulse Radio; Utra Wide band; Pulse Genrator;

on-chip wireless interconnect; C;BPSK;

Gaussian Mono

pulse

I.

[NTRODUCTN

Transission of pses of tra-short dration with a large

actional bandwidth is the typical characteristic of pse

radio R) ltra ie-an ) systes. Te calenge in

te circuit iplementation are to acieve large bandwit, low

power consption, saller size and less circit coplexity

wic are also important requireents for R- wireless

interconnects an battery powered sensor netwos [].

Te wireless interconnect tecnology is a comparatively new

approac, wic as te potential to become a copetitive

candidate to replace global wires. Conventional interconnect

systes sing etal sffers o parasitic capacitances,resistances dring ig equency operation wic limits te

ability of high-speed operation [2].Wireless intercoect

systes offer the feasibility of wireless high-speed

communication among cips. As a result, wireless

interconnect systes ave receive uc attention for bot

data conication and clock distrition [2].

n tis paper, a 5 Gbps CMOS pulse generator wit

ig peak-to-pea amplitue an low power issipation using

978-1-4673-1154-012/$3.00 2012 IEEE

PSK odulation because of low ER is introduce. Te

esigne pulse generator circuit is analyzed in Section I.

Siation rests and coparison of the circit perforancewit tat of te reported pulse generator circuits are

presented in Section II. Te concusion is in Section V.

I. ULSE ENERATOR IRCUT ESGN

Te proposed circuit arcitecture can be use to generatethe tra-wideand BPSK odated pse with for on-chipwireless interconnects is sown in Figre. . Te operation ofthe circit has been explained in the following paragraphs.

A W Pulse Generator Architecture

Te pulse generator is capable of generating Gaussian

ono-pulse an adopting PSK moulation tecnique. So tis

circit has two sections: one is responsible for generatingGaussian mono-pulse for '0 an anoter for generating

reverse polarity Gaussian mono-pulse for '1 . Eac section is

divided into tree basic stages: triangar pse generator,

elay bloc an output stage tat rives te loa. Te input

pulse Cloc) and Data wic are followe by a NAND gate

generate a pse. Then the pse is passed trogh a pse

shaper to prodce triangar pse. Two pses, one derived

o elay block and oter o te NAND gate (two pulses

are of opposite polarit) provide the inpt signals to the otpt

stage. As the otpts of the NAND gates (node A and node E)

are not exactly triangular enoug, so we introce a simple

pulse saper circuits tat resape te pulses to triangularpses (node B and node F) as shown in igre The ainobjective of te elay bloc is to prouce a elay of some

picoseconds between te pulses fee at te output stages

sccessivey to generate a Gassian ono-pse. The delay

epens on te size an number of NOT gates use in te

elay block. Te PMOS and NMOS ansistor sizes in output

stage are chosen based on the need of aplication of the

wavefor. Each UWB pse is generated for corresponding

ata bit.

ICIEV 2012


2/4

IEEE/OSA/IAPR Inteational Conference on Infoatics, Electronics & Vision

B. BPSK Modulated Pulse Generation

Two dal inpt NAND gates are sed in plse generatorcircit to in order to control the occrrence of otpt BPSKUWB plses. To adopt BPSK odlation, a data bit '0 isrepresented by a Gassian ono-plse and a data bit ' ' isrepresented by a reverse polarity of that Gassian ono-plse.Separate plse generator sections are sed for this prpose.

The inpt clock to the circit shold have a low to hightransition at the start of each data bit for the proper nctioningof the circit. Otpt plses of the NAND gates are prodceddring high to low transition of the inpt clock. To reshapethese plses to trianglar plses, we have sed a siple plse

shaper circit by controlling the tie of rise and fall of theplses. The otpt of the plse shaper are shown inFigre.2(a) at node F and in Figre.2(b) at node B. In order togenerate a Gassian ono-plse, two delayed plses ofreverse polarity are feed to the otpt stage. A slight variationin this schee can prodce two Gassian plses, one is ofopposite polarit to other representing the data bit '0 and '1.

Figre. shows different nodes and stages of each section.The wavefors at node E, F, G, H and K are shown inFigre.2(a) for generation of plses representing data bit '0and the wavefors at node A, B, C and K in Figre.2(b) forgeneration of plses representing data bit '1. The otptplses are seen across the load resistance (R).

CckDt

t

Dyg Ps t i Bc

Niv MoncylI Gnr f '1

_._._.___-

p StageFigure: 1 Schematic diagram of the proposed UWB pulse generator.

III. IULATION ESULTS ND EASURED

ERFORANCE

The proposed plse generator is designed sing IBM 90nCMOS tecnology with 1.2 V spply. All the perforanceanalysis was perfored in HSPICE.

A. Output Pulse Trainfor Random Data Input

A sqare clock plse train with eqency of 10 GHz is sedto drive the plse generator. Figre shows the silated

88

otpt for a rando data bit. The UWB plses representingeach databit are delayed by an average of 200ps becasetrianglar plses generate nearly at the end of the data bit. Thepeak to peak swing on a K otpt load is 800V and theaverage plse width is 12ps. Plse width of positive Gassianonocycle is 121ps and reverse is 128ps (Figre.3).So thereis no chance of overlapping of two adjacent plsesrepresenting data bits as dration of each data bit is 200ps.

Figre. shows variation in aplitde of otpt plses de tovariation in otpt load (R). Otpt p-p voltage for different is shown in Table. I

M r

r l \

I

soLI

!

F

j[

G

U

A

K;

t

n :o 2 f) e)(a)

au r

jn

1

I

A

B I

c

V

V

K

1h

f J

J

r

i

I

,

l l(b)

'

Figure.2 Timing diagram of data and (a) pulses at different nodes (E, F,G, H, K) for data bit 0 and (b) for data bit at different nodes (A, B, C,K). Voltage at each node is shown and labeled to the le. Vertical isrepresents voltage in Volt.

ICIEV 2012


3/4


89 ICIEV 2012

Figure. 3 BPSK UWB pulses

Figure.4 Generated UWB pulses for random data input 1010001100

Figure.5 Variation in amplitude of output pulses due to variation in loadresistance (RL).

TABLE I. OUTPUT VOLTAGE DUE TO VARIATION IN RL

RLin Output peak-to-peak voltage swing5K 802mV

4K 762mV

3K 658mV

2K 521mV

1K 320mV

B. Frequency Spectrum

The pulse power spectral density is shown in Figure. 6.

The -3dB bandwidth is found to be 10GHz from 5GHz to 15

GHz centered at 10GHz.

Figure.6 PSD of UWB pulse

C. Power Consumption

As most of the time all the MOSFETs remain OFF, there

is no specific path for the flow of static current from supply

to ground. So the pulse generator circuit shows much lowerstatic power consumption. The circuit consumes only

dynamic power and the power consumption including all the

gates is only 0.227mW which implies .0455pJ/pulse for a

supply voltage of 1.2V.

D. Monte Carlo Analysis

Monte Carlo statistical simulations provide the best

approximation of the circuit performance variation over the

manufacturing process window. Multiple simulations were

Figure.7 Sensitivity analysis: Monte Carlo

run to randomly vary process (doping, geometric effects etc.)

and hence device parameters (oxide thickness, junction/well


4/4


capacitance, treshold voltage etc.) within the expected

istributions[9]. Te estimate sensitivity of te output signal

is sown in Figre.7. Te output signal sows reasonable

discrepancy as a rest of process and isatch variations

(i.e., typical of 40 iterations).Variations in width with respect

to time for positive mono-pulse is up to 12ps an for negative

ono-pse is p to 7ps approxiately.

E Corner SimulationFro the coer siation, it is observed that TT, SF

coers offers the best otpt with better peak-to-peak voltagewith low power dissipation whereas SS coer offers a verlow pe-to-pea voltage compared to te oter coers. Tisimplies tat te normal nctioning of te circuit is egraed ifbot NMOS an PMOS are slow. Table I sows tecomparative analysis of coer simulation results.

TALE II.

ONER IMULATION ESULTS

Corner Type Output Voltage (Peak- Power Dissipatio

to-Peak) pJ/Pulse)

T 802mV .0455 888mV .0546SS 81mV .0012FS 503mV .0388SF 850mV .0490

Te performance of te propose pulse generator is given inTable I

TABE I. ROPOSED LSE GENERATOR ERFOMANCE

Performace Parameters Values

Technology BM 90nm CMOSPeak-to-Peak Pulse Aplitude 800mV

Pulse uration 125psPower Consumption .227mW

(at Data rate of 5Gbps) .0455pJ/pulse

Bdwidth 5GHz-15GHz

Comparison with Other Reported Pulse GeneratorsTable IV depicts that the proposed pse generator is one

of the ost effective UWB pse generator for IR-UWBconication.

TALE IV. OMPARISON WITH OTHR ULSE GENERATORSCMOS Energy Amplitude(Peak Pulse Width

Technology Consump- -to-Peak) (ns)tion (mV)

(pJ/pulse)

0.18!m [4] 50 200 1.1-4.5

0.18 m [5] 18 180 3.5

0.13 m [6] 125 450 0.6

0.18!m [7] 4.7 500 0.8

90nm [3] 0.6 450 0.6

90nm [8] 1.42 502 0.06

90nm .0455 800 0.125

(proposed)

90

V. ONCLUSON

An efcient R- pulse generator for on-cip wirelessinterconnects is emonstrate. Te circuit was designeusing IBM9RF 90nm CMOS tecnology. It posses te abilityto andle data bit at a rate of 5Gbps. Wit a supply of .2V, itcan generate BPSK odated Gssian ono-pses withpeak-to-peak voltage of 800V. Negligible static crrent and

very low dynaic power consption akes it not onlyappropriate for on-chip ipleentation t also for batterypowered sensor networks for other applications sch asmedical diagnosis.

CKNOWLEDGENT

Athors wod like to thak Dr. A.B.M. Harn-Ur-ashidand the Departent of Electrical and Electronic Engineeringof Bangladesh University of Engineering and Tecnology fortheir co-operation and spport.

EFRNCES

[] Y. Zhu, 1 Hu and Hui Wu, "A 2.5 Gpulse/s, 25pJ/pulse, .18m COSImpulse Radio UWB Transmitter Based on Dual-Polarity Distributedeform Generator. Silicon Monolithic ntegrated Circuits in RSystems, 2009. SiRF '09, pp. 1-4.

[2] B. Floyd, C. . Hung, d K. O. Kenneth, "Intra-chip wirelessinterconnect for clock distribution implemented with integratedantennas, receivers, d trsmitters, IEEE 1 Solid-State Cir., vol. 37,no. 5, pp. 534-552, ay 2002

[3] Y. Wang, K. niewski, V. Gaudet et al "A CMOS R-UWB TransceiverDesign for Contact-Less Chip Testing Applications, IEEE transactionson circuits and systemsii: express briefs, vol. 55, no. 4, April 2008.

[4] J. Ryckaert, C. esset, ort, M. Badaroglu, V. e Heyn, P.Wambacq, G. V der Plas, S. Donnay, B. Van Poucke, and B.Gyselinckx, "Ultra-wi de-band transmitter for low power wirelessbody area networks: esign and evaluation, E Trans. CircuitsSyst., vol. 52, no. 12, pp. 2515-2525, Dec. 2005.

[5] .- Ph, 1 Lee, V. Krizhanovskii, S.-K. Han, and S.-G. Lee, "A 18-pJ/pulse OOK CMOS transmier for multiband UWB impulse radio,IEEE icrow. Wireless Compon. Lett., vol. 17, no. 9, pp. 688-690, Sep.2007.

[6] 1 Smaini, C. Tinella, . Helal, C. Stoecklin, 1 Chabert, C. evaucelle,R. Caenoz, N. Rinaldi, d D. Belot, "Single-chip COS pulsegenerator for UWB systems, IEEE 1 Solid-State Circuits, vol. 41, no.7, pp. 1551 -1 561,

Ju\. 2006.[7] .- Ph, V. Krizhanovskii, S.-K. Han, S.-G. Lee, H. seo Oh, and N.

S. Kim, "4.7pJ/pulse 7 derivative Gaussi pulse generator for impulseradio UWB, in Proc. E SCAC, May 2007, p. 3043-- -3046

[8] . Arafat, S..S. Rashid, Roy, and B.. H. Rashid ASimple High ata Rate UWB OO Pulse Generator with TransmittedReference for On-Chip ireless nterconnects. n CECE, ecember2010, p.131134

[9] IB9RF COS9RF Training ual, pp 133

ICIEV 2012

Documents

UWB Communications