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Accordo di Programma FIRB
Unità 5 IUSS -‐ Is8tuto Universitario di Studi Superiori
prof. Paolo Arcioni prof. Andrea Mazzan8 prof. Federico Montecchi prof. Francesco Svelto
Accordo di Programma FIRB
• Altro personale: doDorandi: Marco Sosio (21° ciclo) Federico Vecchi (23° ciclo) giovani ricercatori: Mohammed Vahidfar (PhD) Eyssa Wissam (PhD) Enrico Monaco (PhD stud.t)
Accordo di Programma FIRB
• APvità:
Task 0.1: “Program Management”
Task 1.7: “Enabling Blocks for UWB Applica8ons”
Task 1.8: “Enabling CMOS Receiver Blocks for Millimeter-‐Wave Applica8ons”
Task 2.1: “Millimeter-‐Wave Fully Integrated Receiver Front-‐End”
CMOS Analog Processing of UWB signals for communications, automotive and imaging
Computer and peripherals data transfer 3GHz-10GHz UWB OFDM Gbit/sec connectivity
24GHz ISM and unlicensed around 60GHz
Automotive radars 24GHz and 77GHz
Imaging: security and medical THz gap : 30GHz – 300GHz
CMOS Analog Processing of UWB signals for communications, automotive and imaging
Outline • Quadrature Demodulator and Frequency Synthesizer for 3-10 GHz WiMedia UWB (Task 1.8)
• A 24GHz SubHarmonic Direct-Conversion Receiver (Task 1.9)
• A Wideband 60GHz Receiver Front-End for Gbit/sec Communications (Task 1.9, Task 2.1)
• Frequency Generation for Sub-THz Applications
Quadrature Demodulator and Frequency Synthesizer for 3-10 GHz
WiMedia UWB (Task 1.8)
A.Mazzanti, M.Vahid, M.sosio, F.Svelto, “A Reconfigurable Demodulator with 3GHz – 5GHz Agile Synthesizer for 9-band WiMedia UWB in 65nm CMOS” Proceedings of the IEEE International Solid State Circuit Conference (ISSCC),pp. 412-413, San Francisco, Feb. 2009.
A.Mazzanti, M.Vahid, M.sosio, F.Svelto, “A Low Phase-Noise Multi-Phase LO Generator for Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers” IEEE Journal of Solid State Circuits, Vol. 45 no. 10, pp. 2104-2115 Oct.2010
Motivation
A 3-5GHz synth. driving a demodulator reconfigurable between fundamental and sub-harmonic modes for groups 1,3-4 is proposed
• WiMedia UWB tailored to short range, high data rate, WPAN
• Wide bandwidth makes synthesizer design challenging: - Quadrature LC unfeasible - Rings show poor performances - SSB mixers suffers from spurs and power consumption
Reconfigurable Sub-Harmonic mixer
Sub-Harmonic mode Fundamental mode
2
Reconfigurable mixers for UWB
Sub-Harmonic
• Groups 3,4 fall in frequency at roughly twice Group 1 • Synthesizer for Group 1 demodulates also Groups 3 & 4
Synthesizer band only 1/3 the RF band
Fundamental
3
Demodulator architecture
I & Q reconfigurable demodulators Multiphase LO provided by a 4-stage locked ring oscillator Locking signal provided by 3 multiplexed LC-PLL to meet phase noise and settling time
4
Experimental Results
CMOS 65nm LP from STMicroelectronics active area 1.5 mm2
8
Gain [dB] 10 Input Referred Noise [nV/√Hz] 2.3
IIP3 [dBm] 11 IIP2 [dBm] 40
I & Q phase error < 2° Phase Noise @ 10 MHz [dBc/Hz] -128
Integrated Phase Noise [deg] 1.7 Spurs Level [dBc] - 43
Frequency Hopping time [ns] < 6ns Power Consumption [mW] 79
Silicon Area [mm2] 3.7 (1.5 Active) Technology CMOS065 - LP
A 24GHz SubHarmonic Direct-Conversion Receiver Front-End
(Task 1.9) F.Svelto, A.Mazzanti, M.Sosio, M.Repossi, “A CMOS Sub-Harmonic Architecture for Signal Down-Conversion at Ka-Band” Proceedings of the IEEE International Workshop on Radio-Frequency Integration Technology, pp. 179-182, Singapore, Dec. 2007.
A. Mazzanti, M. Sosio, M. Repossi, F. Svelto, “A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS” Proceedings of the IEEE International Solid State Circuit Conference (ISSCC),pp. 216-217, San Francisco, Feb. 2008.
M.Sosio, A.Mazzanti, M.Repossi, F.Svelto “A Low-Power Ka-band Direct Conversion Receiver Employing Half-Frequency Local Oscillator in 65nm CMOS”, Proceedings of the 39th European Microwave Conference ),pp. 256-259, Rome, Sept. 2009.
A. Mazzanti, E. Sacchi, P. Andreani, F. Svelto, “Analysis and Design of a Double-Quadrature CMOS VCO for Subharmonic Mixing at Ka-Band”, IEEE Transaction on Microwave Theory and Techniques, Vol. 56, no. 2, pp. 355-363, Feb. 2008.
A. Mazzanti, M. Sosio, M. Repossi, F. Svelto, “A 24 GHz Subharmonic Direct Conversion Receiver in 65 nm CMOS”, IEEE Transaction on Circuits and Systems-I, in press.
Sub-harmonic quadrature receiver
Synthesizer running at half frequency, thus saving power
• Quadrature down-conversion: no need for an IF stage
• No serious spurious coupling issue because LO and received signal are at different frequency
Multiphase local oscillator
• 4 coupled VCOs in a ring structure provide 8 differential time-shifted signals
• Mild trade-off between phase noise and phase accuracy, set by Icp/Isw
• Icp=Isw leads to acceptable phase error with only 1dB of noise penalty
Comparison with Ka-band VCOs ref fo
[GHz] T.R [%]
P.N. @1MHz [dBc/Hz]
Power mW
FoM [dBc/Hz]
Notes
MWCL 06 19.9 2.7% -108 32 179 Differential
JSSC 06 24.4 6% -99.3 14.5 175.3 Differential
ISSCC 07 26 23.6% -92.6 45 164.5 Differential
JSSC 03 26.8 15.2% -84.2 129 151.6 Quadrature
RFIC 05 23.7 6.8% -94.0 22 168 Quadrature
ISSCC 05 32 6.3% -97 140 165.5 Quadrature
This work 13 26.5% -110 15 180.5 half frequency (8 phases)
Despite the requirement for 8-phases, running the VCO at half frequency gives benefits to tuning and spectral purity without power penalty
Experimental Results
65nm CMOS from STMicroelectronics, 2.1 mm2
Gain [dB] 31.5 Minimum NF [dB] 6.5
Input 1dB compression [dBm] -25 IIP3 [dBm] -17 IIP2 [dBm] 0
I & Q phase Error < 3° VCO Tuning Range [%] 26.5
VCO Phase Noise @ 1MHz [dBc/Hz]
-110
LO at Input [dBm] < -65 (at fo/2) < -90 (at fo)
Silicon Area [mm2] 2.1 (1.4 active) Power Consumption [mW] 40.8 (LNA+Mixers)
22.8 (VCO + Dividers)
28.8 (base-band)
A Wideband 60GHz Receiver Front-End for Gbit/sec Communications
(Task 1.9, 2.1) S. Bozzola, D. Guermandi, A. Mazzanti, F. Svelto “An 11.5% frequency tuning, -184 dBc/Hz noise FOM 54 GHz VCO” Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium 2008, pp.657-660, Atlanta, June 2008.
S. Bozzola, D. Guermandi, F. Vecchi, M. Repossi, M. Pozzoni, A. Mazzanti, F. Svelto, “A Sliding IF Receiver for mm-wave WLANs in 65nm CMOS” Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) 2009, pp.669-672, San José, Sept. 2009.
F. Vecchi, S. Bozzola, M. Pozzoni, D. Guermandi, E. Temporiti, M. Repossi, U. Decanis, A. Mazzanti, F. Svelto “A Wideband mm-Wave CMOS Receiver for Gb/s Communications Employing Interstage Coupled Resonators” Proceedings of the IEEE International Solid State Circuit Conference (ISSCC),pp. 220-221, San Francisco, Feb. 2010.
F.Vecchi, S.Bozzola, M.Pozzoni, D.Guermandi, E.Temporiti, M.Repossi, U.Decanis, A.Mazzanti, F.Svelto “A 60GHz Receiver with 13GHz Bandwidth for Gbit/s Wireless Links in 65nm CMOS” Proc. of the IEEE International Conference on Integrated Circuits Devices and Technology, pp. 228-231 Grenoble, June 2010
High Rate 60 GHz Phy Proposal*
• Large RF bandwidth (~9 GHz minimum)
• Minimum Sensitivity: from -60 dBm (1 Gb/s) to -50 dBm (4 Gb/s)
• Maximum Noise Figure < 10 dB
• Large LO tuning range required
• Very stringent phase noise at maximum data rate
* ECMA International, “High Rate 60 GHz Phy, MAC and HDMI PAL”, Standard ECMA-387, 1st Edition, Dec. 2008. [Online].
Phase Noise Requirements
• Phase noise rotates signal constellation and impairs BER • An LO phase noise < -113dBc/Hz @10MHz offset is required in the most stringent case
IEEE 802.15-06-0477-01-003c 2Gbit/sec 16-QAM
Sliding IF Receiver Architecture
• First down-conversion to 1/3 of the received frequency lower tuning-range required, relatively low power • Only one PLL needed • Injection Locked Dividers to generate I/Q half frequency signals
Wide-band LNA based on coupled resonators
Cc ↑
• gain-bandwidth trade-off in tuned inter-stage loads leads to large dissipation. • coupled resanators are introduced to increase bandwidth and limit dissipation
CMOS Passive Components for mm-wave have been studied intensively (Task 1.8)
F. Vecchi, M. Repossi, A. Mazzanti, P. Arcioni, F. Svelto “A Lumped-Element Physical Model for Symmetrical Spiral Inductors and their Mutual Cross-Talk in Silicon RF-ICs” Proceedings of the International Symposium on Microwave and Optical Technology, Rome – Italy, Dec. 2007.
F. Vecchi, M. Repossi, A. Mazzanti, P. Arcioni, F. Svelto, “A Simple and Complete Circuit Model for the Coupling Between Symmetrical Spiral Inductors in Silicon RF-ICs” Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium 2008, pp.479-482, Atlanta, June 2008.
F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni and F. Svelto, “Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations” IEEE Journal of Solid State Circuits, Vol. 44, No. 9, pp. 2605-2615, Sept. 2009.
F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni and F. Svelto, “Analysis of Loss Mechanisms in Coplanar Waveguides Integrated on Bulk CMOS Substrates” Proceedings of the 39th European Microwave Conference, pp. 189-192, Sept. 2009.
Shielded CPW (S-CPW) *
Best attenuation ever reported for standard scaled CMOS process
* F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto: “Design of Low-loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, September 2009, pp. 2605-2615.
Experimental Results
Gain 35.5 dB NF 5.6-6.5 dB RF Bandwidth >13 GHz Image Rejection 80 dB LO Tuning Range 12.6 % I/Q Mismatch < 3°
LO Phase Noise (from 60GHz)
-115 dBc/Hz @ 10MHz
Input 1 dB Comp. Point (Low Gain) -21 dBm
Power 75 mW
Summary
• Inter-stage coupling is effective to enhance the gain-bandwidth product of gain stages in mm-Wave receivers
• The realized solution proves a very good sensitivity over a wide band of 56GHz – 68GHz
• A remarkable phase noise has been achieved with a VCO tuning of 12.6%
Frequency Generation for Sub-THz Applications
E. Monaco, M. Borgarino1 F. Svelto, A. Mazzanti“A 5.2mW Ku-Band CMOS Injection-Locked Frequency Doubler with Differential Input / Output” Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp. 61-64 San José, Sept. 2009.
A.Mazzanti, E. Monaco, M. Pozzoni, F. Svelto, “A 13.1% Tuning Range 115GHz Frequency Generator Based on an Injection-Locked Frequency Doubler in 65nm CMOS” ,Proceedings of the IEEE International Solid State Circuit Conference(ISSCC), pp.422-423, San Francisco, Feb. 2010.
E. Monaco, M. Pozzoni, F. Svelto, A. Mazzanti “A 6mW, 115GHz CMOS Injection-Locked Frequency Doubler with Differential Output”, Proceedings of the IEEE International Conference on Integrated Circuits and Technology , pp. 236-239 , Grenoble, June 2010.
E. Monaco, M.Pozzoni, F. Svelto, A. Mazzanti “Injection-Locked CMOS Frequency Doublers for u-Wave and mm-Wave Applications”, IEEE Journal of solid State Circuits , Vol. 45, no.8, pp. 1565-1574, Aug. 2010.
VCOs at fundamental frequency State of the art 60GHz VCOs display ~10% Tuning Range Scaling to 120GHz (assuming constant Q):
60GHz 120GHz
L L/2 C C/2
Rp, gm Rp, gm
Cactive Cactive
Cv ~Cv/10 10% T.R. 2.5% T.R.
constant Q is very optimistic
higher current and tech. scaling give marginal benefits
Half frequency VCO + doubler • Tuning range preserved • Phase noise improvement due to higher Q of passives • Power saving in the divider of the PLL
Frequency doubler performance is key
Doubler circuit topology
C-L-C and M1 form a Pierce oscillator
M2’-2’’ inject the double frequency locking current
Supply provided by a choke inductor
CCM balances the two outputs
Comparison with fundamental freq. VCOs Ref. f0 [GHz] Phase Noise [dBc/
Hz @10MHz] Tuning Range
[%] Pdiss [mW]
FoMT [dB]
[3] 98.0 -102.7 2.55 7 -162.2 [3] 105.2 -97.5 0.19 7.2 -134.9 [4] 114.0 -107.6 2.10 8.4 -165.9 [5] 109.2 -105.2 2.24 9.6 -163.1 [5] 122.8 -100.2 1.30 9.6 -154.4 [5] 139.6 -93.0 0.86 9.6 -144.8
[6]* 102.2 -100.9 4.12 7.6 -164.6 This Work 115 -107 13.1 12 -179.8
* 32nm SOI-CMOS