Using Programmable Logic to Accelerate DSP Functions

“An Overview“

Greg GoslinDigital Signal Processing Applications Manager

Corporate Applications Group15OCT95

Agenda When to use FPGAs for DSP, an Overview

– What is Digital Signal Processing (DSP)?

– Where is DSP Used?

– Traditional DSP Approaches.

The Promise of Programmable Logic– Case Study: Finite Impulse Response Filter.

– Case Study: Viterbi Decoder.

Building Fast Filters in FPGAs, a Tutorial– Efficient Algorithms for FPGAs.

– Using Distributed Arithmetic for Filter Designs.

– How to use an FPGA to Building Filter Designs.

Design Methodologies for DSP in FPGAs– Design Entry and Third Party Software Tools.

What is Digital Signal Processing (DSP)? DSP is the arithmetic processing

of digital signals sampled at regular intervals

DSP can be reduced to three trivial operations:

– Delay

– Add

– Multiply

Accumulate = Add + Delay

MAC = Multiply + Accumulate

The MAC is the engine behind DSP– More MACs = Higher Performance, Better

Signal Quality

– MACs vs. MIPS, not always equal

3 MACs

50* MACs

100 MACs

Filter

Where is DSP Used?DSP has many names and acronyms:

Filtering - – FIR

– IIR

– Viterbi

Compression - – Decompression

– MPEG

– JPEG

– ADPCM

Convolution

Correlation

Modulation

$0 $100 $200 $300 $400 $500 $600

Communication

Computer

Instrumentation

MIL/Aero

Consumer

Industrial

OfficeAutomation

1994 Consumption

($US MILLION)

(Source: Forward Concepts)

Traditional DSP Approaches Digital Signal Processor IC

– Software programmable, like a microprocessor

– Single MAC unit

– All processing done sequentially

– Fit the algorithm to the architecture

ASIC (gate array)– Fit the architecture to the algorithm

– Significantly higher performance than DSP processor

– High cost and high risk to develop

– Usually only for high-volume applications

MAC

Data Controller

MemoryADC

Analog input Analog output

Digital output

‘Traditional’ DSP Processor

DAC

Pros

High performance

High density

One chip solution

Cons

High design risk

Long design cycle

Pros

High flexibility

Good adaptability

Low design risk

Cons

Performance

Hardware Complexity

The Promise of Programmable Logic

ASIC DSP ProcessorFPGABest from both worlds

plus:

Efficient IC architecture

System features

Short design cycle

Automatic migration to low cost HardWire

XC4000E Configurable Logic Blocks (CLBs)Simplified Block Diagram

logicfunc.of G1to G4

logicfunc.of F1to F4

logicfunc. ofF',G', and H1

F'

G' SDD Q

ECRD

SDD Q

ECRD

1

1

S/Rcontrol

S/Rcontrol

H1 DIN S/R EC

C1 C2 C3 C4

YQ

GY

XQ

FXK (clock)

G4G3G2G1

F4F3F2F1

G'H'

H'F'

DIN

F'G'

H'

DINF'G'H'

MUX

MUX

Muxes allow 3 independent inputs

to “H” function generator

Look Up Tables can be defined as any 4-input function

including 16x1 SRAM

XC4000E Dual-Port RAM Each CLB can be configured as 16x1 dual-port, synchronous SRAM

Simultaneous read access through ADDR_F and ADDR_G

Write address, data, and control are synchronized to write clock

ADDR_G

D Q

CE

D Q

CE

D Q

CE

DIN

WE

WCLK

DOUT_G

DOUT_F

ADDR_F

MU

X

CommonRead/Write

Address

Read-OnlyAddress

Bit_0

Bit_1

Bit_15

4

4

F GM

UX

0

15

MU

X

0

15

DE

CO

DE

R

0

15

Synchronization Registers

D Q

D Q

XC6200XC6200 System Features MeetEmbedded Coprocessing Requirements

CPU

ReconfigurableCoprocessor

XC6200XC6200

I/O

I/OMemory

1000x improvement in reconfigurationtime from external memory

FastMAPtm assureshigh speed access toall internal registers

All registers accessed viabuilt-in low-skewFastMAPtm busses

Microprocessor interfacebuilt-in

High capacity distributed memorypermits allocation of chipresources to logic or memory

Partial Reconfigurationfully supported

DSP Functions Are Parallel Algorithms 8-Bit, 16-Tap Finite Impulse Response (FIR) Filter

Equation:

REG REG REG REG REG REG REG

REG REGREGREGREG REGREGREG

Data InputX[7:0]

0 15 1 14 2 13 3 12 4 11 5 10 6 9 7 8

Data OutputY[9:0]

C0 C1 C2 C3 C4 C5 C6 C7Multiply by

FilterCo-Efficients

FilterTaps

AccumulateValues

Y c x c x c x c x c x c x c x c x c xj k kjk

n

1

0 0 1 1 2 2 3 3 3 12 2 13 1 14 0 15

Symmetrical Coefficients

FPGAs Outperform‘Traditional’ DSP Processors

22.00

0.241.00

2.60

4.00

16.00

0

5

10

15

20

25

133 MHzPentium™Processor750 KHz

Single50 MHz

DSP3 MHz

XC4003E-3FPGA

(68% util.)8 MHz

Four50 MHzDSPs12 MHz

XC4010E-3FPGA

(98% util.)56 MHz

XC4013E-2FPGA

(75% util.)66 MHz

Per

form

ance

Rel

ativ

e to

50

MH

z F

ixed

-Po

int

DS

P

Serial Distributed Arithmetic(SDA)

Parallel Distributed Arithmetic(PDA)

(est.)8-Bit, 16-Tap FIR Filter

Performance Comparisons(External Performance)

FPGA

FPGA

FPGA

MCM

Case Study: Viterbi Decoder(FPGA-based DSP Co-Processor)

+-

+

-

Old_1

INC

Old_2

-+

+

-

++

++

OptionalPipeliningRegisters

MUX

MUX

New_1

Diff_2

Diff_1

New_2

MSB

MSB

Prestate Buffer Bit

24-bit 24-bit24-bit

1 0

REG

REG

REG

REG

REG

REG

REG

REG

I/O BusI/O Bus

DSP-Only DSP + FPGA8 DEVICES 4 DEVICES

Two 66 MHz DSPsSix 15 ns SRAMsSystem logic

One 66 MHz DSPXC4013E-3 FPGA (44%)Three 15 ns SRAMs

135 ns

360 ns0

1

2

3

Rel

ativ

e P

erfo

rman

ce

2.67 times better performance with

FPGA-assisted DSP

Two 66 MHz DSPsSix 15 ns RAMs

66 MHz DSP+FPGAThree 15 ns RAMs

What to Look for in Your DSP Application Identify Parallel Data Paths

Find Operations that Require Multiple Clock Cycles

Processor Bottlenecks

Flexibility

Parallel Data Paths

Scaleable Bandwidth

Design Modification

Device Expansion

DSP Pro

cess

or

ASICFPG

A= NO= YES

When to Use FPGAs for DSP

0

5

10

15

20

25

30

35

40

45

50

1 4 8 12 16 20 24 28 32 36 40 44 48

Dat

a R

ate

(wit

h 5

0 M

Hz

syst

em c

lock

)

Number of DSPs4 DSPs3 DSPs2 DSPs1 DSP

Arithmetic Operations Per Sample (MACs)

FPGARegion

DSPRegion

High sample rates– Up to 66 MHz with XC4000E-2

Low sample rates– Integrate DSP + system logic in a low-

cost DSP using serial sequential algorithm

Short word lengths– DA algorithm gets faster with shorter

word length

Lots of filter taps– FPGA processes all taps in parallel,

faster than DSP

Fast correlators

Single-chip solution required

HardWire gate array migration path for high-volume designs

Information on DSP Applications Greg Goslin

– Digital Signal and Image Processing Applications Manager

Email: dsp@xilinx.com

WEB: http://www.xilinx.com/dsp.htm

Fax: 408-879-4442