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Highest Performance Programmable DSP
Solution
April 19, 2023
®
www.xilinx.com
Xilinx DSPHighest Performance
XCV3200E is the Worlds’ Highest Performance Programmable DSP
Unique features— Industry’s highest density— More gates = more parallel processing =
higher performance— Segmented routing and LUT based
architecture is superior for DSP— Parameterized cores with Smart-IP
automatically yields optimal implementations
4.4 Billion
Xilinx TI V3200E C64x
MA
Cs
per S
econ
d
®
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Fastest and Most Flexible
Xilinx FPGAs
Highest-performance
+ Reconfigurable
+ Quick turnaround
+ One-chip solutions
®
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Increased Sampling Rate
General-purpose DSP processor - sequential processing
FPGA - parallel processing
* mac - Multiply and Accumulate
....
Reg Reg Reg Reg
C0
Data Out
Data In
n Tap FIR Filter
C1 C2 Cn
rep n
mac*
n Tap FIR Filter
Loop Algorithmn times
®
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Virtex-EM Optimized for DSP
Building Blocks for DSP— Data Storage— Multiplication— Addition/Subtraction— Delay— System Level Integration
MemoryInstruction/Data/
CoefficientStorage1.1 Mbits
High Speed ProgrammableLogic Cells
3.2 M Gates
DLLClock/Phase
Synthesis
311 MHz
PackagingChipScale
Fine Pitch BGA
556 User I/O
Multiple ProgrammableI/O Interfaces
622+ Mbps
Virtex - EM 1.8 Volt
®
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Virtex - EPerformance Leader
160 MSPS160 MHz
FIR Filter 256-tapLinear phase16-bit data/coef.
128 Billion MAC/s
16x16 Multiply Accumulate (MAC)
Xilinx FPGAVirtex-E –08
Function
17 MSPS1.1 GHz
4.4 Billion MAC/s
Processor TI C64x
®
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FIR Filter Generator Only filter core that enables true area and
performance tradeoffs
WORDPARALLEL
BIT SERIAL
BIT SLICE
Area/Cost
PERF
ORM
ANCE
Worlds fastest programmable DSP device
Lower cost than DSP processors
®
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Spartan-II Cost Advantage
ASSP with Equivalent configuration
XC2S10050% cost-saving
Reed-Solomon Encoder/Decoder
High-end DSP processor
Alternative Solution
XC2S1570% cost-saving
FIR Filter 16-tap16-bit data/coef.
Xilinx Solution
Function
®
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Design FlowSystem Design
Domain
Algorithm design
System verification (floating point)
Optimization and re-verification
Conversion tofixed point
MATLAB and Simulink
FPGA DesignDomainAutomatic
generation of HDL
Behavioral simulation
Synthesis, place and route
Timing verification
Foundation/Alliance
GAP
Xilinx System Generator & LogiCOREs
®
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Conversion tofixed point
Simulink Environment
®
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Automatic generation of HDL
Xilinx Blockset for Simulink
Automatically maps to Xilinx LogiCores
Fully Parameterizable
Automatically writes
system HDL
System Generator
®
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Timing verification
Behavioral simulation
Synthesis, place and route
Project Manager
®
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Algorithms
— Common DSP Algorithms– FIR Filter
– Halfband, Hilbert, Interpolated, Multi-channel, Adaptive – FFTs, DDS, Sine/Cosine– FEC
– Reed Solomon, Viterbi— Video and Imaging
– DCT/iDCT, Color space converters— High speed arithmetic
– Fixed point Multiplier, Reloadable multiplier, Divider— Sync/Async FIFO
Complete listing on www.xilinx.com/ipcenter
®
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Xilinx CORE Generator
IP Catalog & Core Delivery System
®
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Xilinx Smart-IP TechnologyFeatures FPGA Architecture tailored to cores
— Segmented routing— Distributed & block memory
Pre-defined core placement & routing
Customer Benefits Performance independent of:
— Core placement— Number of cores used— Surrounding user logic— Device size— EDA tools
Core A
Core A
Core A
Core A Core B
Consistent Performance
FPGA 3
FPGA 2
FPGA 1
®
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Shorter Design Cycle
Development Time
System Design Analysis & Tradeoffs FPGA Design
Traditional design methodology
System Design Analysis & Tradeoffs
Using cores
System Design
Using The Xilinx System GeneratorOnly Xilinx addresses this
with The MathWorks!
Cores address the FPGA design phaseCores address the FPGA design phase
®
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Density Roadmap
Virtex V1000
Den
sity
(sys
tem
gat
es)
50M Gates
Virtex 0.13µ
XC40250XV
50M
2M
1M
500K
1998 1999 2000 2001 2002 2003 2004
4M Virtex 0.15µ
Virtex 0.18µ
10M
4 Tera MAC in 2004 !
®
Reference Material
®
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Virtex-E Optimized for DSP
0.18u 6 Layer Metal— Super high performance— Up to 3.2 million gates
High-performance dual-port on-chip BlockRAM— FFT integration, data
buffers…
Distributed on-chip memory— DA FIR Filters…
Multiply AND logic— 200+ MHz
300+ MHz DLLs— High-performance clock & I/O
BRAM
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