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_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
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USB Host Charger Identification Analog Switches
19-5293; Rev 1; 3/11
General DescriptionThe MAX14566E/MAX14566AE/MAX14566BE are sec-ond-generation USB devices that combine Hi-Speed USB analog switches with a USB host charger (dedicated charger) identification circuit. These devices support both the latest USB Battery Charging Specification Revision 1.2 including data contact detection and a set resistor bias for Apple-compliant devices as well as legacy USB D+/D- short detection using data line pullup. The MAX14566E has a pMOSFET open-drain control output (CEN) and the MAX14566AE has an nMOSFET open-drain control output (CEN) to restart the peripheral connected to the USB host.
These devices feature high-performance Hi-Speed USB switches with low 4pF (typ) on-capacitance and low 4.0I (typ) on-resistance. In addition, the devices feature a single digital input (CB) to switch between pass-through mode and autodetection charger mode. The USB host charger identification circuit allows a host USB port to support USB chargers with shorted DP/DM detection and to provide support for Apple-compliant devices using a resistor bias on USB data lines. When an Apple-compliant device is attached to the port in autodetection charger mode, the devices supply the voltage to the DP and DM lines from the internal resistor-divider. If a USB Revision 1.2-compliant device is attached, the devices short DP and DM to allow correct charger detection. The MAX14566BE features an additional digital input (CB1) to allow forced charger mode.
These devices have enhanced, high electrostatic dis-charge (ESD) protection on the DP and DM inputs up to Q15kV Human Body Model (HBM). All the devices are available in an 8-pin (2mm x 2mm) TDFN package, and are specified over the -40NC to +85NC extended temperature range.
FeaturesS Hi-Speed USB Switching
S Low 4.0pF (typ) On-Capacitance
S Low 4.0I (typ) On-Resistance
S Ultra-Low 0.1I (typ) On-Resistance Flatness
S +2.8V to +5.5V Supply Range
S Ultra-Low 3µA (typ) Supply Current
S Automatic Current-Limit Switch Control
S Automatic USB Charger Identification Circuit
S ±15kV High ESD HBM Protection On DP/DM
S 2mm x 2mm, 8-Pin TDFN Package
S -40NC to +85NC Operating Temperature Range
ApplicationsLaptops
Netbooks
Universal Charger including iPodM/iPhoneM Chargers
Ordering Information/Selector Guide
Note: All devices are specified over the -40°C to +85°C oper-ating temperature range.+Denotes a lead(Pb)-free/RoHS-compliant package.*EP = Exposed pad.
Typical Operating Circuit
iPhone and iPod are registered trademarks of Apple, Inc.
EVALUATION KIT
AVAILABLE
MAX14566E
DMTDM D-
DPTDP D+
LAPTOP CHIPSET VBUS
GND
USBTRANSCEIVER
STANDBY CB
CEN
USBA CONNECTOR
OVERCURRENT PROTECTOR
CEN
Li+BATTERY
EXTERNALPOWER SUPPLY
5V SWITCHINGPOWER SUPPLY
USB A APPLE DOCKCONNECTOR
APPLEDOCK
iPodOR iPhone
USB A MICRO B MICRO-USBCONNECTOR
PHONE OR MP3PLAYER
PARTPIN-PACKAGE
CLS CONTROL
TOP MARK
MAX14566EETA+ 8 TDFN-EP* CEN ADJ
MAX14566AEETA+ 8 TDFN-EP* CEN ADK
MAX14566BEETA+ 8 TDFN-EP* — BMR
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USB Host Charger Identification Analog Switches
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Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)VCC, TDP, TDM, CB, DP, DM, CEN/CEN, CB1....-0.3V to +6.0VContinuous Current into any Terminal .............................Q30mAContinuous Power Dissipation (TA = +70NC) TDFN (derate 11.9mW/NC above +70NC) ....................954mW
Operating Temperature Range .......................... -40NC to +85NCJunction Temperature .....................................................+150NCStorage Temperature Range ............................ -65NC to +150NCLead Temperature (soldering, 10s) ................................+300NCSoldering Temperature (reflow) ......................................+260NC
ELECTRICAL CHARACTERISTICS(VCC = 2.8V to 5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 5.0V, TA = +25NC.) (Note 2)
ABSOLUTE MAXIMUM RATINGS
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
PACKAGE THERMAL CHARACTERISTICS (Note 1)TDFN Junction-to-Ambient Thermal Resistance (qJA) ...........84°C/W Junction-to-Case Thermal Resistance (qJC) ................37°C/W
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY (MAX14566E/MAX14566AE)
Power-Supply Range VCCVCB > VIH 2.8 5.5 V
VCB = 0V (Note 3) 4.75 5.25 V
Supply Current ICC
VCB = VCC VCC = 3.3V 2
FAVCC = 5.5V 7
VCB = 0VVCC = 4.75V 110 200
VCC = 5.25V 120 200
Supply Current Increase DICC 0 P VCB P VIL or VIH P VCB P VCC 2 FA
POWER SUPPLY (MAX14566BE)
Power-Supply Range VCC
VCB = VCC and VCB1 = VCC or VCB = VCC
and VCB1 = 0V or VCB = 0V and VCB1 = VCC
2.8 5.5 V
VCB = 0V and VCB1 = 0V (Note 3) 4.75 5.25 V
Supply Current ICC
VCB = VCC and VCB1 = VCC or VCB = VCC and VCB1 = 0V
VCC = 3.3V 2
mA
VCC = 5.5V 7
VCB = 0V and VCB1 = 0V
VCC = 4.75V 110 200
VCC = 5.25V 120 200
VCB = 0V and VCB1 = VCC
VCC = 5.0V for TYPVCC = 5.5V for MAX
3 7
Supply Current Increase DICC
VCB1 = 0V; 0 ≤ VCB ≤ VIL and VIH ≤ VCB ≤ VCC (Note 4)
1
mAVCB = 0V; 0 ≤ VCB1 ≤ VIL and VIH ≤ VCB1 ≤ VCC (Note 4)
1
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ELECTRICAL CHARACTERISTICS (continued)(VCC = 2.8V to 5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 5.0V, TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG SWITCH
Analog-Signal Range VDP,VDM 0 VCC V
On-Resistance TDP/TDM Switch RON VDP = VDM = 0V to VCC, IDP = IDM = 10mA 4.0 6.5 I
On-Resistance Match Between Channels TDP/TDM Switch
DRONVCC = 5.0V, VDP = VDM = 400mV, IDP = IDM = 10mA
0.1 I
On-Resistance Flatness TDP/TDM Switch
RFLATVCC = 5.0V, VDP = VDM = 0 to VCC, IDP = IDM = 10mA
0.1 I
On-Resistance of DP/DM Short RSHORT VCB = 0V, VDP = 1V, IDP = IDM = 10mA 40 70 I
Off-Leakage Current ITDPOFF, ITDMOFF
VCC = 3.6V, VDP = VDM = 0.3V to 3.3V, VTDP = VTDM = 3.3V to 0.3V, VCB = 0V
-250 +250 nA
On-Leakage Current IDPON,IDMON VCC = 3.6V, VDP = VDM = 3.3V to 0.3V, VCB = VCC
-250 +250 nA
DYNAMIC PERFORMANCE
Turn-On Time tONVTDP or VTDM = 1.5V, RL = 300I, CL = 35pF, Figure 1
20 100 Fs
Turn-Off Time tOFFVTDP or VTDM = 1.5V, RL = 300I, CL = 35pF, Figure 1
1 5 Fs
TDP, TDM Switch Propagation Delay
tPLH, tPHL RL = RS = 50I 60 ps
Output Skew tSK(O)
Skew between DP and DM when connected to TDP and TDM, RL = RS = 50I, Figure 2
40 ps
TDP, TDM Off-Capacitance COFF f = 1MHz 2.0 pF
DP, DM On-Capacitance (Connected to TDP, TDM)
CON f = 240MHz 4.0 5.5 pF
-3dB Bandwidth BW RL = RS = 50I (Note 4) 1000 MHz
Off-Isolation VISOVTDP, VDP = 0dBm, RL = RS = 50I, f = 250MHz, Figure 3 (Note 4)
-20 dB
Crosstalk VCTVTDP, VDP = 0dBm, RL = RS = 50I, f = 250MHz, Figure 3 (Note 4)
-25 dB
INTERNAL RESISTORS
DP/DM Short Pulldown RPD 335 500 710 kI
RP1/RP2 Ratio RTRP 1.485 1.5 1.515 Ratio
RP1 + RP2 Resistance RRP 95 126 176 kI
RM1/RM2 Ratio RTRM 0.843 0.85 0.865 Ratio
RM1 + RM2 Resistance RRM 70 94 132 kI
COMPARATORS
DM1 Comparator Threshold VDM1F DM falling 45 46 47 %VCC
DM1 Comparator Hysteresis 1 %
DM2 Comparator Threshold VDM2F DM falling 6.31 7 7.6 %VCC
DM2 Comparator Hysteresis 1 %
DP Comparator Threshold VDPR DP rising 45 46 47 %VCC
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ELECTRICAL CHARACTERISTICS (continued)(VCC = 2.8V to 5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 5.0V, TA = +25NC.) (Note 2)
Note 2: All units are 100% production tested at TA = +25NC. Specifications over temperature are guaranteed by design.Note 3: The part is operational from +2.8V to +5.5V. However, in order to have the valid Apple resistor-divider network, the VCC
supply must stay within the range of +4.75V to +5.25V.Note 4: Guaranteed by design.
Test Circuits/Timing Diagrams
Figure 1. Switching Time
tr < 5nstf < 5ns
50%VIL
LOGICINPUT
RL
D_
GND
CB
VIN
VIH
tOFF
0V
TD_
0.9 x V0UT 0.9 x VOUT
tON
VOUT
SWITCHOUTPUT
LOGICINPUT
IN DEPENDS ON SWITCH CONFIGURATION;INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
VCC
CL
VCC
VOUT
MAX14566EMAX14566AEMAX14566BE
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
VOUT = VINRL
RL + RON
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DP Comparator Hysteresis 1 %
LOGIC INPUT (CB, CB1)
CB/CB1 Input Logic-High VIH 1.4 V
CB/CB1 Input Logic-Low VIL 0.4 V
CB/CB1 Input Leakage Current IINVCC = 5.5V, 0V P VCB P VIL orVIH P VCB P VCC
-1 +1 FA
CEN/CEN OUTPUTS
VBUS Toggle Time (MAX14566E/MAX14566AE)
tVBT CB = logic 0 to logic 1 or logic 1 to logic 0 0.5 1 2 s
CEN Output Logic-High VoltageCB = logic 0 to logic 1, ISOURCE = 2mA (MAX14566E only)
VCC - 0.4
V
CEN Output Leakage CurrentVCC = 5.5V, VCEN = 0V, CEN deasserted (MAX14566E only)
1 FA
CEN Output Logic-Low VoltageCB = logic 0 to logic 1, ISINK = 2mA (MAX14566AE only)
0.4 V
CEN Output Leakage CurrentVCC = VCEN = 5.5V, CEN deasserted (MAX14566AE only)
1 FA
ESD PROTECTION
ESD Protection Level(DP and DM Only)
VESD HBM Q15 kV
ESD Protection Level(All Other Pins)
VESD HBM Q2 kV
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Test Circuits/Timing Diagrams (continued)
Figure 2. Output Signal Skew
IN+
IN-
CB
VCC
OUT+
OUT-
VIN+
VIN-
VOUT+
VOUT-
TDP
TDM
DP
DM
0V
V+
0V
V+
0V
V+
0V
V+
tPLHX tPHLX
tINRISE
tOUTRISE tOUTFALL
RISE-TIME PROPAGATION DELAY = tPLHX OR tPLHY
FALL-TIME PROPAGATION DELAY = tPHLX OR tPHLYtSK(O) = |tPLHX - tPLHY| OR |tPHLX - tPHLY|tSK(P) = |tPLHX - tPHLX| OR |tPLHY - tPHLY|
50%
50%
50%
50%
90%
10% 10%
90%
10% 10%
RL
RL
50%
50%
50%
50%
tINFALL
90%
90%
tPHLY tPLHY
RS
RS
MAX14566EMAX14566AEMAX14566BE
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Typical Operating Characteristics(VCC = 5V, TA = +25NC, unless otherwise noted.)
Test Circuits/Timing Diagrams (continued)
Figure 3. Off-Isolation and Crosstalk
TDP/TDM ON-RESISTANCEvs. SUPPLY VOLTAGE
MAX
1456
6E to
c01
VTDP (V)
5.55.04.0 4.51.0 1.5 2.0 2.5 3.0 3.50.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
00 6.0
R ON
(I)
VCC = 2.8V
VCC = 5.5V
3.53.02.0 2.51.0 1.50.50 4.0
ON-RESISTANCE vs. VTDP/TDM
MAX
1456
6E to
c02
0.5
1.0
1.5
2.0
2.5
TA = -40°C
TA = +25°C
TA = +85°C
3.0
3.5
4.0
4.5
5.0VCC = 3.3V
0
VTDP/TDM (V)
R ON
(I)
DP/DM SHORT ON-RESISTANCEvs. SUPPLY VOLTAGE
MAX
1456
6E to
c03
VDP (V)
R ON
(I)
5.55.04.0 4.51.0 1.5 2.0 2.5 3.0 3.50.5
5
10
15
20
25
30
35
40
45VCC = 2.8V
VCC = 5.5V
50
00 6.0
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN TD_ AND "OFF" D_ TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
VOUT
CB VCC
VCC
TDP
DP*
VIN
OFF-ISOLATION = 20log VOUT
VIN
CROSSTALK = 20log VOUT
VIN
NETWORKANALYZER
50Ω
50Ω 50Ω
50Ω
MEAS REF
0V OR VCC
*FOR CROSSTALK THIS PIN IS DM.
MAX14566EMAX14566AEMAX14566BE
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Typical Operating Characteristics (continued)(VCC = 5V, TA = +25NC, unless otherwise noted.)
TDP/DP LEAKAGE CURRENTvs. TEMPERATURE
MAX
1456
6E to
c04
TEMPERATURE (°C)
LEAK
AGE
CURR
ENT
(nA)
756030 45-15 0 15-30
5
10
15
20
25
30
35
40
45
0-45 90
VCC = 3.6V, VTDP = 3.3V
ON-LEAKAGE
OFF-LEAKAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX
1456
6E to
c05
VCC (V)
I CC
(µA)
5.24.94.64.34.03.73.43.1
1
2
3
4
5
6
02.8 5.5
CB = VCCTA = -40°C
TA = +25°C
TA = +85°C
SUPPLY CURRENTvs. LOGIC LEVEL
MAX
1456
6E to
c06
LOGIC LEVEL (V)
I CC
(µA)
3.02.70.3 0.6 0.9 1.5 1.8 2.11.2 2.4
20
40
60
80
100
120
140VCC = 5.5V
160
00 3.3
TURN-ON/TURN-OFF TIMEvs. SUPPLY VOLTAGE
MAX
1456
6E to
c07
VCC (V)
TURN
-ON/
TURN
-OFF
TIM
E (µ
s)
5.55.04.0 4.53.0 3.52.5
2
468
1012
tON
tOFF
141618
202224
02.0 6.0
VCC (V)
LOGI
C-IN
PUT
THRE
SHOL
D (V
)
5.24.94.3 4.63.4 3.7 4.03.1
LOGIC-INPUT THRESHOLDvs. SUPPLY VOLTAGE
MAX
1456
6E to
c08
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1 CB_RISING
CB_FALLING
1.2
02.8 5.5
AUTODETECTION MODEMAX14566E toc09
DM 1V/div
CB2V/div
DP1V/div
10µs/div
VCC = 5.0V, DP/DM HIGH IMPEDANCE,CB LOGIC 1 TO LOGIC 0
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Typical Operating Characteristics (continued)(VCC = 5V, TA = +25NC, unless otherwise noted.)
AUTODETECTION MODEMAX14566E toc10
0V
0V
1ms/div
VCC = 5.0V, DP/DM HIGH IMPEDANCE TO0.5V AT DM
DM 500mV/div
DP500mV/div
AUTO RESETMAX14566E toc11
CB2V/div
0V
0V
2s/div
MAX14566E
CEN2V/div
AUTO RESETMAX14566E toc12
CB500mV/div
0V
0V
2s/div
MAX14566AE
CEN2V/div
MAX
1456
6E to
c13
TIME (x 10n - 9)s
DIFF
EREN
TIAL
SIG
NAL
(V)
1.81.61.2 1.40.4 0.6 0.8 1.00.2
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 2.0
HI-SPEED USB TRANSMITTEMPLATE
USB EYE DIAGRAM
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Pin Configuration
Pin Description
1 3 4
8 6 5
CB TDP VCC
MAX14566EMAX14566AE
2
7
TDM
CEN(CEN)
DP GNDDM
TDFN(2mm × 2mm)
TOP VIEW
( ) FOR MAX14566AE ONLY *CONNECT EP TO GND.
*EP
1 3 4
8 6 5
CB TDP VCC
MAX14566BE
2
7
TDM
CB1 DP GNDDM
TDFN(2mm × 2mm)
TOP VIEW
*EP
PINNAME FUNCTION
MAX14566E MAX14566AE MAX14566BE
— 1 — CENnMOSFET Open-Drain Output, Current-Limit Switch (CLS) Control Output. If CB changes from logic 0 to logic 1 or from logic 1 to logic 0, CEN is low for 1s (typ).
1 — — CENActive-Low pMOSFET Open-Drain Output, Current-Limit Switch (CLS) Control Output. If CB changes from logic 0 to logic 1 or logic 1 to logic 0, CEN is high for 1s (typ).
— — 1 CB1 Switch Control Bit. See Table 2.
2 2 2 DM USB Connector D- Connection
3 3 3 DP USB Connector D+ Connection
4 4 4 GND Ground
5 5 5 VCCPower Supply. Connect a 0.1FF capacitor between VCC and GND as close as possible to the device.
6 6 6 TDP Host USB Transceiver D+ Connection
7 7 7 TDM Host USB Transceiver D- Connection
8 8 8 CB
Switch Control Bit. See Table 1.CB = logic 0, charger modeCB = logic 1 (PM), pass-through mode active, DP/DM connected to TDP/TDM
— — — EPExposed Pad. Connect EP to ground. Do not use EP as the only ground connection.
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Detailed DescriptionThe MAX14566E/MAX14566AE/MAX14566BE are Hi-Speed USB analog switches that support USB hosts to identify the USB port as a charger port when the USB host is in a low-power mode and cannot enumerate USB devices. These devices feature high-performance Hi-Speed USB switches with low 4pF (typ) on-capacitance and low 4I (typ) on-resistance. DP and DM can handle signals between 0V and 6V with any supply voltage.
Resistor-DividersAll the devices feature an internal resistor-divider for biasing data lines to provide support for Apple-compliant devices. When these devices are not operated with the resistor-divider, they disconnect the resistor-dividers
from the supply voltage to minimize supply current requirements. The resistor-dividers are not connected in pass-through mode.
Switch ControlThe MAX14566E/MAX14566AE feature a single digital input, CB, for mode selection (Table 1). Connect CB to a logic-level low voltage for autodetection charger mode (AM). See the Autodetection section for more informa-tion. Connect CB to a logic-level high voltage for normal high-speed pass-through mode (PM). The MAX14566BE features dual digital inputs, CB and CB1, for mode selec-tion (Table 2). Connect CB to a logic-level high for nor-mal high-speed pass-through mode (PM). Connect CB to a logic-level low for different charger-mode selection
Functional Diagram
RM1
500kIRM2
DP
CONTROL LOGIC
ONE SHOT
RP1
RP2
DP
TDP
TDM
CB1*
DM
CB
CEN(CEN)
VBIAS
0.46VCC
VCC
VCC
GND
VCC
DM10.46VCC
DM20.07VCC
MAX14566EMAX14566AEMAX14566BE
1s
( ) FOR MAX14566AE ONLY*FOR MAX14566BE ONLY
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USB Host Charger Identification Analog Switches
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with CB1. Connect CB1 to a logic-level low for auto mode (AM) or connect CB1 to a logic-level high for forced dedicated-charger mode (FM).
AutodetectionAll the devices feature autodetection charger mode for dedicated chargers and USB masters. CB must be set low to activate autodetection charger mode.
In autodetection charger mode, the MAX14566E moni-tors the voltages at DM and DP to determine the type of the device attached. If the voltage at DM is +2.3V (typ) or higher and the voltage at DP is +2.3V (typ) or lower, the voltage stays unchanged.
If the voltage at DM is forced below the +2.3V (typ) threshold, the internal switch disconnects DM and DP
from the resistor-divider and DP and DM are shorted together for dedicated charging mode.
If the voltage at DP is forced higher than the +2.3V (typ) threshold, the internal switch disconnects DM and DP from the resistor-divider and DP and DM are shorted together for dedicated charging mode.
Once the charging voltage is removed, the short between DP and DM is disconnected for normal operation.
Automatic Peripheral ResetThe MAX14566E/MAX14566AE feature automatic current-limit switch control output. This feature resets the peripher-al connected to VBUS in the event the USB host switches to or from standby mode. CEN/CEN provide a 1s (typ) pulse on the rising or falling edge of CB (Figures 4, 5, and 6).
Table 1. Digital Input State (MAX14566E/MAX14566AE)
Table 2. Digital Input State (MAX14566BE)
Figure 4. MAX14566E Peripheral Reset Timing Diagram
X = Don't care.
ATTACH
CEN
VBUS
CB
5V
AM
PMPM
AM
USB PERIPHERAL
STANDBY
tVBT
USB CONNECTION
CHARGING CURRENT
1000mA 500mA 1000mA 500mA 1000mA
CB MODE DP/DM COMMENT INTERNAL RESISTOR-DIVIDER
0 AM Autodetection Circuit Active Auto Mode Connected
1 PM Connected to TDP/TDM USB Traffic Active Not Connected
CB CB1 MODE STATUS
0 0 AM Auto Mode
0 1 FM Forced Dedicated-Charger Mode: DP/DM Shorted
1 X PM Pass-Through (USB) Mode: Connect DP/DM to TDP/TDM
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Figure 5. MAX14566E Peripheral Reset Applications Diagram
Figure 6. MAX14566AE Peripheral Reset Timing Diagram
MAX14566E
USBTRANSCEIVER
CURRENT-LIMITSWITCH
CLS EN
SYSTEM CONTROL
STANDBYCB
CEN
+5V POWERSUPPLY
EN
VCC
TDM TDP 0.1µF
10kI
150µF
GND
USBCONNECTION
D+DP
GND
VCC
D-
VBUS
VBUS
DM
ATTACH
CEN
VBUS
CB
5V
AM
PMPM
AM
USB PERIPHERAL
STANDBY
tVBT
USB CONNECTION
CHARGING CURRENT
1000mA 500mA 1000mA 500mA 1000mA
MA
X1
45
66
E/M
AX
14
56
6A
E/M
AX
14
56
6B
E
USB Host Charger Identification Analog Switches
13
Bus Voltage DischargeThe MAX14566AE automatic current-limit switch control output can be used to discharge the VBUS during VBUS reset. When the system controls the current-limit switch for VBUS toggle, the output capacitor can be discharged slowly depending upon the load. If fast discharge of the VBUS capacitor is desired, the CEN output can be used to achieve the fast discharge as shown in Figure 7.
Data Contact DetectAll the devices support USB devices that require detect-ing the USB data lines prior to charging. When a USB Revision 1.2-compliant device is attached, the USB data lines DP and DM are shorted together. The short remains until it is detected by the USB device. This feature guar-antees appropriate charger detection if a USB Revision 1.2-compliant device is attached. The autodetection charger mode is activated after the data contact detect
is established. CB must be set low to activate data con-tact detect.
ESD Test ConditionsESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results.
Extended ESD Protection (Human Body Model)
ESD-protection structures are incorporated on all pins to protect against electrostatic discharges up to Q2kV (HBM) encountered during handling and assembly. DP and DM are further protected against ESD up to Q15kV (HBM) without damage. The ESD structures withstand high ESD both in normal operation and when the device is powered down. After an ESD event, the device contin-ues to function without latchup (Figure 8).
Figure 7. MAX14566AE VBUS Discharge Circuit
MAX14566AE
USBTRANSCEIVER
CURRENT-LIMITSWITCH
CLS EN
SYSTEM CONTROL
STANDBYCB
CEN
+5V POWERSUPPLY
EN
VCC
TDM TDP 0.1µF
10kI
1kI
150µF
GND
USBCONNECTION
D+DP
GND
VCC
D-
VBUS
VBUS
DM
MA
X1
45
66
E/M
AX
14
56
6A
E/M
AX
14
56
6B
E
USB Host Charger Identification Analog Switches
14
Chip InformationPROCESS: BiCMOS
Package InformationFor the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Figure 8a. Human Body ESD Test Model Figure 8b. Human Body Current Waveform
Typical Application Circuit (MAX14566BE)
CHARGE-CURRENT-LIMIT RESISTOR
DISCHARGERESISTANCE
STORAGECAPACITOR
CS100pF
RC1MΩ
RD1.5kΩ
HIGH- VOLTAGE
DCSOURCE
DEVICEUNDERTEST
100%
36.8%
tRL
TIME
tDL
PEAK-TO-PEAK RINGING(NOT DRAWN TO SCALE)
Ir
00
IPEAK (AMPS)
90%
10%
MAX14566BE
USBTRANSCEIVER
CURRENT-LIMITSWITCH
AM/FMSYSTEM CONTROL
PMCB
CB1
+5V POWERSUPPLY
EN
VCC
TDM TDP
TDM TDP
0.1µF
150µF
GND
USBCONNECTION
D+DP
GND
VCC
D-
VBUS
VBUS
DM
EN
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
8 TDFN-EP T822+1 21-0168 90-0064
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 15
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
MA
X1
45
66
E/M
AX
14
56
6A
E/M
AX
14
56
6B
E
USB Host Charger Identification Analog Switches
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 10/10 Initial release —
1 3/11 Changed the USB Battery Charging Specification Revision 1.1 to Revision 1.2 1, 13