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UNIVERSITY OF CALIFORNIA
Los Angeles
Comparison of Digital Offset
Compensation in Comparators
A thesis submitted in partial satisfaction
of the requirements for the degree Master of Science
in Electrical Engineering
by
Koon Lun Jackie Wong
2002
ii
The thesis of Koon Lun Jackie Wong is approved.
________________________________ Behzad Razavi
________________________________ Ingrid Verbauwhede
________________________________ C.-K. Ken Yang, Committee Chair
University of California, Los Angeles
2002
iii
Table of Contents
COMPARISON OF DIGITAL OFFSET COMPENSATION IN COMPARATORS1
CHAPTER 1 INTRODUCTION ..................................................................................... 1 1.1 GENERAL PURPOSES OF COMPARATORS..................................................................... 1 1.2 REQUIREMENTS ON COMPARATORS............................................................................ 1 1.3 INTRODUCTION TO OFFSET COMPENSATION............................................................... 6
CHAPTER 2 CORE COMPARATOR DESIGN........................................................... 9 2.1 ACCURACY............................................................................................................... 10
2.1.1 Device Mismatch in Differential Pair .............................................................. 10 2.1.2 Total Input Referred Offset of Comparator...................................................... 12
2.2 SUPPLY SENSITIVITY ................................................................................................ 24 2.2.1 Supply Sensitivity due to each transistor.......................................................... 24 2.2.2 Overall Supply Sensitivity of Core Comparator .............................................. 26
2.3 SPEED....................................................................................................................... 27 2.3.1 Evaluation Phase.............................................................................................. 27 2.3.2 Reset Phase ...................................................................................................... 34
2.4 INPUT CAPACITANCE ................................................................................................ 40 2.5 POWER CONSUMPTION ............................................................................................. 41 2.6 DESIGN OF NEXT STAGE (SR LATCH)....................................................................... 41
CHAPTER 3 DIGITAL OFFSET COMPENSATION ............................................... 43 3.1 FOUR DIFFERENT ARCHITECTURES .......................................................................... 44
3.1.1 Architecture Comp1 ......................................................................................... 44 3.1.2 Architecture Comp2 ......................................................................................... 45 3.1.3 Architecture Comp3 ......................................................................................... 46 3.1.4 Architecture Comp4 ......................................................................................... 47
3.2 CHARACTERISTICS OF DIGITAL OFFSET COMPENSATION.......................................... 48 3.2.1 Offset Magnitude of Digital Compensation ..................................................... 48 3.2.2 Linearity of Digital Offset Compensation ........................................................ 52 3.2.3 Worst-Case Overall Offset after compensation ............................................... 55
3.3 SUPPLY SENSITIVITY ................................................................................................ 56 3.4 SPEED....................................................................................................................... 59
3.4.1 Comparison on Speed of Different Architectures ............................................ 60 3.4.2 Speed Penalty of Digital Offset Compensation ................................................ 63 3.4.3 Comparison on Linear and Non-linear scaling ............................................... 65
3.5 INPUT CAPACITANCE ................................................................................................ 67 3.6 POWER CONSUMPTION ............................................................................................. 67
3.6.1 Power of Comparators ..................................................................................... 67 3.6.2 Power of Clocking............................................................................................ 70
iv
3.6.3 Total Power ...................................................................................................... 71 3.7 QUICK SUMMARY OF COMPARISON.......................................................................... 73
CHAPTER 4 CIRCUIT PERFORMANCE ................................................................. 74 4.1 ACCURACY............................................................................................................... 74
4.1.1 Measured Internal Offset Due to Device Mismatches ..................................... 74 4.1.2 Measured Digital Offset Compensation........................................................... 77 4.1.3 Linearity ........................................................................................................... 82 4.1.4 Worst-case Overall Offset ................................................................................ 85
CHAPTER 5 APPLICATIONS OF COMPARATORS.............................................. 89 5.1 APPLICATION OF COMPARATORS ON MULTIPHASE FLASH ADC .............................. 89
CHAPTER 6 CONCLUSION ........................................................................................ 93
v
List of Figures
Figure 1 Ideal input/output characteristic of a comparator ................................................. 2 Figure 2 Positive feedback realization ................................................................................ 2 Figure 3 Block diagram of flash ADC architecture ............................................................ 4 Figure 4 Schematic of (a) an amplifier (b) a comparator.................................................... 5 Figure 5 A comparator with analog offset compensation ................................................... 6 Figure 6 Timing Diagrams of φ1, φ2, φ3, VX, and VY............................................................ 7 Figure 7 Core Comparator................................................................................................. 10 Figure 8 Model of Device Mismatch in Differential Pair ................................................. 12 Figure 9 Core comparator model for offset calculations................................................... 12 Figure 10 Current factor mismatch of M1 ......................................................................... 14 Figure 11 common mode analyses of M1,2........................................................................ 15 Figure 12 Threshold mismatch of M3 ............................................................................... 17 Figure 13 common mode analyses for M3 ........................................................................ 18 Figure 14 Current factor mismatch of M3 ......................................................................... 20 Figure 15 Input referred offset voltage due to each transistor .......................................... 23 Figure 16 Supply Sensitivity on Offset due to ∆β1, ∆β2, and ∆Vth2 .................................. 25 Figure 17 Overall Supply Sensitivity on Offset ................................................................ 27 Figure 18 Reset Response of sim2, sim3, sim10, and sim11 ............................................ 38 Figure 19 Simplified SR Latch.......................................................................................... 42 Figure 20 Schematic of Comp1......................................................................................... 44 Figure 21 Schematic of Comp2......................................................................................... 45 Figure 22 Schematic of Comp3......................................................................................... 46 Figure 23 Schematic of Comp4......................................................................................... 47 Figure 24 Digital Offset of Comp1 ................................................................................... 50 Figure 25 Digital Offset of Comp2 ................................................................................... 50 Figure 26 Digital Offset of Comp3 ................................................................................... 51 Figure 27 Digital Offset of Comp4 ................................................................................... 51 Figure 28 Digital Offset DNL of Comp1 .......................................................................... 53 Figure 29 Digital Offset DNL of Comp2 .......................................................................... 53 Figure 30 Digital Offset DNL of Comp3 .......................................................................... 54 Figure 31 Digital Offset DNL of Comp4 .......................................................................... 54 Figure 32 Worst-case overall offset .................................................................................. 56 Figure 33 Supply Sensitivity on Offset of Comp1............................................................ 57 Figure 34 Supply Sensitivity on Offset of Comp2............................................................ 57 Figure 35 Supply Sensitivity on Offset of Comp3............................................................ 57 Figure 36 Supply Sensitivity on Offset of Comp4............................................................ 58 Figure 37 Illustration of input transconductance loss ....................................................... 63 Figure 38 Schematic of Comp1 with 3-bit linear scaling.................................................. 65 Figure 39 Power Consumptions with Digital Offset Compensation Off .......................... 69 Figure 40 Power Consumptions with Digital Offset Compensation On........................... 69
vi
Figure 41 Total Power Consumption with Digital Compensation Off ............................. 71 Figure 42 Total Power Consumption with Digital Compensation On.............................. 72 Figure 43 Measured Internal Offset of Comp1 ................................................................. 75 Figure 44 Measured Internal Offset of Comp2 ................................................................. 75 Figure 45 Measured Internal Offset of Comp3 ................................................................. 76 Figure 46 Measured Internal Offset of Comp4 ................................................................. 76 Figure 47 Measured Digital Offset of Comp1 .................................................................. 79 Figure 48 Measured Digital Offset of Comp2 .................................................................. 79 Figure 49 Measured Digital Offset of Comp3 .................................................................. 80 Figure 50 Measured Digital Offset of Comp4 .................................................................. 80 Figure 51 Measured DNL of Comp1 ................................................................................ 83 Figure 52 Measured DNL of Comp2 ................................................................................ 83 Figure 53 Measured DNL of Comp3 ................................................................................ 84 Figure 54 Measured DNL of Comp4 ................................................................................ 84 Figure 55 Measured Offset of Comp1 after Digital Compensation .................................. 86 Figure 56 Measured Offset of Comp2 after Digital Compensation .................................. 86 Figure 57 Measured Offset of Comp3 after Digital Compensation .................................. 87 Figure 58 Measured Offset of Comp4 after Digital Compensation .................................. 87 Figure 59 Comparison on worst-case offset...................................................................... 88 Figure 60 Block Diagram of Multiphase Flash ADC ....................................................... 89 Figure 61 Speed of 6-bit p-phase Flash ADC ................................................................... 92 List of Tables
Table 1 Simulation results on evaluation with varying comparator transistor size .......... 33 Table 2 Simulation results on reset device........................................................................ 37 Table 3 Evaluation and Reset with vary Vcm (see Table 1,Table 2 for term definition) . 39 Table 4 Power Consumption of Core Comparator............................................................ 41 Table 5 Worst-case Supply Sensitivity of Comp1 − Comp4 ............................................ 59 Table 6 Speed Comparisons with Digital Offset Compensation Off ................................ 60 Table 7 Speed Comparisons with Digital Offset Compensation On................................. 61 Table 8 Maximum Sampling rate of different architecture............................................... 62 Table 9 Speed Comparisons on linear and non-linear scaling of Comp1 ......................... 65 Table 10 Power of Clocking.............................................................................................. 70 Table 11 Performances Rating of Comparators ................................................................ 73
vii
ABSTRACT OF THE THESIS
Comparison of Digital Offset
Compensation in Comparators
by
Koon Lun Jackie Wong
Master of Science in Electrical Engineering
University of California, Los Angeles, 2002
Professor C.-K. Ken Yang, Chair
Digital offset compensation is an efficient technique for designing high speed, high
accuracy, low input capacitance, and low power comparators. Low input capacitance and
low power allow higher order of parallelism, while digital offset compensation allows
high accuracy. A 4-bit digital offset compensation can reduce 140mV input referred
offset due to device mismatches to 13mV. For comparison, four different architectures of
digital offset compensation are fabricated in 0.18µm 1.8V CMOS technology, and a set
of performance metrics for a comparator is developed to compare the tradeoffs between
these four architectures.
1
Comparison of Digital Offset Compensation in Comparators
Chapter 1 Introduction
1.1 General Purposes of Comparators
Modern integrated circuits (IC) design almost always involves strong well defined
digital signals; however, incoming data is often analog signals or corrupted digital signals,
which are caused by limited bandwidth of transmission line, noise coupling, capacitive
and inductive effects from the printed circuit board (PCB), chip package, wire bond, etc.
In order to convert the weak corrupted signals to full swing digital signals, a comparison
with a fixed reference value is performed. A comparator outputs a digital 0 if the signal is
below the reference or a digital 1 if the signal is above the reference.
Comparators are commonly found in modern IC design. Since most IC designs
are synchronous system, comparators are usually triggered by clock. Clocked
comparators are commonly found in Analog-to-Digital Converter (ADC) and based band
receivers. Moreover, since comparators have large voltage gain, they are often used as
sense amplifiers in SRAM and DRAM. Sometimes, in high performance circuits,
comparators are used as a storage element, for instance a latch.
1.2 Requirements on Comparators
In applications like flash ADC and over-sampled receiver, a comparator requires
high gain, high sampling rate, high accuracy, low power consumption, and low input
2
capacitance. In addition, comparators are required to be triggered by clock, if the systems
are synchronous. The requirements of comparators are discussed one by one below.
Figure 1 Ideal input/output characteristic of a comparator
The first requirement of a comparator is having high gain. An ideal comparator
has input/output characteristic as shown in Figure 1. In real implementation, high gain
amplifier is used to approximate this input/output characteristic. To achieve virtually
infinite gain, positive feedback is often employed in comparator design. A simple
realization of positive feedback system could be two back-to-back inverters, as shown in
Figure 2. The output (V1 – V2) of this circuit increases exponentially with time. This will
be discussed in detail in Chapter 2.
Figure 2 Positive feedback realization
The second requirement of a comparator is having high sampling rate. As
synchronous system is running faster and faster, we require clocked comparator to run at
a higher sampling rate as well. A common clocked architecture that can achieve high
sampling rate has two phases of operation: evaluation phase and reset phase. In
Vin1−Vin2
Vout
Vin1
Vin2
Vout
V1 V2
3
evaluation phase, positive feedback is enabled to achieve high gain. In reset phase,
positive feedback is disabled and the comparator clears its previous sample. For fast
operation, reset must be completed quickly and the positive feedback should be enabled
quickly and have short regeneration time constant.
The third requirement of a comparator is having high accuracy, for example ½
LSB of an ADC or minimum signal magnitude of a receiver. Errors that cause inaccuracy
usually are offsets, noise, and residual value from prior comparison. Offsets are often the
largest errors in comparator design. Offsets can be classified into systematic and random
offsets. Systematic offsets can be minimized by symmetric design and careful layout.
Random offsets are caused by device mismatches in layout, and the variance of mismatch
is inversely proportional to the area of devices size (W×L) [1]. Thus, to reduce random
offsets, we should make devices bigger. However, as modern CMOS technology scales
down for higher switching speeds and higher transistor density, offset requirements
become more and more difficult to fulfill. The second error that causes inaccuracy is
noise. Noise includes thermal noise, flicker noise, supply noise, and sampling noise.
Thermal noise is white Gaussian noise from resistors and transistors. Flicker noise is
often referred to 1/f noise of a transistor. Supply noise does not affect the output directly,
because comparator is a fully differential circuit. However, due to large device
mismatches, supply noise may momentarily change the input referred offset, and thus
degrade the accuracy. Sampling noise is caused by the fast transition of clock from reset
phase to evaluation phase. Fortunately, sampling noise is often negligible even with
4
sampling rates of several GSamples/s1. The third error that causes inaccuracy is the
residual value from prior comparison. During reset phase, the comparator clears the
previous data. However, if the reset is not completed before the next evaluation phase
comes, small residual charge on output will get amplified exponentially because of
positive feedback. The imbalanced output thus creates input referred offset, degrading the
comparator accuracy. Since the residual charge depends on the previous sample, this
error is sometimes called Inter-Symbol Interference (ISI).
Figure 3 Block diagram of flash ADC architecture
The forth requirement of a comparator is having low power consumption. The
power consumption of a comparator must be low because frequently a large number of
1 Analysis of sampling noise is not part of this research.
VFS
•
•
COMP
COMP
COMP
COMP
Vin
clk
2N
DEC
OD
ER
N Digital Output
5
comparators operating in parallel are used in a flash ADC architecture or in an over-
sampled receiver. A block diagram of a simple flash ADC is shown in Figure 3. The
basic concept of a flash ADC is to use 2N comparators to compare the input signal with
reference voltages that are generated by dividing the full scale voltage VFS by 2N resistors.
Decoder then converts the comparators output to binary code. Hence a N-bit flash ADC
requires 2N comparators. As a result, the power consumption of a flash ADC doubles as
the number of bits of resolution increases by one.
Figure 4 Schematic of (a) an amplifier (b) a comparator
The last requirement of a comparator is having low input capacitance since low
input capacitance limits the input bandwidth. Similar to power consumption, total input
capacitance of a N-bit flash ADC is simply 2N × input capacitance of a comparator. For a
typical amplifier (Figure 4a) and a typical comparator (Figure 4b), input capacitance is
directly proportional to the size of input devices M1,2. In favor of input capacitance, we
should use small input devices M1,2. However, in favor of offset, we should use big input
M1
M2
M4
VDD
Vb
Vin1 Vin2
M3
Vout1 Vout2
M1
M2
M4
VDD
Vin1 Vin2
Vout1 Vout2
M3
Rst
M5
(a) (b)
6
devices. This contradiction leads to direct tradeoffs between accuracy and input
bandwidth. Therefore, offset compensation is introduced to reduce input referred offset
while keeping input devices small.
1.3 Introduction to Offset Compensation
The ultimate goal of offset compensation in comparators is to reduce the input
referred offset. Offset compensation can be done in analog method or in digital method.
Figure 5 A comparator with analog offset compensation
Traditionally, analog offset compensation is used, and it utilizes capacitors to
store offsets. Figure 5 shows an example of comparator with analog offset compensation
[2]. The comparator has regenerative amplifier M1 – M4, reset S5 – S7, and sampling
network S1 – S4 and C1,C2. shows the timing diagram of φ1, φ2, φ3, and VX, VY.
M3
M1 M2
M4
S7 S6 S5
C2 C1
S2
S4
S1
S3
φ3
VDD
φ1 φ1 φ2 φ2
φ1 φ1
+Vout −Vout
+Vin
+Vref
−Vin
−Vref
Q P
X Y
7
Figure 6 Timing Diagrams of φ1, φ2, φ3, VX, and VY
The operation of this comparator is the following: 1) The comparator is in reset phase, φ1
= H, φ2 = L, φ3 = H, S3 – S7 are on. Nodes P and Q are charged to +Vref and –Vref
respectively, and the offset of the comparator is stored in C1 and C2. 2) At t1, φ1 switches
to low, S3 – S6 turn off, so reset ends. 3) At t2, φ2 switches to high, S1 and S2 turn on to
track the inputs. 4) At t3, φ3 switches to low, S7 turns off, and regeneration starts. In this
example, we decouple the relationship between input capacitance and offsets. During
tracking mode in step 3, inputs see C1,2 in series with gates of M1,2, which results a
capacitance as small as gate capacitance of M1,2. Meanwhile, offset of the comparator is
given in [2]:
121
;7
71
−=∆+=
Rg
RgAV
AV
VmP
mNd
d
OSOS ,where VOS1 is the input-referred offset without
offset compensation, Ad is the differential voltage gain form the gates of M1 and M2 to
their drains, and ∆V is the offset due to charge injection mismatch between S5 and S6. gmN
and gmP are the NMOS and PMOS transconductance respectively, and R7 is the small-
signal on-resistance of S7. One potential problem for this architecture is that it may
t1 t2 t3 time
φ1
φ2
φ3
VX, VY
8
require large C1,2 to reduce the charge injection mismatch between S5 and S6. Large C1
and C2 increase the settling time during reset and thus slow down the operating frequency.
Generally analog offset compensation requires a capacitor to store the offset in every
cycle, so the comparator is in closed loop in around half a cycle. The maximum speed of
a comparator is eventually limited by the closed loop response. This restriction is much
more relaxed in digital offset compensation.
In digital offset compensation, offsets of a comparator can be tuned by changing
the digital inputs. Offsets are then stored in static memory when the system is initialized.
Hence, the comparator can remain in open loop most of the time, and thus its inherent
maximum speed can possibly be achieved.
This project focuses on digital offset compensation techniques and how they
affect the other requirements of gain, sampling rate, etc. Four different digital offset
compensation architectures are compared. Chapter 2 begins by discussing the design
issues of a core comparator. This core comparator will also be the baseline to which each
of compensation technique is compared for the penalty of inserting digital compensation.
Comparisons on digital offset compensation in chapter 3 will be based on performance
parameters and terminology presented in chapter 2. A test chip is fabricated in 0.18um
CMOS technology, and measured results will be given in chapter 4. Applications of
comparators will be discussed in chapter 5.
9
Chapter 2 Core Comparator Design
This project starts with a basic design of comparators. While there are many
architectures, we chose the comparator as shown in Figure 7 for its power efficiency [3].
This comparator has two operation modes, evaluation phase and reset phase. In
evaluation phase, clk is logical high. Current source Mclk turns on, and the input devices
M1,2 sense the differential input. The differential current of M1,2 imbalances the back-to-
back inverters, which form a positive feedback system. The imbalance charge on Vout1,
Vout2 is then regenerated to full swing. In reset phase, Mclk turns off and all RST1-6 turn on.
The reset devices RST1-6 eliminate all imbalance charge, so the previous data is cleared.
At this time, the comparator goes back to initial state and is ready to amplify the signal
when evaluation phase comes again.
Four digital offset compensation techniques are explored based on the same basic
comparator structure. Then we can examine not only tradeoffs among different
compensation architectures but also tradeoffs between with and without digital offset
compensation. For each compensation architecture, we base our comparison on the same
set of performance metric: accuracy, supply sensitivity, speed, input capacitance, and
power. This chapter looks at each of these metrics for the core comparator. A brief
discussion on SR latch, which receives the output of comparator and provides constant
logical output over one cycle, will be given at the end of this chapter.
10
Figure 7 Core Comparator
2.1 Accuracy
A very important requirement of a comparator is small input referred offset
voltage. Any input offset voltage in comparator will directly add on the signal; as a result,
the accuracy of the comparator will be decreased. Offsets can be systematic or random.
Systematic offset can be minimized by differentially symmetric design and careful layout.
Random offset arises if there are device mismatches. In this section, we will describe the
model for device mismatch in differential pair and total input referred offset of the
comparator.
2.1.1 Device Mismatch in Differential Pair
Matching properties of CMOS transistor are categorized into threshold mismatch,
RST2 42
M5 42
VDD
RST142
RST5 42
RST6 42
M642
M3 42
M442
RST442
RST3 42
M1 82
M282
Mclk 162
Vout1 Vout2
Vin1 Vin2
clk
clk clk
clk
invbot1 invbot2
11
∆Vth, and current factor mismatch, ∆β, according to [1]. The magnitude of these two
quantities can be approximated for a give gate oxide thickness and transistor size. For
instance, in 0.18µm technology, oxide thickness is around 4nm. In our comparator design,
drawn size of input transistor is W/L = 8λ/2λ = 0.96µm/0.24µm. Note that effective
channel length for the drawn length of 0.24µm is 0.18µm. The standard deviation of the
random mismatches can be approximated by [1],
eff
Vthth WL
AV
22 )( =σ
effWLA2
2
2 )( β
ββσ = ,
where σ(Vth) and σ(β) are standard deviation of ∆Vth and ∆β respectively, AVth2 and Aβ
2
are area proportionality constant which could be found from a lookup graph for a given
oxide thickness. It is found that AVth = 4mVµm, Aβ = 1%µm, σ(Vth) = 9.62mV and σ(β)
β
= 2.41%. Adapting to this methodology and assuming worst-case conditions, we will
model the threshold mismatch as an ideal voltage source on transistor gate with
magnitude ∆Vth = 6σ(Vth), and current factor mismatch as error in channel width, ∆W W =
6 σ(β)
β . This simple model is illustrated in Figure 8.
12
Figure 8 Model of Device Mismatch in Differential Pair
2.1.2 Total Input Referred Offset of Comparator
With a mismatch model for a differential pair, we can replace all pairs in our core
comparator with this model to find the total input referred offset. In order to obtain the
worst-case offset, the placements of the voltage sources and scaled transistors are
specially chosen. As shown in Figure 8, transistors labeled with “OS” are replaced by the
mismatch model. For clarity, all reset devices RST1-6 are not shown.
Figure 9 Core comparator model for offset calculations
The mismatches of three differential pairs contribute offset of the comparator. In
this section, I will discuss the affects of each offset source carefully, and simulation
W−∆WL
WL
+ − ∆Vth
Vin1 Vin2
VDD
M1(OS) W12L
M2 W12L
Mclk Wclk
L
M3(OS) W36L
M4 W36L
invbot1 invbot2
M5 W36L
(OS)M6 W36L
Vout1 Vout2
Vin1 Vin2
clk
13
results are presented at the end of this section to confirm the theoretical results.
Offset due to threshold mismatch of M1, ∆Vth1:
∆Vth1 is modeled as a voltage source on the gate of transistor M1. Since M1 is the
input device of the comparator, the input referred offset voltage due to threshold
mismatch of M1 is just ∆Vth1 itself. This magnitude is always constant under any bias
conditions.
Offset due to current factor mismatch of M1, ∆β1:
∆β1 is modeled as a channel width mismatch ∆W, i.e. ∆ββ =
∆WW To calculate the
input referred offset due to ∆W, I will calculate the differential current that ∆W generates,
as illustrated in Figure 10a, and then compare the current with that of generated by
equivalent ideal voltage source at the input, as shown in Figure 10b.
14
Figure 10 Current factor mismatch of M1
Before analyzing two configurations, it is important to know that transistors M1,2 are in
saturation because in the beginning of evaluation mode node invbot1, invbot2 are
precharged to VDD. However, Mclk is in triode region because Vgs,Mclk = VDD, Vds,Mclk =
Vcm − Vgs1,2, which could be quite low. Analyzing Figure 10a, we could find:
211
211
212
211
211
)(21
)(21)(
21
)(121)(
21
thgsndiff
thgsnthgsoxn
thgsnthgsoxn
VVWWki
VVkVVL
WCI
VVWWkVV
LWWCI
−
∆=
−=−
=
−
∆+=−
∆−=
µ
µ
From Figure 10b, we have:
)(, 1111 thgsnmeqmdiff VVkgwhereVgi −=∆=
Equation 1 )(21
1, 1 thgstodueeq VVWWV −∆=∆⇒ ∆β
VDD
M1(OS)W−∆W
L
M2WL
Mclk Wclk
L
M3
M4
invbot1 invbot2
M5
M6
Vin1 Vin2
clk
VDD
M1 WL
M2 WL
Mclk Wclk
L
M3
M4
invbot1 invbot2
M5
M6
Vin1 Vin2
clk
+ −
I1 I2 I1 I2
∆Veq
(a) (b)
15
Although this is a valid equation, this gives no insight on how it behaves for a given input
common mode voltage, which could be determined and controlled easily. Thus, it is
desirable to relate Vgs1 with input Vcm.
Figure 11 common mode analyses of M1,2
If we look at only common mode voltage, the input differential pair can be
combined into a single transistor twice as wide as original. Thus, circuit in Figure 11a can
be transformed to Figure 11b. Mclk is in triode region, so it is modeled as a resistor, and
M1,2 are in saturation because their drains are closed to VDD at the beginning of
evaluation mode. Hence we can write:
1
2112
1,
211
12
11
1,211
)()(
)()(
)(
)(212
gsthDDclk
thgsgs
thDDclkn
thgsngsthgsnclkcm
clk
gscm
clk
clkdsthgsn
VVVW
VVWV
VVkVVk
VVVkRV
RVV
RV
VVkI
+−
−=+
−−
=+−=
−==
−=
VDD
M1 W12L
M2 W12L
Mclk Wclk
L
M3
M4
invbot1 invbot2
M5
M6
Vcm Vcm
clk
VDD
M12 2W12
L
Rclk
M34
invbot12
M56
Vcm
+Vds,clk
_
(a) (b)
I
16
This is a quadratic equation, so we can solve for (Vgs1 −Vth) after subtracting both sides by
Vth:
Equation 2
−
−−
+−
=− 1)()(4
12
)( 12
121
thDDclk
thcmthDDclkthgs VVW
VVWW
VVWVV
Therefore, we can substitute Equation 2 back to Equation 1 to get the input referred offset
due to current factor mismatch of M1 in terms of input Vcm. 1, β∆∆ todueeqV is, thus,
approximately square root of (Vcm − Vth) dependence.
Offset due to threshold mismatch of M3, ∆Vth2:
At the beginning of evaluation phase, invbot1,2 will drop from VDD. By the time
that invbot1,2 drops to VDD −Vthn, transistors M3,4 will turn on. However, M1-4 are still in
saturation. M3,4 act as cascode devices, and thus, ∆Vth2 does not create any offset at the
beginning of evaluation phase.
As invbot1,2 continue to drop and input devices M1,2 enter triode region, ∆Vth2
influences the differential current and thus creates offset. Let us analyze the differential
current as in the previous case. Here, I assume that out1, out2 are still closed to VDD, and
M5,6 are still off. This assumption is reasonable because by the time that M5,6 are on, the
signal is amplified, and hence the influence of ∆Vth2 becomes relatively small.
17
Figure 12 Threshold mismatch of M3
In Figure 12a, since M1,2 enter triode region, they are modeled as resistors. As a
result, M3,4 is a degenerated differential pair. The differential current is:
)(1),(,
1,
111333
13
3,32,3
thgsnthgsnm
m
meffmtheffmdiff VVk
RandVVkgRg
ggwhereVgi
−=−=
+=∆=
In Figure 12b, differential current due to equivalent offset voltage is:
1111 , dsnmeqmdiff VkgwhereVgi =∆=
Using these two equations, we can find the input referred offset. However, the
mathematics becomes complicated very quickly. To simplify the calculation, we note that
313
3
1 11
mm
m gRg
gR
≤+
≤
We can use this to calculate the upper and lower bounds of input referred offset. Since
upper bound gives the worst case offset, only upper bound calculation is shown here. As
a result, the upper bound of input referred offset due to ∆Vth2 is
VDD
M1 W12L
M2W12L
Mclk Wclk
L
M3(OS) W36L
M4W36L
invbot1 invbot2
M5
M6
Vout1 Vout2
Vin1 Vin2
clk
+ −
∆Vth2
VDD
M1 W12L
M2 W12L
Mclk Wclk
L
M3 W36L
M4 W36L
invbot1 invbot2
M5
M6
Vout1 Vout2
Vin1 Vin2
clk
+ −
∆Veq
(a) (b)
18
Equation 3 2112
3362
1
3,
)(2 th
ds
thgsth
m
mVtodueeq V
VWVVW
Vgg
Vth
∆−
=∆≤∆ ∆
Again, we want to relate the above equation with input common mode voltage, so we do
a common mode analysis.
Figure 13 common mode analyses for M3
Assuming out1, out2 are closed to VDD, we can find Vds1:
Equation 4 )()( 131 gscmgsDDds VVVVV −−−=
From current equations, we have:
Equation 5 2331
233
1 )()( thgsnclkgscmthgsnclk
gscm VVkRVVVVkR
VVI −=−⇒−=
−=
Substituting the above back to Vds1, and substituting Vds1 into Equation 3, input referred
offset voltage becomes:
VDD
M1 W12L
M2W12L
Mclk Wclk
L
M3 W36L
M4W36L
invbot1 invbot2
M5
M6
Vout1 Vout2
Vcm Vcm
clk
VDD
M12 2W12
L
Rclk
invbot12
M56
Vout12
Vcm
+Vds,clk
_
(b)
M34 2W36
L
(a)
I
19
Equation 6 212
362
333
3, )(2 th
ODnclkODthDD
ODVtodueeq V
WW
VkRVVVVV
th∆
−−−≤∆ ∆ , where
thgsOD VVV −= 33 is the overdrive voltage of M3.
The exact relationship between VOD3 and Vcm could be found by writing the drain current
of transistor M1 and substituting into Equation 5. Instead of the complete equations, to
understand how ∆Veq,due to ∆Vth2 and Vcm are related, we can pay attention on the
denominator of Equation 6. The denominator is simply a constant (VDD –Vth) subtract
(VOD3+Rclkkn3VOD32). We can expect that (VOD3+Rclkkn3VOD3
2) increase with Vcm by
inspecting Equation 5. The denominator will eventually reduce to zero if we allow Vcm to
increase beyond VDD. In other words, ∆Veq,due to ∆Vth2 will increase to infinity in the same
way as hyperbola. However, in the limited range of Vcm, we can only see a small portion
of hyperbolic curve as shown in simulation results in Figure 15.
Offset due to current factor mismatch of M3, ∆β2:
As in the previous case, we treat transistors M1,2 as resistors, and we can write the
differential current due to ∆β2 as:
20
Figure 14 Current factor mismatch of M3
( ) ( )
( ) ( ) ( )
∆+∆+
∆+∆−−−∆=
−−−∆−
∆+=
36
23
3633
23
363
23
233
363
11221
121
WWV
WWVVVVV
WWk
VVVVVW
Wki
gsgsthgsthgsn
thgsthgsgsndiff
where ∆Vgs3 is the small change in Vgs3 due to introducing 36WW∆ in M3.
We can neglect the products of ∆ terms because they are relatively small, and the
differential current is equal to the difference of current through M1,2, which is modeled as
R1. Assuming the gate voltages of transistors M3,4 are the same, we can write:
( ) ( )1
333
23
363 2
21
RV
VVVVVW
Wki gsgsthgsthgsndiff
∆=
∆−−−∆≈
Equation 7
( )( )
( )31
23
363
331
23
363
121
121
m
thgsn
thgsn
thgsn
diff gR
VVW
Wk
VVkR
VVW
Wki
+
−∆
=−+
−∆
≈⇒
VDD
M1 W12L
M2 W12L
Mclk Wclk
L
M3(OS)W36−∆W
L
M4 W36L
invbot1 invbot2
M5
M6
Vout1 Vout2
Vin1 Vin2
clk
VDD
Mclk Wclk
L
M3(OS) W36−∆W
L
M4 W36L
invbot1 invbot2
M5
M6
Vout1 Vout2
clk
R1 R1
(a) (b)
21
The expression in Equation 7 makes sense because it simply states that the small change
in drain current due to ∆β2 is the increase in current for a non-degenerated transistor
divided by (1+degeneration loop gain). Again to simplify the calculation, we calculate the
upper bound of input referred offset voltage.
( )23
3631 2
1thgsneqmdiff VV
WWkVgi −∆≤∆=
Equation 8
( )11
23
363
,21
2dsn
thgsn
todueeq Vk
VVW
WkV
−∆
≤∆ ∆β
Equivalently, we can express this in terms of VOD3 as in the previous case by using
Equation 4 & Equation 5.
Equation 9 ( ) 2333
23
3612
36, 2
12
ODnclkODthDD
ODtodueeq VkRVVV
VW
WWWV
−−−∆≤∆ ∆β ,where
thgsOD VVV −= 33
As you can see, the denominator is exactly the same as that of ∆Veq,due to ∆Vth2. Therefore,
∆Veq,due to ∆β2 has a hyperbolic increasing characteristic too. Although the numerator of
∆Veq,due to ∆β2 increases faster than that of ∆Veq,due to ∆Vth2, the overall rate of change is
dominated by the denominator. As a result, ∆Veq,due to ∆β2 is similar to ∆Veq,due to ∆Vth2 as
shown in simulation results in Figure 15.
Offset due to threshold mismatch of M5, ∆Vth3 and current factor mismatch of M5, ∆β3:
It can be seen that threshold mismatch and current factor mismatch of M5 have
22
little influence on input referred offset voltage. It is true because by the time that M5,6
turn on, the differential signal is already amplified to a large amplitude compared to the
mismatches. In other words, the gain from input to output is large, offset due to M5,6 on
the output is divided by a large gain caused by positive feedback; as a result, the input
referred offset voltage due to M5,6 is very small. The simulations show consistent results
with the theory.
Total input referred offset voltage:
The device mismatches are statistical numbers, and they are modeled as Gaussian
distribution. As a result, the total input referred offset is found by summing the variance
of the 6 mismatches above. That is
Equation 10 23
23
22
22
21
21 βββ σσσσσσσ ∆∆∆∆∆∆ +++++= VthVthVthtotal
For convenience, the last two terms, σ∆Vth3 and σ∆β3, can usually be neglected because
they are relatively small.
Simulations on input referred offset voltages over different Vcm:
The simulation results on input referred offset voltage show that the equations
above can predict the offset. Also, the variations on offset with varying VCM are also
consistent with the theory. Figure 15 shows the 3σ offset due to each transistor.
Obviously, the dominant sources of input referred offsets are due to transistor M1-4, and
offsets due to M5,6 are negligible. The overall offset is again calculated by summing the
23
variances as in Equation 10. For example, at Vcm = 1.4V, standard deviations of input
referred offset due to each differential pair are σ∆Vth1 = 10.1mV, σ∆β1 = 10.3mV, σ∆Vth2 =
9.5mV, σ∆β2 = 8.1mV, σ∆Vth3 = 1.9mV, σ∆β3 = 0.7mV. Using Equation 10, the standard
deviation of total input referred offset, σtotal = 19.2mV, and the worst case total input
referred offset is 6σtotal = 115mV.
0.8 1 1.2 1.4 1.6 1.80
10
20
30
40
50
60
Input Vcm
Inpu
t Ref
erre
d O
ffset
(mV
, diff
)
Offset due to Device Mismatch of Core Comparator
vt1 vt2 vt3 beta1beta2beta3
Figure 15 Input referred offset voltage due to each transistor
24
2.2 Supply Sensitivity
In the previous section, we found that input referred offset changes with VCM. In
addition, we found that as supply voltage changes, the input referred offset changes as
well. In most digital system, supply voltage is noisy because of the digital switching
property. As a result, it is important to know the supply sensitivity on offset. In order to
find the supply sensitivity, we need to find the supply sensitivities due to each transistor
and then combine the results to obtain the overall supply sensitivity as in the case of input
referred offset. Thus, the first section will discuss the supply sensitivity on offset due to
each transistor. The second section will combine the results and obtain the overall supply
sensitivity on offset.
2.2.1 Supply Sensitivity due to each transistor
As in the offset calculations in 2.1.2, the comparator is broken into 3 differential pairs
and each pair has threshold mismatch, ∆Vth, and current factor mismatch, ∆β. Supply
Sensitivity on offset due to each differential pair has been found in simulations. Since
offset due to ∆Vth1, which is simply equal to input referred offset, does not change with
supply and offset due to ∆Vth3 and ∆β3 are much smaller than other offsets, supply
sensitivity due to ∆Vth1, ∆Vth3, and ∆β3 are not shown in Figure 16.
25
0.8 1 1.2 1.4 1.6 1.810
15
20
25
30
35
40
45
Input Vcm (V)
Offs
et(m
V,d
iff)
Offset due to beta1 mismatch
Noraml 10% Sup −10% Sup
0.8 1 1.2 1.4 1.6 1.8−4
−3
−2
−1
0
1
2
3
4
Input Vcm (V)
Cha
nge
in O
ffset
(m
V, d
iff)
Offset due to beta1 mismatch
+10% Sup−10% Sup
(a) (b)
0.8 1 1.2 1.4 1.6 1.80
10
20
30
40
50
60
Input Vcm (V)
Offs
et(m
V,d
iff)
Offset due to beta2 mismatch
Noraml 10% Sup −10% Sup
0.8 1 1.2 1.4 1.6 1.8−4
−2
0
2
4
6
8
Input Vcm (V)
Cha
nge
in O
ffset
(m
V, d
iff)
Offset due to beta2 mismatch
+10% Sup−10% Sup
(c) (d)
0.8 1 1.2 1.4 1.6 1.80
20
40
60
80
100
Input Vcm (V)
Inpu
t Ref
erre
d O
ffset
(mV
, diff
)
Offset due to vt2 mismatch
Noraml 10% Sup −10% Sup
0.8 1 1.2 1.4 1.6 1.8−20
−10
0
10
20
30
Input Vcm (V)
Cha
nge
in O
ffset
, (m
V, d
iff)
Offset due to vt2 mismatch
+10% Sup−10% Sup
(e) (f)
Figure 16 Supply Sensitivity on Offset due to ∆β1, ∆β2, and ∆Vth2
26
In Figure 16, all offset values are 3σ standard deviation. In the plots on the left i.e.
(a), (c), and (e), “Normal” represents the offsets at normal supply 1.8V, which is exact
equal to the data in Figure 15. “10% Sup” represents the offsets when supply is 10%
higher than normal, which is 1.98V. “–10% Sup” represents the offsets when supply is
10% lower than normal, which is 1.62V. The plots in the right column i.e. (b), (d), and (f),
show the change in offset, ∆σ, from normal operating supply. Note that offset due to ∆β1
has positive supply sensitivity, which means positive change of supply causes positive
change in offset, while offsets due to ∆β3 and ∆Vth2 have negative supply sensitivity.
2.2.2 Overall Supply Sensitivity of Core Comparator
We can use change in offset, ∆σ, in 2.2.1 to calculate the overall supply
sensitivity on input referred offset. Since all offsets are statistical values, the overall
change in offset, ∆σtotal, is calculated by using Equation 10. And the worst-case overall
supply sensitivity is 6∆σtotal as shown in Figure 17. Figure 17a shows 6∆σtotal in mV,
while Figure 17b shows 6∆σtotal
6σtotal in percentage. In moderate VCM (1.2V – 1.4V) the
worst-case change in offset due to 10% supply change is about 10% also.
Before we finish this section, please keep in mind that Figure 17 shows the worst-
case values. Offset of a comparator is a random variable, and so is supply sensitivity on
offset. In addition, notice that supply sensitivities on offset due to ∆β1 and due to ∆Vth2
oppose to each other. This means that it is possible to obtain a high input referred offset
while supply sensitivity on offset is small, because the two opposing sources cancel with
27
each other.
0.8 1 1.2 1.4 1.6 1.80
10
20
30
40
50
60
Input Vcm (V)
Tot
al C
hang
e in
Offs
et (
mV
,diff
)
Supply Sensitivity on Offset
+10% Sup−10% Sup
0.8 1 1.2 1.4 1.6 1.80
5
10
15
20
25
30
35
Input Vcm (V)
Per
cent
age
Cha
nge
in O
ffset
(%
)
Supply Sensitivity on Offset in Percentage
+10% Sup−10% Sup
(a) (b)
Figure 17 Overall Supply Sensitivity on Offset
2.3 Speed
A second important requirement of a comparator is high sampling rate. Since the
comparator spends half of the cycle on evaluation and half of the cycle on reset, the
maximum sampling rate of a comparator depends on the speed of both evaluation and
reset. To do a complete analysis, the speed of evaluation and the speed of reset are
examined separately. First, analysis of evaluation phase will be performed and a set of
formula will be developed to represent how fast the evaluation is. Second, a criterion is
developed to assure proper reset. The effects on both evaluation and reset phase of
different input common mode bias, VCM, are discussed last.
2.3.1 Evaluation Phase
In evaluation phase, clock is logical high. All reset devices, RST1-6, are off, and
tail current Mclk is on. Input differential pair will steer the current according to the
28
difference of inputs. In order to create a lot of gain within a short amount of time,
positive feedback is utilized. Unlike traditional operation amplifier, which has finite gain,
positive feedback system provides infinite gain. Positive feedback is realized by two
back-to-back inverters. Here, characterizations on evaluation phase will be given, and
then the choices of transistor sizes will be briefly discussed. For your convenience,
Figure 7 is shown again in this section.
Figure 7 Core Comparator
Characterizations on Evaluation phase:
The whole evaluation phase can basically divided into three time intervals. In the
first time interval, the comparator changes from reset phase to evaluation phase. The
second time interval begins when Vinvbot1,2 drop to VDD − Vthn, turning on M3,4. And the
RST2 42
M5 42
VDD
RST142
RST5 42
RST6 42
M642
M3 42
M442
RST442
RST3 42
M1 82
M282
Mclk 162
Vout1 Vout2
Vin1 Vin2
clk
clk clk
clk
invbot1 invbot2
29
last time interval starts when Vout1,2 drop to VDD − |Vthp|, turning on M5,6. Let us look at the
behavior of the comparator starting from the first time interval.
During reset phase, nodes invbot1,2 are tied to VDD; thus, transistors M3-6 are all off.
As a result, when the comparator changes from reset phase to evaluation phase, M3-6 are
initially off. In this period, the only active devices are input differential pair M1,2 and
current source Mclk. Since M3-6 are off, transistors M1,2 see only capacitance on their drain,
Cinvbot1,2. The transfer function from input, in1,2, to invbot1,2, differential wise, can be
written as:
Equation 11 2,1
2,1
,
2,11 )(
invbot
m
diffin
invbot
sCg
VV
sH == , where gm1,2 is the transconductance of M1,2.
If we look at it more carefully, H1(s) is actually an integrator. This is desirable since it
gives infinite gain at DC while averaging or filtering out the high frequency noise
depending on viewing the problem in time domain or in frequency domain.
The second interval starts when M3,4 turn on, i.e. Vinvbot1,2 ≅ VDD − Vthn. Cross-
coupled transistors M3,4 provides positive feedback response. The response of positive
feedback is well known [4]. The differential output will be exponentially increasing with
time (often referred to as regeneration):
Equation 12 t
Cg
initialoutoutout
m
eVtV4,3
,)( = ,
where Cout/gm3,4 is regeneration time constant.
The third time interval is similar to the second time interval. As Vout1, Vout2 drop to
VDD − Vthp, M5,6 turn on. The positive feedback, as a result, becomes stronger and
30
differential output becomes:
Equation 13 t
Cgg
initialoutoutout
mm
eVtV6,54,3
,)(+
=
Equation 13 is valid until M3-6 enter triode region. As M3-6 enter triode region,
gm3,4 + gm5,6 decreases. Regeneration will eventually stop and Vout saturates at VDD.
It is however not convenient to go through all three equations to calculate the
exact output. As a result, we developed a simplified equation to characterize the
evaluation phase.
Equation 14 τdelaytt
inout eVtV−
=)( ,
where out
mm
Cgg 6,54,3 +
=τ and tdelay captures the initial integrator response. The implicit
meaning of tdelay is that we treat initial integrator response, which is much slower than the
regeneration response, as a delay on start of regeneration. Equation 14 enables us to
compare the evaluation speed of different comparators.
Choice of transistor sizes
In order to choose the transistor sizes such that the comparator gives fastest
evaluation, we should maximize integrating factor and minimize regeneration time
constant. This section will discuss the tradeoffs of sizing the transistors.
First, it is desirable to minimize regeneration time constant, since smaller
regeneration time constant results in larger gain in fixed amount of time. Let us first
concentrate on the effects of M3-6. According to [5], having the width ratio of M3,4 and
31
M5,6 equal to 1.0 gives the best regeneration. As you notice, the P:N ratio is smaller than
normal inverter P:N ratio, which is normally 2-3. In comparator both NMOS and PMOS
provide positive feedback, while PMOS has larger parasitic; thus, it is natural to size
down PMOS. If loading capacitance is large, increasing the width of M3-6 will increase
out
mm
Cgg 6,54,3 +
, so regeneration is faster. On the other hand, if loading capacitance is so
small that the gate capacitance of M3-6 dominates, increasing the width of M3-6 will not
change out
mm
Cgg 6,54,3 +
because both gm3,4 + gm5,6 and Cout increase at the same time. Under
small loading capacitance condition, although regeneration time constant does not depend
on the width of M3-6, it is not a good idea to choose arbitrarily large M3-6 because M3,4
add parasitic capacitance on node invbot1,2, which lowers down the integrating factor and
prevents the common mode of invbot1,2 from dropping down and thus delays the start of
regeneration. Another way to decrease the regeneration time constant is to increase the
current and thus increase the width of Mclk. As a result, there is tradeoff between power
and speed.
Secondly, we consider increasing the integrating factor 2,1
2,1
invbot
m
Cg
. It is obvious that
we should minimize Cinvbot1,2. However, when we employ digital offset compensation,
Cinvbot1,2 often increases. This will be discussed in more detail when we consider the
speed penalty of digital offset compensation in Chapter 3. Another way to increase the
integrating factor is to increase input gm. We can increase either the width of input
devices M1,2 or the width of current source Mclk. The former is a tradeoff with input
32
capacitance, while the latter is a tradeoff with power. From equation,
Doxm IL
WCg 2,1
2,1 2µ= we find that the rates of increase in gm1,2 should be the same for
sizing M1,2 and for sizing Mclk. However, since Mclk is often in triode region, sizing M1,2
increases not only W1,2/L but also ID because smaller Vgs1,2 results in larger Vds,clk.
Therefore, sizing input devices M1,2 gives us more advantages. Note that sizing input
devices M1,2 also gives advantages in term of input offset voltage.
Simulation Results on Sizing Transistors
The evaluation speed has been simulated to confirm the intuitive understanding
explained above. [5] states that the comparator gives the best performance by having the
ratio between M3,4 and M5,6 equal to 1, so the width of M3-6 are always the same in all
simulations below. The three remaining parameters are width of transistors Mclk, M1,2,
and M3-6. To compare the speed, we calculate the regeneration time constant τ, and tdelay
(see Equation 14 for definition). To show the combined effect, we also calculate the time
from clock transition to the time that differential output reaches 1.2V, denoted as
t(@Vout=1.2V). An output of 1.2V is chosen because it is large enough to toggle the output
stage, for example inverter or SR latch. We rank the comparators using T(@Vout=1.2V). In
the table shown below, columns Mclk, M1,2, and M3-6 are the ratio of their width to the
minimum transistor width (Wmin/L) = 4λ/2λ = 0.48µm/0.24µm. For example, Mclk = 2×
means that size of Mclk = 2Wmin/L = 8λ/2λ = 0.96µm/0.24µm. Note that L=0.24µm has
effective length Leff = 0.18µm.
Sim Mclk M1,2 M3-6 τ(ps) tdelay(ps) T(@ Vout=1.2V)(ps) Ranks
33
1 1× 1× 1× 40.4 74.0 263 8 2 2× 1× 1× 37.8 57.2 234 6 3 1× 2× 1× 37.2 55.6 227 5 4 1× 1× 2× 42.0 98.7 307 10 5 2× 2× 1× 34.3 38.3 196 1 6 1× 2× 2× 36.2 79.2 255 7 7 2× 1× 2× 38.9 75.6 265 9 8 2× 2× 2× 32.8 54.9 211 2 9 4× 1× 1× 37.2 45.3 219 4 10 1× 4× 1× 38.6 40.8 217 3 11 1× 1× 4× 52.5 130 425 11
Table 1 Simulation results on evaluation with varying comparator transistor size
As shown in the table, sim5, which doubles both Mclk and M1,2, gives the fastest
response. This makes sense because we simultaneously increase positive feedback
gm3,4+gm5,6 and input gm1,2, which is directly proportional to the integrating factor. One
would think that doubling all devices Mclk, M1,2, and M3-6 would be fastest. However,
sim8 is only second fastest. Although sim8 actually has a faster τ than sim5, sim8 has
more delay on tdelay, resulting in a slower overall response.
The next two fastest are sim10 and sim9. The larger M1,2 have a slight advantage
as discussed earlier. These two simulations are similar for the next two in the rank, sim3
and sim2.
The 7th in the rank is sim6. Again, increasing M3-6 gives better τ than rank #3-6 do,
but it adds too much capacitance on node invbot1,2, which slow down the integration. The
other interesting result is that sim1 is ranked 8th, which tells us using all minimum size
does not necessarily give the slowest response. Sim7, sim4, and sim11 are slowest. These
three simulations show that increasing size of M3-6 is not a good idea. Note that the
output loading effect is already taken into account in the simulations above. The details
34
of output loading will be discussed in section 2.6.
Once the comparator is optimized for the evaluation phase, we should design an
appropriate reset so that it can work correctly and efficiently.
2.3.2 Reset Phase
Reset is as important as regeneration for accurate operation. In order to reset a
comparator that has positive feedback, we must break its positive feedback loop and reset
it as fast as its regeneration. However, if the reset is incomplete and there is any residual
charge on Vout1, Vout2, positive feedback will amplify the residual charge exponentially
when evaluation phase comes again. As a result, a small residual charge can create large
input referred offset. In this project, differential output needs to be less than 0.5mV at the
end of reset phase to achieve the required accuracy. In this section, the design of reset
transistors is presented; tradeoffs between reset and evaluation will also be discussed.
Design of Reset Transistors:
During clock is logical low, the tail current source Mclk is off. If no reset device is
added, the comparator will still stay in its state forever because of the positive feedback.
In order to break the positive feedback, we must place some transistors to break the back-
to-back inverter. All possible reset transistors RST1-6 are shown in Figure 7. For your
convenience, Figure 7 is shown here again.
35
Figure 7 Core Comparator
The most important reset is RST5, which shorts the two outputs together. Without
RST5, the reset response is very poor. However, RST5 alone is not enough because as
long as all 4 feedback devices are on, there is fighting between reset and regeneration. In
order to break the positive feedback, RST1,2 and RST3,4 are utilized.
Both RST1,2 and RST3,4 have their tradeoffs. First, RST1,2 can only shut off
PMOS; as a result, there is still a slight fighting between reset and regeneration due to
NMOS M3,4. More importantly, since RST1,2 are connected to out1,out2, the parasitic of
RST1,2 will degrade the regeneration time constant. Second, RST3,4 are indirect resets,
because they serve as reversing the current of NMOS M3,4. Once current is reversed, M3,4
not only stop regenerating, but also help reset the comparator. In small signal analysis, a
cross-coupled NMOS pair under reversed current condition has effective resistance equal
RST2 42
M5 42
VDD
RST142
RST5 42
RST6 42
M6 42
M3 42
M4 42
RST442
RST3 42
M1 82
M2 82
Mclk 162
Vout1 Vout2
Vin1 Vin2
clk
clk clkclk
invbot1 invbot2
36
to 1/gm. This 1/gm3,4 will help cancel the −2/gm5,6 from positive feedback PMOS M5,6,
leaving RST5 to eliminate the rest of the negative resistance. Since RST3,4 are indirect
resets, in the early part of the reset phase, it cannot reset the comparator as quickly as
RST1,2. On the other hand, RST3,4 completely break the positive feedback, so it can
remove small output residue more quickly and more accurately than RST1,2. This
behavior can be seen in simulations in the next section. RST3,4 do not degrade the
regeneration time constant, yet they degrade the integrating factor of a comparator.
The last reset is RST6. In digital offset compensated comparator, capacitance on
node invbot1,2 is usually large; as a result, RST6 is introduced to further reset the charge
on node invbot1,2.
Simulation Results on Reset Devices:
Simulations are performed with varying reset devices size to see the performance
change, including evaluation and reset. We simulate on different sizes of RST1,2, RST3,4,
RST5, and RST6. As in the evaluation section, one unit size is Wmin/L = 4λ/2λ =
0.48µm/0.24µm, and the device sizes are multiple of unit size. Simulation condition is
Vcm=1.2V, Mclk=4×, M1,2=2×, and M3,4=1×. This configuration is the same for all digital
offset compensated comparators so that we are able to perform a fair comparison later.
For comparison, we calculate all evaluation metrics, τ, tdelay, and T(@Vout=1.2V) (see
Table 1 for definition). Three new measurements are maximum frequency in evaluation
phase, fmax,eva = 1/(2 T(@Vout=1.2V)), reset time, treset, that is the time required to reset a
comparator whose differential output decreases from full VDD to 0.5mV, and maximum
frequency based on reset time, fmax,rst = 1/(2treset).
37
Evaluation Phase Reset Phase Sim Rst5 Rst1,2 Rst3,4 Rst6 τ(ps) tdelay(ps) T(@Vout=1.2V)
(ps) fmax,eva (GHz)
Rank treset (ps)
fmax,rst (GHz)
Rank
1 1× 0× 0× 0× 30.5 15.7 157 3.19 1 836 0.60 11 2 1× 1× 0× 0× 33.0 19.3 171 2.92 5 332 1.51 9 3 1× 0× 1× 0× 30.6 21.2 162 3.08 2 305 1.64 8 4 1× 1× 1× 0× 32.9 24.6 176 2.84 7 174 2.88 2 5 1× 1× 1× 1× 32.9 29.0 181 2.77 8 175 2.85 3 6 2× 0× 0× 0× 32.3 20.7 170 2.95 4 650 0.77 10 7 2× 1× 0× 0× 34.7 24.3 184 2.72 9 269 1.86 6 8 2× 0× 1× 0× 32.3 26.5 176 2.85 6 234 2.14 4 9 2× 1× 1× 0× 34.7 27.9 187 2.67 11 149 3.36 1 10 1× 2× 0× 0× 35.3 24.0 186 2.68 10 266 1.88 5 11 1× 0× 2× 0× 30.6 26.0 167 2.99 3 281 1.78 7
Table 2 Simulation results on reset device
Let us analyze the results shown in Table 2 from top to bottom. Sim1 is a
comparator with only RST5, the middle reset that ties both outputs together. As expected,
it gives the fastest evaluation but the slowest reset. Next, adding RST1,2 in sim2 will
speed up the reset, almost 3 times as fast as original. Also as expected, adding RST1,2
slightly degrades the regeneration time constant because it adds capacitance on the output
nodes. Sim3 has a highly desirable result. By adding RST3,4, the comparator resets faster
than that in sim2 while degradation of evaluation is minimum, i.e. the 2nd fastest in
evaluation. Since RST3,4 do not add parasitic capacitance on out1,out2, the regeneration
time constant is almost the same as that in sim1. Although integrating factor is reduced,
which can be seen by comparing tdelay, the overall evaluation performance is not heavily
degraded because the comparator spends only a short time on integration.
Sim4 uses both RST1,2 and RST3,4; hence, reset response is much faster, the 2nd
fastest. Among all comparators shown in this table, sim4 is the best since both evaluation
and reset achieve 2.8Ghz. In next simulation, further adding reset RST6 seems to give
38
adverse results, where both evaluation and reset is slower than those in sim4. However,
note that RST6 may become more useful when digital offset compensation is added to the
comparator. The effect of RST6 will be discussed more in Reset Penalty in Chapter 3.
Sim6-9 have similar behavior as sim1-4 do. Generally, sim6-9 have slower
evaluation but faster reset because of the doubled RST5. In sim10 and sim11, we see that
doubling RST1,2 or doubling RST3,4 alone can never be as efficient as having RST1,2 and
RST3,4 simultaneously (sim4).
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
−0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Time, ns
Diff
eren
tial O
utpu
t, m
V
Reset Response of a comparator
←sim2
←sim3
sim10→
sim11→
Figure 18 Reset Response of sim2, sim3, sim10, and sim11
Interestingly sim3 resets faster than sim2, but sim11 resets slower than sim10.
Figure 18 illustrates the reason. RST1,2 (sim2 & sim10) can reset the comparator quickly
at the beginning; however, the fighting between reset and regeneration exists, and thus it
takes a long time to eliminate small residue charge. On the other hand, RST3,4 (sim3 &
39
sim11) mainly reverse the current of M3,4; hence, there is a delay before the positive
feedback is broken. After the feedback is broken, comparator is completely reset at a
rapid rate.
In conclusion, sim4, which has RST5, RST1,2, and RST3,4, gives the best tradeoff
between evaluation and reset. This configuration can break the positive feedback quickly
while it does not heavily degrade the evaluation.
Effects on evaluation and reset with varying Vcm:
The comparator shown in Figure 7 works only in a certain range of input common
mode voltage, Vcm. For the lower bound, the input common mode voltage must be high
enough to turn on both input devices M1,2 and current source Mclk. (Vcm > Vth1,2 = 0.4V)
For the upper bound, the input common mode voltage is limited by the power supply on
chip (Vcm < VDD = 1.8V). It is found that the comparator achieves the best performance in
intermediate Vcm. The simulation results are shown below.
Evaluation Phase Reset Phase Vcm (V) τ(ps) tdelay(ps) T(@Vout=1.2V)
(ps) fmax,reg (GHz)
treset (ps) fmax,rst (GHz)
0.8 39.5 33.9 216 2.31 168 2.97 1.0 34.5 24.8 184 2.72 171 2.92 1.2 32.9 24.6 176 2.84 174 2.88 1.4 32.2 29.7 178 2.81 176 2.84 1.6 31.7 35.6 182 2.75 178 2.82 1.8 31.4 45.4 190 2.63 179 2.80
Table 3 Evaluation and Reset with vary Vcm (see Table 1,Table 2 for term definition)
At low Vcm the regeneration is slow as expected because low Vcm results in low
Vds,Mclk thus low tail current. As Vcm increases, tail current increases, so regeneration time
constant decreases. However, at high Vcm, tdelay becomes worse since input devices M1,2
40
enter triode region, which decreases input gm and thus the integrating factor. In short, τ
becomes worse in low Vcm, and tdelay becomes worse in high Vcm. Intermediate Vcm
therefore gives the fastest evaluation.
For reset phase, high Vcm leads to slightly slower reset. A high common mode
input tries to pull down invbot1,2 harder, which opposes the pull up of the reset devices.
Comparing the variation of fmax in evaluation phase and reset phase, we can see
that within the possible Vcm bounds (0.4V < Vcm < 1.8V), the comparator still provides a
good performance in the range of 1.0V ≤ Vcm ≤ 1.6V.
2.4 Input Capacitance
In applications, like over-sampler and flash ADC, a bank of comparators is
typically placed in parallel. Total input capacitance, in these cases, may become
enormous because it is simply equal to the input capacitance of a single comparator
multiplied by number of comparators in parallel. Therefore, it is desirable to minimize
the input capacitance of a comparator. Unfortunately, the input capacitance of a simple
comparator, like Figure 7, is the gate capacitance of input devices M1,2, which must be
sized to fulfill the input referred offset requirement. As a result, there is a direct tradeoff
between input capacitance and offset. One of the methods to decouple the relationship
between input capacitance and offset is digital offset compensation. The input
capacitance requirement will be revisit in Chapter 3 where digital offset compensation is
introduced.
41
2.5 Power Consumption
Power consumption is also a big issue when numerous comparators are used in
applications, like over-sampling receiver and flash ADC. Again, the total power
consumption simply gets multiplied by the number of comparators. To reduce the power
consumption, load capacitance and current must be minimized. Assuming that load
capacitance is already minimized by proper sizing and careful layout, we can only reduce
current by minimizing tail current transistor Mclk. As current has direct relationship with
speed, there is obviously tradeoff between power consumption and speed. Fortunately,
power consumption of a comparator is typically much less than normal operation
amplifier because positive feedback saturates the back-to-back inverters and shuts off the
current when evaluation is finished. Moreover, according to [3], comparator shown in
Figure 7 has a better power efficiency among other architecture. Simulation results on
power measurements are shown in Table 4. As you can see, power consumption increases
with input common mode voltage because Mclk is usually in triode region and Vds,clk varies
with Vcm.
VCM (V) 0.8 1.0 1.2 1.4 1.6 1.8 Power (µW) 79.41 87.76 94.25 100.4 106.0 112.2
Table 4 Power Consumption of Core Comparator
2.6 Design of Next Stage (SR Latch)
In order to provide a constant logical output over one period, we must place a SR
latch after the comparator. Since comparator outputs provide full swing signal in
42
evaluation phase and are pull up to VDD in reset phase, a NAND based SR latch is well
suited. However, a NAND based SR latch may not give satisfying performance at high
speed. Hence, a simplified SR latch as shown in Figure 19 has been designed.
Figure 19 Simplified SR Latch
During evaluation phase, full swing differential signal from comparator is converted to
single ended digital signal at SRoutb. During reset phase, Vin1, Vin2 are pull up to VDD,
turning off MSR1,SR2. Thus, Node SRoutb stays constant until the next evaluation phase
comes again. This behavior is exactly same as a NAND based SR latch. The advantage of
this circuit is its high speed and low input capacitance, which directly affects comparator
regeneration time constant and power consumption. Although this SR latch has
systematic offset and large random offset due to small transistor size, fortunately
comparator has large gain, so input referred offset due to SR latch is well below 2mV
according to simulation. For fair comparison, all digital offset compensated comparators
in the next chapter are followed by this SR latch. Inverters are then used to buffer up to
drive the output.
MSR1 42
MSR2 42
VDD VDD
MSR3 42
MSR4 42
Vin1 Vin2
Output SRoutb
43
Chapter 3 Digital Offset Compensation
The most important feature of digital offset compensation in comparator is that
offsets are measured digitally and are stored in static memory. Once offsets are stored,
the comparator can remain in open loop system, and thus, inherent speed of a comparator
can possibly be achieved.
In this project, four architectures on digital offset compensation are considered.
This project will compare the characteristics of these four architectures, and tradeoffs
between them. We compare all four architectures by measuring the performance metrics,
which were characterized for the core comparator in chapter 2. In this chapter, four
architectures are first presented, and their basic operating principles are explained.
Section 3.2 – 3.6 will compare performance metrics: input referred offset, supply
sensitivity, speed, input capacitance, and power consumption respectively. The last
section will give a summary of comparison of all four architecture.
44
3.1 Four Different Architectures
3.1.1 Architecture Comp1
Figure 20 Schematic of Comp1
The first architecture, Comp1, is shown in Figure 20. Extra devices MCM1-6 and
MOS1-6 are placed in parallel with input devices to steer small amount of current. This
current will provide an offset to compensate for the internal offset due to device
mismatches. Node VCM is connected to the common mode voltage of inputs Vin1 and Vin2.
Since internal offset varies with common mode as you can see in Figure 15, an offset
compensation that varies with VCM can increase the correction precision. Nodes D1-4 are
controlled digitally. Turning on only D1 provides the least offset correction, so we call it
RST2 42
RST142
Mcm4 46
MCM3 46
M6 42
M1 82
M5 42
M2 82
Mclk 162
RST6 62
M3 42
M4 42
RST5 42
Vin1 Vin2
clk
RST4 62
RST3 62
clk
VDD
clk clk
Vout1 Vout2
Invbot2 Invbot1
MCM1 46
MOS1A 46
MOS1B 46
MCM2 46
MOS246
MOS3 46
D1 D2 D3
Mcm6 46
Mcm5 46
MOS4 46
MOS5 46
MOS6A 46
MOS6B 46
VCMVCM
D4
45
Least Significant Bit (LSB) correction. Turning on subsequent bits (D2, D3) increases the
correction in a binary fashion. If negative offset compensation is needed, D4 will be
turned on and D1-3 will be turned on appropriately to control the magnitude of the
negative offset. The LSB control devices, D1, is not half the size of D2 device because it
is desirable to minimize the parasitic capacitance of MCM1-6 and MOS1-6 and not to slow
down the speed of the comparator. The performance and compensation non-linearity of
Comp1 will be discussed in the next section.
3.1.2 Architecture Comp2
Figure 21 Schematic of Comp2
The second architecture, Comp2, is similar to Comp1. Schematic of Comp2 is
shown in Figure 21 [6]. The problem of Comp1 is its large parasitic capacitance due to
digital offset compensation. Each branch consists of 2 NMOS and the capacitance
RST2 42
RST1 42
M6 42
M1 82
M5 42
M2 82
Mclk 162
RST6 62
M3 42
M4 42
RST5 42
Vin1 Vin2
clk
RST4 62
RST3 62
clk
VDD
clk clk
Vout1 Vout2
Invbot2 Invbot1MOS0 48
MOS1 48
MOS2 88
MOS3 168
MOS4 328
D1b
D2b
D3b
VCM VCM
D4b
46
between the NMOS slows the comparison speed. In Comp2, one branch is a single
NMOS. Therefore, using linear scaling on MOS1-4 in Comp2 does not degrade the speed
as severely as Comp1 does. MOS1-4 are binary weighted, so additional coding on D1-4 is
not needed. The supply of inverters is VCM, so the compensation magnitude also varies
with input common mode. Dummy device MOS0 is added to balance the capacitance on
nodes invbot1,2, so no systematic offset is introduced when MOS1-6 are off.
3.1.3 Architecture Comp3
Figure 22 Schematic of Comp3
The third architecture, Comp3, produces digital offset by controlling tail current
[7]. In Figure 22, tail current is split to MclkL and MclkR. Additional currents sources Mclk0-
4 and MOS0-4 are digitally controlled by D1-4. Mclk1-4, and MOS1-4 is binary weighted.
Dummy current source Mclk0 and MOS0 is again for balancing the comparator. A small
RST2 42
RST142
M6 42
M1 82
M5 42
M282
MclkL 82
RST6 62
M3 42
M442
RST5 42
Vin1 Vin2
clk
RST4 62
RST3 62
clk
VDD
clk clk
Vout1 Vout2
Invbot2 Invbot1
M7 44
VDD
MclkR 82
MOS0 42
Mclk0 42
MOS1 42
Mclk1 42
MOS2 82
Mclk2 82
MOS3 162
Mclk3 162
Mclk4 322
MOS4 322
D1 D2 D3
D4
47
NMOS M7 has three purposes. First, it reduces offset due to mismatch of MclkL and MclkR.
Second, the offsets created by digital compensation devices Mclk1-4 and MOS1-4 are
reduced, so minimum channel length can be used to create the appropriate range of offset,
unlike Comp1 and Comp2, whose digital compensation parts have longer channel length.
Third, M7 promotes current steering of differential pair M1,2. If M7 is not present, M1 sees
only MclkL, which is model as resistor because MclkL is in triode region. As a result, M1 is
degenerated by RMclkL. On the other hand, if M7 is present, M1 is degenerated by
RMclkL//(RM7/2) so input gm is larger.
3.1.4 Architecture Comp4
Figure 23 Schematic of Comp4
The last architecture, Comp4, is shown in Figure 23 used by [8]. Comp4 varies
capacitances of invbot1,2; an imbalance current flowing into PMOS capacitors MC0-4
produces offset. During digital signals D1B-4B are high, PMOS MC1-4 are off, so nodes
RST2 42
RST1 42
M6 42
M1 82
M5 42
M2 82
Mclk 162
RST6 62
M3 42
M4 42
RST5 42
Vin1 Vin2
clk
RST4 62
RST3 62
clk
VDD
clk clk
Vout1 Vout2
Invbot2 Invbot1
MC0 42
MR 162
VDDD1B D2B D3B
MC1 42
MC2 82
MC3 162
×1 ×2 ×4
D4B
MR 162
×8 ×1
MC4 322
RST7 46 VDD
48
invbot1,2 see only source/drain overlap capacitances. If digital signal D1B, for example,
switches to low, PMOS MC1 turns on, so invbot2 sees source/drain overlap capacitance
plus channel capacitance due to MC1. A slight capacitance difference between invbot1 and
invbot2 results in a small current imbalance. As a result, by controlling the difference of
capacitance between invbot1 and invbot2, offset of the comparator can be controlled.
PMOS MR, acting as a resistor, is placed in series with PMOS capacitance MC0-4. The
series resistors reduce the effective capacitance, so the digital offset precision can be
adjusted. MR is carefully sized so that the correction range of the digital offset
compensation just covers the maximum offset due to internal device mismatches.
3.2 Characteristics of Digital Offset Compensation
The goal of digital offset compensation is to create an offset that cancels the
internal offset due to device mismatches, so the overall offset of the comparator reduces
to zero ideally. This section discusses the offset magnitude for each comparator. However,
if the digital offset steps are not uniform, the overall offset after compensation will be
degraded. In other words, linearity among offset magnitude directly affects the worst-
case overall offset. Linearity of offset compensation is secondly presented, and the worst-
case overall offset after compensation is shown last.
3.2.1 Offset Magnitude of Digital Compensation
All four comparator Comp1-4 have 4-bit (16-level) offset correction. Simulations
have been performed to examine the characteristics of offset correction of each
comparator. Simulation results are shown in Figure 24 – Figure 27. “Device Mismatch”
49
represents 6σ of offset due to internal device mismatch of a core comparator. “Digital
OS” represents 16-level offset correction of the comparators.
Figure 24 shows the digital offset for Comp1. Comp1 loses one digital level on
D4D3D2D1 = 1111 because this digital value provides zero offset as shown in the
schematic in Figure 20. The variation of digital offset with VCM is similar to that of
internal device mismatch shown in dotted line in the figure. This property provides a
better correction over wide range of VCM.
Figure 25 shows the digital offset magnitude of Comp2. Comp2 provides 16-level
correction. Each level is close to a constant value over high VCM. As you can see from the
distribution, the 16 levels divides 6σ internal offset quite evenly. The linearity is
expected to be the best and will be discussed in the next section in detail.
Figure 26 shows the digital offset of Comp3. Comp3 splits the tail current, so
mismatch between two tail currents contributes offset of the comparator. As a result, the
internal device mismatch is larger than Comp1, Comp2, and Comp4. The digital offsets
created by Mclk1-4 in Figure 22 increase fairly quickly with VCM, making a wide spread in
high VCM. The worst-case overall offset after compensation is, thus, degraded. In addition,
compression of the offset step size at high digital offset settings can be easily observed in
Comp3. The first positive LSB creates the largest step. As the digital value increases, the
offset difference between two levels diminishes because Vds,clk decreases with more MOS1-
4 turned on. Since Vds,clk is reduced, the offsets created by digital controlled branches
reduces as well.
50
0.8 1 1.2 1.4 1.6−150
−100
−50
0
50
100
150
Input Vcm
Inpu
t ref
erre
d of
fset
(mv,
diff
eren
tial) Comp1, Digital Controlled Offset
Device MismatchDigital OS
Figure 24 Digital Offset of Comp1
0.8 1 1.2 1.4 1.6−150
−100
−50
0
50
100
150
Input Vcm
Inpu
t ref
erre
d of
fset
(mv,
diff
eren
tial) Comp2, Digital Controlled Offset
Device MismatchDigital OS
Figure 25 Digital Offset of Comp2
51
0.8 1 1.2 1.4 1.6
−400
−300
−200
−100
0
100
200
300
400
Input Vcm
Inpu
t ref
erre
d of
fset
(mv,
diff
eren
tial) Comp3, Digital Controlled Offset
Device MismatchDigital OS
Figure 26 Digital Offset of Comp3
0.8 1 1.2 1.4 1.6
−200
−150
−100
−50
0
50
100
150
200
Input Vcm
Inpu
t ref
erre
d of
fset
(mv,
diff
eren
tial) Comp4, Digital Controlled Offset
Device MismatchDigital OS
Figure 27 Digital Offset of Comp4
52
As shown in Figure 27, the digital offsets of Comp4 increase gradually with VCM.
This characteristic is similar to that of Comp1. Some compression of the step size has
been observed.
3.2.2 Linearity of Digital Offset Compensation
All 4 architectures have equal number (4-bit) of digital offset correction. The
nonlinear offset compensation will degrade the effect number of bit correction; as a result,
the accuracy will be degraded. This section compares the differential non-linearity (DNL)
of each comparator.
Digital offset DNL of Comp1 is shown in Figure 28. The maximum DNL is
approximately 0.5 LSB. There is a clear “zig zag” pattern in the DNL profile. This
pattern is created by the non-linear scaling on the digital controlled branches. We
observed that the LSB creates a larger offset then it should; thus, a large positive DNL in
one digital setting is followed by an equal magnitude but negative DNL in the subsequent
digital setting. Fortunately, the “zig zag” pattern creates less than 0.5 LSB DNL.
Figure 29 shows digital offset DNL of Comp2. It can be observed that as more
switches are asserted, the step size slightly decreases. As a result, Comp2 also has minor
compression of the offset step size, and it causes about 0.5 LSB DNL.
Digital offset DNL of Comp3 is shown in Figure 30. The DNL of Comp3 is the
worst among 4 architectures. The maximum DNL is as high as 1 LSB, reducing the
effective number of bits to less than 3 bits of correction. The compression described
earlier is particularly noticeable. Digital Offset
DNL of Comp4 is shown in Figure 31. Comp4 loses about 0.8 LSB DNL.
53
Figure 28 Digital Offset DNL of Comp1
Figure 29 Digital Offset DNL of Comp2
−10 −5 0 5 10−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6Comp1, Digital Offset DNL
Offs
et D
NL
(LS
B)
Digital Level, W
vcm=0.8vcm=1.0vcm=1.2vcm=1.4vcm=1.6
−10 −5 0 5 10−0.4
−0.2
0
0.2
0.4
0.6Comp2, Digital Offset DNL
Offs
et D
NL
(LS
B)
Digital Level, W
vcm=0.8vcm=1.0vcm=1.2vcm=1.4vcm=1.6
54
Figure 30 Digital Offset DNL of Comp3
Figure 31 Digital Offset DNL of Comp4
−10 −5 0 5 10−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
1.2Comp3, Digital Offset DNL
Offs
et D
NL
(LS
B)
Digital Level, W
vcm=0.8vcm=1.0vcm=1.2vcm=1.4vcm=1.6
−10 −5 0 5 10−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8Comp4, Digital Offset DNL
Offs
et D
NL
(LS
B)
Digital Level, W
vcm=0.8vcm=1.0vcm=1.2vcm=1.4vcm=1.6
55
3.2.3 Worst-Case Overall Offset after compensation
Ideally, overall offset of a comparator after digital offset compensation is equal to
maximum offset of the core comparator divided by 2(Number of bits correction). In the previous
section, we know that effective number of bits should replace the actual number of bit to
capture the non-linearity. In addition to non-linearity, we found that the maximum offset
of the comparator should really be replaced by the offset correction range of the
particular architecture. In other words, the worst-case overall offset is approximated by
bitsofnumberEffective
RangeCorrectionOffset2
. In simulation, the worst-case overall offset is calculated by
dividing the biggest step between two digital levels in Figure 24 – Figure 27 by 2 because
the worst situation is when internal offset lies at the middle of two digital offset levels.
The simulated results are shown in Figure 32.
Comp4 has larger worst-case overall offset then Comp1 and Comp2 because
Comp4 has not only worse DNL profile but also larger correction range (±220mV), while
the correction range of Comp1 and Comp2 is only ±150mV. The large worst-case overall
offset of Comp3 clearly shows that knowing only DNL is not sufficient. Even though
DNL of Comp3 is only two times larger than that of Comp1 and Comp2, the actual
worst-case offset of Comp3 is four times larger, because Comp3 has worse internal offset
to start, and thus has larger offset correction range. From this comparison of the worst-
case overall offset, we conclude that Comp1 and Comp2 have the best compensation
offset and Comp3 is the worst.
56
Figure 32 Worst-case overall offset
3.3 Supply Sensitivity
As discussed in section 2.2, the input referred offset due to device mismatches
changes with supply voltage. Similarly, the digital offset changes with supply as well.
The overall supply sensitivity of an architecture is thus calculated by combining the
supply sensitivity of internal offset in section 2.2 and the supply sensitivity on digital
offset. In this section, simulations are performed to find the supply sensitivity on digital
offset of each architecture. The worst-case supply sensitivity of each comparator will be
obtained in the end of this section.
0.8 1 1.2 1.4 1.60
10
20
30
40
50
60
70
Input Vcm
Wor
st−
case
offs
et(m
v, d
iffer
entia
l)
Worst−case overall offset
Comp1Comp2Comp3Comp4
57
0.8 1 1.2 1.4 1.670
80
90
100
110
120
130
Input Vcm (V)
Offs
et (
mV
,diff
)
Digital Offset of Comp1
Noraml 10% Sup −10% Sup
0.8 1 1.2 1.4 1.6−10
−5
0
5
10
15
Input Vcm
Cha
nge
in O
ffset
(m
V, d
iff)
Digital Offset of Comp1
10% Sup −10% Sup
(a) (b)
Figure 33 Supply Sensitivity on Offset of Comp1
0.8 1 1.2 1.4 1.650
60
70
80
90
100
110
Input Vcm (V)
Offs
et (
mV
,diff
)
Digital Offset of Comp2
Noraml 10% Sup −10% Sup
0.8 1 1.2 1.4 1.6−20
−10
0
10
20
30
Input Vcm
Cha
nge
in O
ffset
(m
V, d
iff)
Digital Offset of Comp2
10% Sup −10% Sup
(a) (b)
Figure 34 Supply Sensitivity on Offset of Comp2
0.8 1 1.2 1.4 1.60
100
200
300
400
500
600
700
Input Vcm (V)
Offs
et (
mV
,diff
)
Digital Offset of Comp3
Noraml 10% Sup −10% Sup
0.8 1 1.2 1.4 1.6−100
−50
0
50
100
150
Input Vcm
Cha
nge
in O
ffset
(m
V, d
iff)
Digital Offset of Comp3
10% Sup −10% Sup
(a) (b)
Figure 35 Supply Sensitivity on Offset of Comp3
58
0.8 1 1.2 1.4 1.640
60
80
100
120
140
160
Input Vcm (V)
Offs
et (
mV
,diff
)
Digital Offset of Comp4
Noraml 10% Sup −10% Sup
0.8 1 1.2 1.4 1.6−20
−15
−10
−5
0
5
10
15
Input Vcm
Cha
nge
in O
ffset
(m
V, d
iff)
Digital Offset of Comp4
10% Sup −10% Sup
(a) (b)
Figure 36 Supply Sensitivity on Offset of Comp4
In Figure 33 – Figure 36, the plots on the left (a) show maximum digital offsets of
Comp1 – Comp4 when supply is “Normal”(1.8V), 10% higher (1.98V) “10% Sup”, and
10% lower (1.62V) “–10% Sup”. The plots on the right (b) show the change in offset,
∆VDigiOS, from normal supply, which is the supply sensitivity on offset in mV.
Having both supply sensitivities on offset due to internal mismatch and due to
digital offset compensation, the overall supply sensitivity on offset can be found for each
comparator. However, the calculation on overall supply sensitivity is not straight forward,
because all sensitivities are not independent random variables. Supply sensitivity due to
digital offset compensation, ∆VDigiOS, depends on the total internal offset of the
comparator, because digital value is set to compensate the internal offset at the beginning.
Thus, it is reasonable to state that ∆VDigiOS is proportional to internal offset, 6σtotal. On the
other hand, the supply sensitivity on internal offset ∆σtotal must also depend on total
internal offset 6σtotal. Thus, supply sensitivity on digital offset ∆VDigiOS and supply
sensitivity on internal offset ∆σtotal are correlated. Furthermore, we know ∆σtotal is not
directly proportional to total input offset 6σtotal because some mismatches have positive
59
supply sensitivity while the others have negative supply sensitivity. This causes a
possibility that high internal offsets, 6σtotal, may have low supply sensitivity, ∆σtotal. All
these situations complicate the calculation of overall supply sensitivity of Comp1 −
Comp4.
To develop special treatments on accounting the correlation between variables
seems to be out of scope of this project. A rough approximation on worst-case overall
supply sensitivity is thus given here. In this approximation, we pretend that ∆VDigiOS and
∆σtotal are independent. With this assumption, we can calculate worst-case supply
sensitivity, ∆VOS,SUP, by:
( ) ( )22, totalDigiOSSUPOS VV σ∆+∆=∆
Table 5 shows the results of ∆VOS,SUP at VCM=1.2V for all 4 comparators.
Comp1 Comp2 Comp3 Comp4 Supply Sensitivity, ∆VOS,SUP*
13mV 18mV 22mV 16mV
*Worst-case supply sensitivity (±10% Change in Supply) measured at VCM = 1.2V Table 5 Worst-case Supply Sensitivity of Comp1 − Comp4
3.4 Speed
As described in section 2.3, speed of the core comparator is determined by the
speed of two phases, evaluation phase and reset phase. In evaluation phase, regeneration
time constant τ, tdelay (Equation 14), and t(@Vout=1.2V) (Table 1) characterize the evaluation
speed. In reset phase, reset time, treset, that is time required to reset a comparator whose
differential output decreases from full VDD to 0.5mV determine the reset speed. In this
60
section, the same measurements are repeated for each of the four comparators. The first
subsection compares the speed of different architectures. The second subsection discusses
the penalty on digital offset compensation. The last subsection compares the linear and
nonlinear scaling on digital compensation devices.
3.4.1 Comparison on Speed of Different Architectures
In each of the four architectures, the extra devices for compensation impact the
speed. Moreover, the comparator speed changes with the digital offset compensation
settings. Therefore, in this section, speed of 4 comparators with zero digital offset will be
first compared to the original speed of the core comparator. The effects of different
digital settings will be presented next.
Digital Offset Compensation Off
Evaluation Phase Reset Phase Architecture τ(ps) tdelay(ps) T(@Vout=1.2V) (ps) fmax,eva (GHz) treset (ps) fmax,rst (GHz)Core Comp 32.9 24.6 176 2.84 174 2.88 Comp1 36.8 38.6 211 2.37 201 2.49 Comp2 33.1 47.8 200 2.50 181 2.77 Comp3 33.9 53.2 210 2.38 173 2.89 Comp4 33.5 58.8 211 2.37 199 2.51
Table 6 Speed Comparisons with Digital Offset Compensation Off
Turning digital offset compensation off means setting digital offset be zero. In
order words, D4D3 D2D1=0000 or D4BD3B D2BD1B=1111 in the case of Comp4. In Table 6,
data for “Core Comp” is repeated from the speed of core comparator with the following
configuration: Vcm=1.2V, Mclk=4×, M1,2=2×, M3,4=1×, RST5=1×, RST1,2=1×, RST3,4=1×,
and RST6=0×. For evaluation phase, digital offset compensation architectures impact the
61
speed of core comparator by 15%. This is expected because the digital compensation
devices contribute parasitic capacitance and slow down the comparison. Among four
architectures, Comp2 is fastest with digital offset compensation off. Reset devices are
intentionally made stronger, specifically, RST3,4=1.5×, RST6=1.5× and additional reset
like RST7 and M7 (see schematic of Comp1-4). The reset speed of Comp1 – Comp4 is
optimized under the condition when digital offset compensation is on. The reset devices
are carefully sized so that the reset speed and evaluation speed is similar, as shown in
Table 7 in the next subsection. Hence when digital offset compensation is off, the reset
speed is faster then the evaluation speed. Also, we know the reset speed with digital
offset compensation off is so fast that it will not be the limiting factor of the speed of the
comparator.
Digital Offset Compensation On
Evaluation Phase Reset Phase Architecture τ(ps) tdelay(ps) T(@Vout=1.2V) (ps) fmax,eva (GHz) treset (ps) fmax,rst (GHz)Core Comp 32.9 24.6 176 2.84 174 2.88Comp1 35.8 72.4 238 2.10 218 2.29Comp2 34.5 65.1 224 2.23 229 2.19Comp3 32.7 37.8 189 2.65 191 2.62Comp4 36.6 66.8 232 2.15 231 2.17
Table 7 Speed Comparisons with Digital Offset Compensation On
When digital offset compensation is turned on, all digital compensation devices
are on. Since the speed of a comparator depends on input magnitude, we must make sure
that the input magnitude in this section is the same as that of last section. To do so, we
must force the comparators to have zero input referred offsets. Therefore, while we turn
on digital compensation devices, dummy devices, which include MOS0 (Comp2 and
62
Comp3) and MC0 (Comp4), are turned on at the same time to balance the comparator. In
short, digital settings will be D4D3 D2D1=1111 for Comp1, 2, and 3 or D4BD3B
D2BD1B=0000 for Comp4, and dummy devices are turned on as if they were connected to
D1 or D1B.
With digital offset compensation, more parasitic capacitance is added to the
comparator, so the evaluation speed of Comp1, Comp2, and Comp4 slow down by 24%
compared to the core comparator. However, Comp3 is only 6.7% slower than the core
comparator because Comp3 increases the total tail current. Reset speed is designed to be
closed to the evaluation speed for optimizing the sampling rate.
With the sampling rate under conditions of offset compensation on and off, we
found that the maximum overall sampling rate of Comp1, Comp2, and Comp4 is limited
by compensation on condition, whereas overall sampling rate of Comp3 is limited by
compensation off condition. The maximum overall sampling rates of all architectures are
listed in Table 8. The percentage reduction on sampling rate compared to CoreComp is
listed in the last column. Overall, digital offset compensation reduces the sampling rate of
a comparator by 15% – 25%.
Architecture Sampling Rate (GHz)
Sampling Rate Reduction (%)
Core Comp 2.84 0% Comp1 2.10 –26% Comp2 2.19 –23% Comp3 2.38 –16% Comp4 2.15 –24%
Table 8 Maximum Sampling rate of different architecture
63
3.4.2 Speed Penalty of Digital Offset Compensation
This section only applies on Comp1, Comp2, and Comp4; Comp3 is actually
faster when digital offset compensation is on because of its split current architecture. The
speed penalty of Comp1, Comp2, and Comp4 is caused by several factors. The dominant
factor is the extra parasitic capacitances due to digital compensation devices, which have
been discussed in the last subsection. Another factor is the decrease in input
transconductance, gm,in, of Comp1,2,4 with increasing digital offset. The decreasing gm,in
degrades the integrating factor, and thus the evaluation response is degraded. We will
carefully examine why input transconductance reduces in this section.
Loss in Input Transconductance, gm,in
Figure 37 Illustration of input transconductance loss
In Comp1, Comp2, and Comp4, the common idea is to add some devices to
influence the current steering of input devices M1,2. Let us take a simple differential pair
and add an extra device to draw a constant current on one side, as shown in Figure 37.
Assume the current through the extra device is a fraction of ISS, say αISS, where α ≤ 12 .
For comparator, the only important operating point is where the differential output
current crosses zero, i.e. I1 = I2. In addition, total tail current is ISS. Hence, IM2 = 0.5ISS,
M1 WL
M2WL
VCM + ∆Vin2 VCM – ∆Vin
2 MOS
IM1 IM2 αISS
I1 I2
VCM
ISS
64
and IM1 = (0.5 – α) ISS. Small differential voltage ∆Vin is applied to the inputs, creating
small differential current idiff.
∆−−
∆
+=−=22 2121
inm
inmSSdiff
Vg
VgIiii α
( )221
inmmSSdiff
VggIi
∆++=α
We can then find gm1 and gm2 by substituting IM1 and IM2.
( ) ( )2
5.025.02 inSSOXnSSOXnSSdiff
VI
LWCI
LWCIi
∆
+−+= µαµα
Equation 15 ( ) ( ) inSSOXnSSdiff VI
LWCIi ∆
+−+= 5.022
121 µαα
If α = 0, then inSSDmdiff VIIgi ∆== )5.0(2,1 , which is the case without digital offset
compensation. In Equation 15 the first term αISS is the offset created by MOS, and the
fraction ( )2
121 +− α is the factor of loss in input transconductance, gm,in. If α is small,
we can approximate the fraction ( )2
121 +− α with first order Taylor series, which gives
− α
211 . This means that if a fraction α of ISS is used in digital offset compensation, the
input transconductance is lost by 12 α. This also tells us that a comparator with larger
offset will have a slower speed, even though parasitic is not taken into account.
Furthermore, the input referred noise will increase as digital offset increases.
65
3.4.3 Comparison on Linear and Non-linear scaling
When Comp1 was being designed, we found that a linear 4-bit scaling on digital
offset compensation severely degraded the comparator performance. In this section, we
will compare Comp1 with 3-bit linear scaling as shown in Figure 38, with 4-bit linear
scaling (schematic is same as Figure 38 except that one more bit correction is needed),
and with 4-bit non-linear scaling as shown in Figure 20. Hence, we know how well the 4-
bit non-linear scaling improves the performance.
Figure 38 Schematic of Comp1 with 3-bit linear scaling
Evaluation Phase Reset Phase Architecture τ(ps) tdelay(ps) T(@Vout=1.2V) (ps) fmax,eva (GHz) treset (ps) fmax,rst (GHz) 3-bit Linear 34.7 73.0 233 2.15 216 2.32 4-bit Linear 42.8 106.9 310 1.62 383 1.31 4-bit Non-linear 35.8 72.4 238 2.10 218 2.29
Table 9 Speed Comparisons on linear and non-linear scaling of Comp1
RST2 42
RST1 42
M642
M1 82
M5 42
M282
Mclk 162
RST6 42
M3 42
M442
RST5 42
Vin1 Vin2
clk
RST4 42
RST3 42
clk
VDD
clk clk
Vout1 Vout2
Invbot2 Invbot1 ×2 ×1 ×1
×1 ×1 ×2
VCM
D1 D2
×4
×4
D3
VCM
66
From Table 9, 4-bit linear scaling version performs poorly in both evaluation
phase and reset phase. Both speeds are almost half of the speeds that the 3-bit version has.
In the 4-bit non-linear version, the performance is very closed to that of the 3-bit linear
version. Moreover, we expect that the power consumption of the 4-bit non-linear version
is similar to that of the 3-bit linear version as well. With the speed and power benefit, we
decided to use the 4-bit non-linear version and sacrifice 0.5LSB nonlinearity as shown in
Figure 28.
After comparing the speeds for digital compensation both off and on and
understanding the origin of speed penalty of digital offset compensation, we know that
digital offset compensation could reduce the speed by 15% – 25%. We can improve the
speed by changing the digital coding scheme. In the current setting, we control the whole
(both left and right) digital compensation in a single binary array, and the worst case is
during compensating for −1LSB offset, which corresponds to turning on all compensation
devices. As a result, all parasitic capacitances due to digital compensation are added to
the comparator and large portion of total current is used for offset compensation. On the
other hand, if we choose to control the left and right digital compensation separately,
which means we need digital signal D3L D2L D1L for left and another D3R D2R D1R for right
hand side, the worst-case becomes turning on all devices on one side only. Since we
reduce the number of active devices by half, we halve not only parasitic capacitance but
also the current flowing through digital compensation devices. The loss in input
transconductance is also reduced, so the speed of the comparator can be improved.
67
3.5 Input Capacitance
As shown in schematics Figure 20 − Figure 23, all four comparators do not
increase input capacitance. However, Comp1 and Comp2 need an extra terminal VCM.
Depending on applications, an extra driver may be needed to generate VCM. Fortunately,
VCM is a DC value or a low frequency signal. Hence, extra driver can be simple.
In applications of high order parallelism, the VCM driver is usually shared among all
comparators. The little extra hardware on VCM driver and the small input capacitance
make the digital offset compensation attractive in applications with high order parallelism.
3.6 Power Consumption
Similar to the speed issue, power consumption of each comparator is more than
that of core comparator, since digital offset compensation devices add parasitic
capacitance on the comparator. In the first subsection, power consumption of each
comparator is compared with that of core comparator. As in the speed section, we
separate our discussion into 2 cases. The first case is when digital offset compensation is
off, and the second case is when digital offset compensation is on. Clock loading and
power consumed on driving clock is discussed in the second subsection. The total power
of comparator and clocking will be discussed in the last subsection.
3.6.1 Power of Comparators
Digital Offset Compensation Off
When digital offset compensation is off, the comparator’s switched
68
capacitance does not include the channel capacitance; only source/drain overlap
capacitances are added to the comparator. The power consumption is, thus, closed to the
power consumption of the core comparator. Figure 39 shows power consumption of all
comparators, under the condition of digital offset compensation off, operating at 1.5GHz,
1.8V supply. Comp2 and Comp3 have similar power consumptions, which are closed to
that of core comparator. However, Comp4 dissipates more power because both source
and drain overlap capacitances are added on node invbot1,2. Comp1 has the largest power
consumption because MCM1-6 are always on, and thus capacitances CgdMcm1-6, CgsMcm1-6,
and CgdMos1-6 are added to invbot1,2. As a result, power consumption of Comp1 is largest.
Digital Offset Compensation On
When digital offset compensation is on, more capacitances are added on the
comparator. The power consumption thus increases. Figure 40 shows the power
consumption of all comparators operating at 1.5GHz, 1.8V supply. Comp4 is
interestingly the lowest power consuming. The reason is that Comp4 uses the smallest
size devices for digital offset compensation, its overlap capacitance plus the gate
capacitance is thus the smallest. Comp3 is the second least power consuming, because
again the digital compensation devices are smaller than that of Comp1 and Comp2.
Comp1 and Comp2 have comparable power consumptions. Note that by adding digital
offset compensation, the power consumption is at least double to that of core comparator.
69
0.8 1 1.2 1.4 1.6 1.850
100
150
200
250
300
Input Vcm (V)
Pow
er (
uW)
Power Consumption with Digital Compensation Off
CoreCompComp1 Comp2 Comp3 Comp4
Figure 39 Power Consumptions with Digital Offset Compensation Off
0.8 1 1.2 1.4 1.6 1.850
100
150
200
250
300
350
Vcm (V)
Pow
er (
uW)
Power Consumption with Digital Compensation On
CoreCompComp1 Comp2 Comp3 Comp4
Figure 40 Power Consumptions with Digital Offset Compensation On
70
By noticing the increase in power consumption when digital compensation is on,
we again suggest to control the left part and right part of digital compensation separately.
As we explained at the end of speed section, by turning on only left or right devices, we
halved the extra parasitic capacitance, and thus the power consumption can be greatly
reduced.
3.6.2 Power of Clocking
Power of clocking is mainly due to charging and discharging the clock load
capacitance. Thus, to find the power consumed on driving the clock, we can simply find
the clock load capacitance. Table 10 shows the clock load capacitance of each
comparator, and the corresponding clocking power. Power calculation is based on 1.8V
supply operating at 1.5GHz. It is obvious that Comp1, Comp2, and Comp4 have the same
clock load capacitance. Comp3 has large clock load capacitance because of its digital
offset compensation structure.
Core Comp Comp1 Comp2 Comp3 Comp4 Clock Load Capacitance
10.9fF 12.5fF 12.5fF 37.6fF 12.5fF
Clocking Power
52.9µW 60.8µW 60.8µW 183µW 60.8µW
Table 10 Power of Clocking
71
3.6.3 Total Power
The total power is calculated by summing the power of comparator itself and
power of clocking. Figure 41 shows the total power consumption when digital
compensation is off; Figure 42 shows the total power consumption when digital
compensation is on. Again, operating condition is 1.8V supply, 1.5GHz clock. Since
clocking power of Comp3 is much larger than others, Comp3 becomes the most power
consuming comparator among four architectures. Comp2 is the least power consuming
when digital compensation is off, and Comp4 is the least power consuming when digital
compensation is on. Overall, digital offset compensation increases the power
consumption by 60% to 160%, greatly depending on the choice of architecture.
0.8 1 1.2 1.4 1.6 1.8100
150
200
250
300
350
Input Vcm (V)
Tot
al p
ower
(uW
)
Total Power Consumption with Digital Compensation Off
CoreCompComp1 Comp2 Comp3 Comp4
Figure 41 Total Power Consumption with Digital Compensation Off
72
0.8 1 1.2 1.4 1.6 1.8100
150
200
250
300
350
400
450
500
Vcm (V)
Tot
al P
ower
(uW
)
Total Power Consumption with Digital Compensation On
CoreCompComp1 Comp2 Comp3 Comp4
Figure 42 Total Power Consumption with Digital Compensation On
73
3.7 Quick Summary of Comparison
In summary, we have compared the performances of 4 digital offset compensation
architectures. Offset compensation ability, supply sensitivity, speed, input capacitance,
and power have been compared in detail. Table 11 shows the summary of the
performances. Comp1 and Comp2 are suitable in high accuracy applications, while
Comp4 is suitable in low power system.
Performance Core Comp Comp1 Comp2 Comp3 Comp4 Worst-case Offset
60 – 140mV 8 – 14mV 8 – 13mV 7 – 65mV 9 – 21mV
Effective number of bit correction
N/A 3.5bit 3.5bit 3bit 3.2bit
Worst-case Supply Sensitivity on Offset*
10mV 13mV 18mV 22mV 16mV
Sampling Rate (%Reduction)
2.84GHz 2.10GHz (–26%)
2.19GHz (–23%)
2.38GHz (–16%)
2.15GHz (–24%)
Input Capacitance
1fF 1fF 1fF 1fF 1fF
Power** (% Increase)
142–175µW 213–390µW (50–120%)
238–400µW(67–129%)
328–460µW(130–160%)
168–280µW(18–60%)
*Worst-case supply sensitivity (±10% change in supply) measured at VCM = 1.2V ** Power consumption in VCM range 0.8V ≤ VCM ≤ 1.6V
Table 11 Performances Rating of Comparators
74
Chapter 4 Circuit Performance All four architectures have been fabricated in 0.18µm 1.8V CMOS technology. In
the test chip, each architecture is duplicated 20 times. As a result, there are 20 Comp1, 20
Comp2, 20 Comp3, and 20 Comp4 in the same chip. Thus, we are able to collect
statistical data from the chip. Since this project emphasizes on offset compensation, only
offset of the comparators have been measured.
4.1 Accuracy
In each of the following subsections, we will present the measurements of internal
offset, digital offset, linearity of digital offset, and worst-case overall offset respectively.
4.1.1 Measured Internal Offset Due to Device Mismatches
As you can see from the schematics, Comp1, Comp2, and Comp4 share the same
core comparator, while Comp3 has split tail current architecture. Therefore, Comp1,
Comp2, and Comp4 have similar internal offset, while Comp3 has larger internal offset.
75
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6−200
−150
−100
−50
0
50
100
150
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Comp1 Internal Offset measurements
Data Points Average +/− 3 sigma Theoretical bounds
Figure 43 Measured Internal Offset of Comp1
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6−150
−100
−50
0
50
100
150
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Comp2 Internal Offset measurements
Data Points Average +/− 3 sigma Theoretical bounds
Figure 44 Measured Internal Offset of Comp2
76
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6−400
−300
−200
−100
0
100
200
300
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Comp3 Internal Offset measurements
Data Points Average +/− 3 sigma Theoretical bounds
Figure 45 Measured Internal Offset of Comp3
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6−250
−200
−150
−100
−50
0
50
100
150
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Comp4 Internal Offset measurements
Data Points Average +/− 3 sigma Theoretical bounds
Figure 46 Measured Internal Offset of Comp4
77
In the figures above, “Data points” represent the offset of each duplicated
comparator. Thus, there should be 20 data points at the same VCM. “Average” represents
the average value of all data points at that VCM. “+/− 3sigma” is the ±3 × (standard
deviation σ) calculated statistically from data points. “Theoretical bounds” is ±3 ×
(standard deviation σ) obtained from simulations. In all four figures above, we can see
that the internal offset tends to negative. This negative trend is mainly due to layout
asymmetry of the comparator itself. If you neglect the offset due to layout asymmetry, the
range of “+/− 3sigma,” which is obtained from real circuits, is closed to the range of
“Theoretical bounds,” which are obtained from simulations. This verifies that the analysis
in chapter 2 accurately predicts the offset of the comparator.
4.1.2 Measured Digital Offset Compensation
Since there is inaccuracy in the simulation model, the performance of the real
circuit implementation deviates from the simulations presented in Chapter 3. The errors
on estimating parasitic capacitance in simulations are typically high. The incorrect
parasitic capacitance model will lead to large performance impact in digital offset
compensation. This will be discussed in detail for each comparator.
Figure 47 shows the measured digital offset of Comp1. It is obvious that the
correction range obtained in measurements is larger than that in simulations. We found
that the simulations over-estimated the parasitic capacitance. As a result, all transistors in
real implementation have more drive strength than those in simulations. Consequently,
the digital offset magnitude of Comp1 in real circuits, which is shown in Figure 47,
78
covers a larger range than shown in the simulations of Figure 24. In addition to error in
correction range, simulated digital offsets increase fairly linearly with VCM, but measured
digital offsets are fairly constant over wide range of VCM. The intuitive understanding on
the structure of Comp1 actually predicts that the digital offset is quite insensitive to the
change in VCM. Comp1 stacks 2 transistors in series as if degenerating the top transistor
MCM1-6 by the bottom transistor MOS1-6 (see schematic Figure 20). As a result, the current
flowing through each branch is regulated by the small feedback mechanism. The created
offset is also regulated, and thus, the offset magnitude does not change rapidly over wide
range of VCM. This effect clearly shows up in Figure 47.
In addition, the drawback of Comp1 is its nonlinearly scaling devices on digital
offset compensation. It is expected that the LSB, D1 has different characteristic from
other bits do. Figure 47 shows that the offsets created by LSB, corresponding to all odd
digital levels, approach more to a constant than the offsets created by 2nd LSB,
corresponding to all even digital levels. It is because LSB is created by MCM1 and MOS1AB,
which form larger degeneration; thus the current flowing through the LSB branch is less
sensitive to VCM. The different behaviors between the 1st LSB and the 2nd LSB degrade
the linearity of the digital offset compensation. The linearity will be discussed in next
section.
79
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6−200
−150
−100
−50
0
50
100
150
200
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Comp1 Measured Digital OS compensations
7 6 5 4 3 2 1 0 −1−2−3−4−5−6−7
Figure 47 Measured Digital Offset of Comp1
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6−400
−300
−200
−100
0
100
200
300
400
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Comp2 Measured Digital OS compensations
7 6 5 4 3 2 1 0 −1−2−3−4−5−6−7−8
Figure 48 Measured Digital Offset of Comp2
80
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6−600
−400
−200
0
200
400
600
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Comp3 Measured Digital OS compensations
7 6 5 4 3 2 1 0 −1−2−3−4−5−6−7−8
Figure 49 Measured Digital Offset of Comp3
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6−40
−30
−20
−10
0
10
20
30
40
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Comp4 Measured Digital OS compensations
7 6 5 4 3 2 1 0 −1−2−3−4−5−6−7−8
Figure 50 Measured Digital Offset of Comp4
81
Figure 48 shows the measured digital offset of Comp2. The difference between
Comp1 and Comp2 is especially clear with measurements. Comp2 creates offset similar
to a β mismatch of M1,2. Notice the similarity of “beta1” in Figure 15 with Figure 48.
Note that simulation shown in Figure 25 incorrectly predicts that digital offset stays
constant in high VCM. The stronger drive strength in actual devices shows up clearly in
measured digital offset of Comp2 in Figure 48. In high VCM, the real measured digital
offset is larger than the simulated digital offset by more than 100%.
Figure 49 shows the measured digital offset of Comp3. The measured circuit
performance of Comp3 deviates the least from simulation results. The digital offset in
real implementation is only slightly larger than that in simulation. The large non-linearity
also clearly shows up in real circuits.
Figure 50 shows the measured digital offset of Comp4. The inaccurate parasitic
capacitance model affects the performance of Comp4 the most. All capacitances due to
MC0-4 are smaller in the fabricated chip; thus, smaller offsets are resulted. In Figure 50,
the maximum digital offset created by Comp4 is only about 40mV, while simulation
expects the maximum digital offset of more than 200mV. Because of the small magnitude
of digital offset, the finite precision of the equipments leads to difficulties in offset
measurements. Figure 50 shows the measured digital offset of Comp4 with large
measurement uncertainty. By carefully inspecting all 16 digital offset levels, level 3 (3
LSB) and level 4 (4 LSB) cross over with each other. We suspect that the dummy
capacitor MC0 in Figure 23 does not match with other capacitors in layout. The same
problem occurs in –4 and –5, which is caused by the same transition from 3LSB to 4LSB.
82
4.1.3 Linearity
Linearity will directly affect the effective number of bits correction. DNL of each
comparator is calculated from the digital offset measurements in the previous section, and
the DNL profiles are shown in Figure 51 − Figure 54.
The measured DNL of Comp1 increases to 1 LSB. However, if VCM is below 1.4V,
the DNL is less than 0.8 LSB. This suggests that it is better to operate Comp1 at low or
moderate VCM. Note that the “zig zag” pattern shows up in measurement as well.
Unlike digital offset measurements, measured DNL of Comp2 is much more
similar to the simulation results. From Figure 52, we confirm that Comp2 has DNL
approximately 0.5 LSB, and is the best among four comparators.
Comp3 has the worst DNL profile, as predicted in simulations. In real circuits, the
worst DNL is almost 1.5 LSB. Simulations can also predict the compression of the step
size of offset compensation. The measured DNL profile of Comp3 is also very similar to
the simulation results.
With a lot of difficulties in precise measurements, the measured DNL profile of
Comp4 is not very meaningful. Thus, we will not have further discussion on this.
83
−8 −6 −4 −2 0 2 4 6 8−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
Digital Level, W
Offs
et D
NL
(LS
B)
Comp1 Measured Digital Offset DNL
vcm=0.8vcm=1.0vcm=1.2vcm=1.4vcm=1.6
Figure 51 Measured DNL of Comp1
−8 −6 −4 −2 0 2 4 6 8−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
Digital Level, W
Offs
et D
NL
(LS
B)
Comp2 Measured Digital Offset DNL
vcm=0.8vcm=1.0vcm=1.2vcm=1.4vcm=1.6
Figure 52 Measured DNL of Comp2
84
−8 −6 −4 −2 0 2 4 6 8−1
−0.5
0
0.5
1
1.5
Digital Level, W
Offs
et D
NL
(LS
B)
Comp3 Measured Digital Offset DNL
vcm=0.8vcm=1.0vcm=1.2vcm=1.4vcm=1.6
Figure 53 Measured DNL of Comp3
−8 −6 −4 −2 0 2 4 6 8−2
−1.5
−1
−0.5
0
0.5
1
1.5
Digital Level, W
Offs
et D
NL
(LS
B)
Comp4 Measured Digital Offset DNL
vcm=0.8vcm=1.0vcm=1.2vcm=1.4vcm=1.6
Figure 54 Measured DNL of Comp4
85
4.1.4 Worst-case Overall Offset
When four comparators have similar range of digital offset compensation, DNL
and worst-case overall offset give the same results. However, since four comparators in
this test chip have different ranges of corrections, worst-case overall offset is eventually
the most important metric and it tells which comparator has higher accuracy.
In Figure 55 – Figure 58, “Worst-case offset” is the worst possible offset of a
comparator, and it is calculated by finding the biggest separation between two digital
levels in measured digital offset from Figure 47 – Figure 50. “Data Points” are the actual
offset of the duplicated comparators on chip after digital offset compensation. As a result,
all “Data Points” are bounded by the “Worst-case offset.”
In Figure 58, there are only 3 “Data Points” for offset of Comp4, because Comp4
has very limited correction range, and most duplicated comparators have offset larger
than its correction range. We can find only 3 comparators that have small enough offset
to compensate.
Finally, Figure 59 shows the worst-case offsets of all four comparators in one plot.
Since Comp4 has too narrow correction range, we will neglect Comp4. Comp1 provides
lowest offset in this test chip. Because of the inaccurate capacitance model in simulations,
Comp2 has larger worst-case offset than expected. Comp3 still performs the worst in
offset compensation.
86
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6−25
−20
−15
−10
−5
0
5
10
15
20
25
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Comp1 Measured Offset after Digital compensation
Worst−case OffsetData Points
Figure 55 Measured Offset of Comp1 after Digital Compensation
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6−40
−30
−20
−10
0
10
20
30
40
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Comp2 Measured Offset after Digital compensation
Worst−case OffsetData Points
Figure 56 Measured Offset of Comp2 after Digital Compensation
87
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6−80
−60
−40
−20
0
20
40
60
80
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Comp3 Measured Offset after Digital compensation
Worst−case OffsetData Points
Figure 57 Measured Offset of Comp3 after Digital Compensation
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6−8
−6
−4
−2
0
2
4
6
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Comp4 Measured Offset after Digital compensation
Worst−case OffsetData Points
Figure 58 Measured Offset of Comp4 after Digital Compensation
88
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.60
10
20
30
40
50
60
70
80
Vcm (V)
Mea
sure
d O
ffset
, (m
V, d
iff)
Measured Worst−case Overall offset
Comp1Comp2Comp3Comp4
Figure 59 Comparison on worst-case offset
89
Chapter 5 Applications of Comparators
The comparators designed in this project are optimized for high order parallelism.
For example, flash ADC or over-sampler usually require a large number of comparators
in parallel in the first stage. Thus, the comparators should have small input capacitance,
low power consumption. For ADC design, comparator must fulfill the accuracy
requirement as well. In the coming section, a brief ADC design example is shown for
illustrating the application of comparators with digital offset compensation.
5.1 Application of Comparators on Multiphase Flash ADC
Figure 60 Block Diagram of Multiphase Flash ADC
To illustrate the application of comparators on Flash ADC architecture, we are
going to design a N bit multiphase flash ADC. In a single-phase flash ADC, we need to
•
•
φ1
N-bit
ADC
N
φ2
N-bit
ADC
N
φP
N-bit
ADC
N
Vin
VFS
•
•
COMP
COMP
COMP
COMP
Vin
clk
2N
90
place 2N comparators in parallel in the first stage. To push the speed performance, we
place, for example, p single-phase flash ADC in parallel. Each flash ADC is triggered by
different phase, φ1, φ2,…φP. The block diagram is shown in Figure 60.
First of all, we need to design a comparator with required accuracy. Since we
know we are going to place a large number of comparators in parallel in the first stage,
we use small transistor size for input device M1,2. With a designed input device size, say
minimum size or 2× minimum size, we know the maximum offsets due to device
mismatch by using techniques developed in chapter 2. By applying digital offset
compensation, we can reduce the input referred offset to fulfill the required accuracy. In
short,
scorrectionbitsofnumberEffectiveV
V mismatchOSoverallOS
,, =
Effective number of bits corrections depends on DNL of offset compensation, which is
explained in chapter 3. After number of bits corrections on offset is designed, we can
design appropriate reset devices. The design of a comparator ends at this point. We can
then obtain the performance metrics of the comparator, especially speed of comparator
fcomp, by simulations.
After the design of the comparator is done, we can obtain the sampling frequency
by modeling the sampling action as a simple RinCin circuit, where Rin = 25Ω for end
termination configuration, and Cin is the sum of capacitances due to pads, channel, and
input capacitance of comparators. Since there are 2N comparators in a single-phase flash
ADC and there are p flash ADC in parallel, we have total (2N)p comparators connected to
91
the input. Thus,
Equation 16 Cin,total = Cpad + (2N)(p)Cin,comp ,
where Cpad includes any fixed capacitances due to pads, channels, etc., and Cin,comp is the
input capacitance of the comparator. For proper operation, we need to let input voltage
settle within 0.5 LSB = VFS2N+1 , where VFS is full-scale voltage of ADC. The settling time,
which is equal to the sampling time TSAMP, can be calculated by
( ) ininSAMPNCR
T
CRNTe inin
SAMP
12ln2
11 +=⇒≤ +
−
As a result, sampling frequency is
Equation 17 ( ) ininSAMPSAMP CRNT
f12ln
11+
==
Meanwhile, comparators can only operate up to its maximum speed, fcomp. Thus the
maximum operating frequency of p-phase flash ADC, fADC, = p×fcomp. Both fADC and fSAMP
depend on p, and they set the speed bounds of the ADC, as shown in Figure 61.
When p < po, fADC limits the speed of the ADC; when p > po, fSAMP limits the
maximum speed. The optimum speed is where fADC = fSAMP. This sets a quadratic equation
for p.
( ) inincompSAMPADC CRN
pfff12ln
1+
=⇒=
Equation 18 ( ) ( ) ( ) 012ln12 2
, =+
−+compin
padcompinN
fRNpCpC
92
Speed of 6-bit p-phase Flash ADC
po0
2
4
6
8
10
12
14
0 2 4 6
Number of parallel ADC, p
Spee
d (G
S/se
c)
fadcfsamp
Figure 61 Speed of 6-bit p-phase Flash ADC
Hence, we can always solve for Equation 18 to obtain the optimum speed of a p-phase
flash ADC. The optimum speed can tell us the fundamental speed limit of a p-phase flash
ADC architecture. This is just a simple example, as we can still increase the performance
by using a multistage ADC to decrease the total input capacitance, or by using distributed
capacitance technique to increase the input sampling bandwidth. More design issues on
those techniques seem out of scope of this paper.
93
Chapter 6 Conclusion
This project can be mainly divided into 3 big sections. The 3 sections are
characterization of core comparator (Chapter 2), comparison of comparators with digital
offset compensation (Chapter 3), and chip performance (Chapter 4).
In the first section, (Chapter 2), core comparator is characterized. The
performance metrics of a comparator are input referred offset, supply sensitivity, speed,
input capacitance, and power. A set of formulas is developed to calculate input referred
offset, and we identify the 6 different sources that contribute to offsets, and we
understand how each source varies with VCM. We are able to roughly estimate the supply
sensitivity on offset, so we know the fundamental limit of the accuracy of a comparator.
We know how to size the transistors to achieve higher speed on both evaluation and reset.
In addition, this architecture has small input capacitance and power consumption [2].
With these metrics, we can compare comparators with different architectures,
comparators with different offset compensation, and the tradeoffs of using digital offset
compensation.
In the second section (Chapter 3), we compare four comparators with different
digital offset compensation. Based on the performance metrics developed in chapter 2,
we created Table 11 to summarize the comparison of digital offset compensation. Comp2
has the best offset compensation ability because of its linearity, while Comp4 is a good
alternative because of its low power consumption. In general, digital offset compensation
can reduce the input referred offset from 140mV to 13mV. Effective number of bits
94
correction can be ranged from 3 – 3.5 bit from a 4-bit architecture. Input capacitance is
less than 1fF. By adding digital offset compensation, the sampling rate is only reduced by
15 – 25%, and power consumption increases by 60 – 160%.
In the third section (Chapter 4), all four comparators are implemented in 0.18µm,
1.8V CMOS technology. Since this project emphasizes on offset compensation, only
offset measurements are performed. We verified that the analysis for internal offset could
predict the offset of a comparator. We found that simulations over-estimated the parasitic
capacitance; thus, transistors have more drive strength. As a result, Comp1, Comp2, and
Comp3 have offset correction range larger than that obtained from simulations; however,
Comp4 has offset correction range less than expected. In addition, Comp2 gives the best
DNL (0.5LSB), and Comp3 gives the worst DNL (1.5LSB).
In the end of this project, we also give a simple example to illustrate how to apply
comparators with digital offset compensation in real implementation. We have developed
a method to design transistor size of comparators and number of bit corrections for
comparators. Moreover, we are able to find the optimum speed of a p-phase flash ADC.
With this example, we showed that comparators with digital offset compensation have
high potential on applications with high order parallelism.
95
Reference
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[2] Razavi, B.; Wooley, B.A., "A 12-b 5-Msample/s two-step CMOS A/D converter," IEEE Journal of Solid-State Circuits, vol.27, (no.12), Dec. 1992. p.1667-78.
[3] Dobberpuhl, D.W., "Circuits and technology for Digital's StrongARM and ALPHA microprocessors [CMOS technology]," Seventeenth Conference on Advanced Research in VLSI, IEEE Comput. Soc, 1997. p.2-11. ix+322 pp.
[4] Razavi, B., “Principles of Data Conversion system Design,” IEEE Press, pp. 177-81, 1995.
[5] Sakurai, T., "Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFETs," IEEE Journal of Solid-State Circuits, vol.23, (no.4), Aug. 1988. p.901-6.
[6] Ellersick, W.; Yang, C.-K. K.; Horowitz, M.; Dally, W., "GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link," 1999 Symposium on VLSI Circuits Digest of Papers, June 1999, pp. 49-52.
[7] Weinlader, D.; Ho, R.; Yang, C.-K. K.; Horowitz, M., "An eight channel 36 GSample/s CMOS timing analyzer," 2000 ISSCC Digest of Technical Papers, Feb 2000, pp. 170-1.
[8] Lee, M.-J.E.; Dally, W.; Chiang, P., "A 90 mW 4 Gb/s equalized I/O circuit with input offset cancellation," 2000 ISSCC Digest of Technical Papers, Feb 2000, pp. 252-3.