Agilent ParBERT 81250 Parallel Bit Error Ratio Testercc.ee.nchu.edu.tw/~aiclab/public_htm/Tools/measurement/... · 2007. 9. 6. · Generator Formats DNRZ, RZ, R1 2.7G:DNRZ DNRZ, separate

Agilent ParBERT 81250Parallel Bit Error Ratio TesterProduct OverviewVersion 5.51

The Only Parallel Bit Error Ratio Solutionfor testing at 675 Mbit/s, 1.65 Gbit/s, 2.7 Gbit/s, 3.35 Gbit/s, 7 Gbit/s, 10.8 Gbit/s, 13.5 Gbit/s and 45 Gbit/s

Agilent ParBERT 81250

ParBERT 81250 also providesdata and control signals fortheDUT if required.

The ParBERT Software Suiteis a ready-to-use package, whichoffers different levels of measure-ment analysis:1. Fast pass/fail measurementsideal for production2. Output Timing measure-ments provide results for setup& hold times, skew betweenchannels, phase margins,detailed Jitter results(RJ/DJ/TJ), and eyeopening specification results3. Output level measurementsprovide results for high/lowlevels, amplitudes, thresholdmargins and Q-factor analysis4. Graphical results fordetailed root cause analysis -see trends clearly and fast, e.g.color and contour plots.

Agilent ParBERT 81250 isparticularly suitable for the fol-lowingapplications:

10.8 Gb/s675 Mb/s 2.7/1.6 Gb/s 45 Gb/s3.35 Gb/s

E4805B/08A

Standard/

High

Performance

ClockModule

E4832A

675 Mb/s

Module

E4861A

2.7 Gb/sModule

E4838A

675 Mb/s

Generator

E4835A

675 Mb/s

Analyzer

E4862A/64A/63A/65A

2.7/1.6 Gb/s

Generator/Analyzer

E4862B/63B

3.35 Gb/s

Generator/Analyzer

E4866A

10.8 Gb/s

Generator

Module

E4867A

10.8 Gb/sAnalyzer

Module

E4861B

3.35 Gb/s

Module

E4810A

3.35 Gb/s

Electrical/Optical

Generator Module

E4811A

3.35 Gb/s

Optical/Electrical

Analyzer Module

E4896A 45 Gb/s Pattern Generator Bundle

E4867A 45 Gb/s Error Detector BundleE4883A Lightwave Transmitter Module

E4882A Lightwave Receiver Module

E4884A High Performance Lightwave Option

Modules

Front Ends

13.5 Gb/s

N4872A

13.5 Gb/s

Generator Module

N4873A

13.5 Gb/s

Analyzer Module

Agilent ParBERT 81250 is a modularparallel electrical and optical biterror ratio (BER) test platform, whichworks up to 45 Gbit/s. The ParBERT81250 platform comprises modulesthat work at 675 Mbit/s, 1.65 Gbit/s,2.7 Gbit/s, 3.35 Gbit/s, 7 Gbit/s, 10.8 Gbit/s, 13.5 Gbit/s and 45 Gbit/s. The system generatespseudo random word sequences(PRWS), standard pseudo randombinary sequences (PRBS) and user-defined patterns on parallel lines.You can analyze bit error ratios withuser defined patterns, PRBS/PRWSor mixed data (a combination ofuserdefined patterns and PRBS).

ParBERT 81250 is a perfect fitfor parallel-to-serial, serial-toparallel, serial-to-serial andmultiple serial BER test.Examples comprise multiplexerand demultiplexer(Mux/Demux) - or SerDes(serializer/deseralizer) - testingused in telecom and storagearea network (SAN) ICs, multi-ple transmitter and receivertesting in manufacturing,amplifiers as well as 10GbEand forward error correction(FEC) device testing.

1. 10GbE device testing2. Multiplexer andDemultiplexer Test- OC-768 device testing: Youcan test 16:1 and 4:1 40Gdevices using the ParBERT81250 45G and either 3.3Gbit/s or 10.8 Gbit/s modules- OC-192 device testing: TheParBERT 81250 10.8 Gbit/smodules enable testing ofthe serial high-speed side ofMuxes/DeMuxes. Combinedwith 675Mbit/s, 1.6Gbit/s,2.7Gbit/s or 3.3 Gbit/s modulesyou can test both sides ofmul-tiplexers/demultiplexers- OC-48 device testing3. Characterization of SAN ICs4. Manufacturing Test of multiple Transmitters, Receivers,Transceivers and Amplifiers5. FEC Device Test

For more information on these appli-cations, please see brochure p/n5968-9250E. For information on theAgilent ParBERT 81250 45 Gbit/s,please see p/n 5988-3020EN. Formore information on ParBERT 3.35Gbit/s optical/electrical modules,please see p/n 5988-5901EN. Thisdocument focuses on theParBERT platform up to 10.8 Gbit/s.

Figure 1: ParBERT Product Family

Page 2/58 ParBERT Main Overview

FeaturesModular, flexible and scalable platform architecture· Up to 128 channels @ 675 Mbit/s· Up to 64 channels @ 3.35 Gbit/s, 2.7 Gbit/s· Up to 30 channels @13.5 Gbit/s, 10.8 Gbit/s, 7 Gbit/sGenerator and Analyzer modules available from 675Mbit/s up to 45 Gbit/sMix of channels (generator/analyzer) and speed classes

Generate pseudo random word sequences (PRWS) andstandard PRBS up to 231-1; Analyze bit error ratios withuser- defined data, PRBS or mixed data from parallel portsGenerate and analyze single-ended, low voltage anddifferential signals - including true differential

Data generation and analysis with sequencing and looping

Auto phase & auto delay alignment

Each generator or analyzer channel has independentprogrammable control of voltage levels and timing delay

Interrupt-free change of analyzer delay/generatordelay (13.5 Gbit/s, 7 Gbit/s and 3.35 Gbit/s; other speedclasses generator only)Jitter modulation (13.5 Gbit/s, 7 Gbit/s and 3.35 Gbit/s)Variable Cross (13.5 Gbit/s, 7 Gbit/s and 3.35 Gbit/s)Windows XP®/Windows 2000®/NT 4.0 operating systems

Plug and play drivers

Measurement Suite

Benefits· Grows with customer’s test and application needs· Covers a wide range of technologies and applications

Allows system configurations perfectly meeting cus-tomer’s application needsProvides unique flexibility to test complex devices withmany channels and/or frequencies, e.g. Serial bus appli-cations, Mux/Demux (SerDes), FECPerform parallel BER measurements - ideal forMux/Demux applications

· Test logic technologies e.g. LVDS, ECL, PECL, SSTL-2· Generate the necessary signals to perform margin

tests, emulate frequency and level changes and stress your device as far as possible

· Generate complex sequences that contain memory-based (up to 64Mbit) and/or PRBS/PRWS data

· Generate data packets with header and payload· React to control signals from the DUT· Auto alignment of expected data with incoming data· Save time as you do not need to find the correct sam

ple point manually - typically takes just 100ms.Allows device characterization for a wide range of tech-nologies/ applications in the semiconductor and com-munication industryContinuous running signals for measurements wherechanging analyzer delay is necessary

Allows jitter tolerance testing to be performedProvides real-world stressProvide “standard” and “detailed” views for performingmeasurements fast and efficientlyAllows remote access and simplifies remote programdevelopment· DUT output timing measurement - bathtub curve with

jitter analysis (RJ/DJ separation), skew between channels, setup and hold times

· Output level measurement - amplitude information,high/low level and Q-factor

· Eye opening measurement - color and contour plots· Fast eye mask measurement - automatic threshold

adjust, fast and efficient insights for manufacturing test· Comprehensive BER measurement - actual and accu

mulated BER, errors of ones and zeros, total bits transferred and file capturing for post-processing analysis.

· Spectral Jitter

ParBERT 81250 Key Feaures & Benefits

ParBERT Main Overview Page 3/58

Key Features(Continued)

Perform Parallel BERmeasurements up to13.5 Gbit/sParBERT 81250 makes testingof Mux/Demux (serializer/deserializer) devices easier.Only ParBERT 81250 is able togenerate pseudo-random-wordsequences (PRWS) on the par-allel side and analyze bit-errorratios with user-definedpatterns, PRBS up to 231-1 orboth combined.

PRBS/PRWS and memorycapabilityThe polynomial 2n-1, the PRBSalgorithm and the parallel buswidth define PRWS. The bitsof the PRWS are assigned toparallel lines and are thenmultiplexed to form a PRBS(see figure 3).

Auto phase and auto delayalignmentAs the latency from the inputto the output is often notknown exactly, or it is notdeterministic, synchronizationbetween incoming data andoutcoming data has to be car-ried out. ParBERT 81250 hasthree capabilities to synchro-nize/align the incoming dataautomatically (see figures 4and 5):1) Data shift bit-by-bit ifPRBS is used2) Detect Word if user-definedpatterns are used3) Moving of the samplingpoint delay of the analyzer upto 10ns without stopping theinstrument. Moving of thesampling point delay can alsobe used in addition to thealignment of data patterns (1and 2) to refine the synchro-nization.

PRBS:

PRWS:

1

1

1

1

2

2

2

2

A

B

D

C

A

A

B

BD

D

C

C

Parallel:PRWS

Parallel:PRWS

Serial Link:PRBS 1

1

1

1

A

B

C

D

2

2

2

2

1 1 1 1 2 2 2 2Serial

1 1 1 1 2 2 2 2

1 1 1 1 2 2 2 2

1 1 1 1 2 2 2 2

Expected

1

2

N

…..

BER = .5

BER = .5

BER = 0

Loa d Ex pe ct e d

Che ck BER

BER = 0 BER > 0

Fou n d Pha se Ne x t Ex pect e d

GOTO me a su r eme n t

AB

DC

Parallel Serial

Figure 2: BER Results Screen

Figure 3: MUX/DEMUXApplication: Relationshipbetween PRBS and PRWS

Figure 5: Standard view when choosing PRBS/PRWS patterns and data syn-chronization mode

Figure 4: Mechanism of auto-phaseand auto-delay assignment


Interrupt-free change ofanalyzer delay

The analyzer delay can bechanged ±1 period whilst theinstrument is running withoutcausing it to stop see figure 6.The 13.5 Gbit/s, 7 Gbit/s and3.35 Gbit/s modules can dothis on the Analyzer andGenerator.

Multiple frequencies

The modular architecture ofParBERT allows the use of dif-ferent channels at differentspeeds. Therefore it is possibleto combine channels of differ-ent speed classes in oneParBERT system. A ParBERTsystem can be configured withone or more clock groups.Each clock group is controlledfrom one clock module. Withinone clock group (one clockmodule controls a group ofchannels) a frequency ratio of2n, n =1,2,....10 is possible,see figure 7.

With the two clock groups anyfrequency ratio m/n,n=1,2,...,256 is possible. The‘application examples’ showsome ‘two-clocksystem’configurations

Figure 6: Parameter Editor for analyzer timing

Figure 7a: Parameter Editor for setting multiple frequencies inone system


675 Mbit/s 2.7 Gbit/s/3.35 Gbit/s 10.8 Gbit/s 13.5 Gbit/s, 7 Gbit/sData Rate Range 333.3 Kbit/s .. 333.4 Mbit/s .. 2.7 Gbit/s 9.5 .. 10.8 Gbit/s 620 Mbit/s .. 7 Gbit/s

675 Mbit/s 20.8 Mbit/s .. 3.35 Gbit/s 620 Mbit/s .. 13.5 Gbit/sNumber of Channelswithin 1 Frame / + 2Expander Frameswith ext. PC 44/132 22/66 11/33 10/30

Inputs/Outputs differential & single differential & single differential & single differential & singleended ended ended ended

Data Capability PRBS/PRWS/ PRBS/PRWS/ PRBS/PRWS/ PRBS/PRWS/2 Meg Memory 8/16 Meg Memory 32 Meg Memory*** 64 Bit Memory

Generator Formats DNRZ, RZ, R1 2.7G:DNRZ DNRZ, separate NRZ, DNRZ50% clock clock output**DNRZ, R1, RZ

Technology TTL, (P)ECL, LVDS CML, (P)ECL*, CML, ECL,LVDS, LVDS, CML, PECL,ECL, addressed LVDS, SSTL-2 SSTL-2 low voltage CMOS

The idea of the ParBERT81250 product structure is thatyou receive the instrument,which meets your measurementneeds exactly. The ParBERTmodularity offers modules andfrontends. At 13.5 Gbit/s, 10.8Gbit/s and 7 Gbit/s, there arededicated modules forGenerators and Analyzers. At3.35 Gbit/s, 2.7 Gbit/s, 1.6Gbit/s and 675 Mbit/s themodules carry 2/4 front-ends.The frontendsdetermine which kind ofoutput or input connectorsyour specific instrument has.This means front-ends deter-mine the speed and input/out-put capabilities of your instru-ment. A mix of front-ends ispossible within the modules.The front-ends are placed indata modules, which areresponsible for sequencing,generating and analysing ofdata patterns includingPRBS/PRWS. These modules,plus at least one clockmodule, which generates thecommon system frequency ofthe instrument, are installed inthe mainframe.

The operating system is MSWindows® NT 4.0, 2000, or XP.The ParBERT 81250 SoftwareSuite consists of:- Graphical User Interface- Measurement Suite- Software Tools (10GbE Tool,

SONET/SDH FrameGenerator

- VXI Plug & Play Driver

At runtime the software con-sists of several processes. Thefirmware server controls thehardware and is the linkbetween the graphical userinterface and the HardwareModules. Also the MeasurementSoftware or any custom remoteprogram can communicate withthe Firmware Server. Theremoteaccess is established either byusing the Plug and Play driv-ers from Agilent Vee or from aC/C++/Visual Basic program orby a SCPI based language viaGPIB. This allows the buildingof a customized VXI systemincluding other standard VXImodules.

The VXI frame offers 13 slots.Assuming the use of theFireWire interface and oneClock module in place, themainframe can hold up to 10channels at 13.5 Gbit/s and 7Gbit/s, 11 channels at the datarate of 10.8 Gbit/s, 22 chan-nels at 3.35 Gbit/s, 2.7 Gbit/sand 1.65 Gbit/s or 44 channelsat 675 Mbit/s. If more chan-nels are needed there is thepossibility of adding up to twoexpander frames to reach themaximum number of channelswithin one clock group.Additional clock modules areneeded to set up systemswhich work with differentclock speeds that are notdivisible or multipliable by thefactors 2, 4, 8, 16 (if E4832Ais used) and 2 and 4 (ifE4861A is used). For example,for testing 1:7 or 1:10Mux/Demux devices two clockmodules are required.Please check the ApplicationExamples within the nextchapter. The ParBERT 81250Software Suite runs on anexternal PC, or a laptop,which is connected to the sys-tem via an IEEE 1394 PC linkto VXI.

Fundamental Platform Description


Analyzing the data & the DSC(17th) bit:· Ensure that the 16 data

channels are valid (validPRBS 27-1 or 211-1)streams:

· Ensure that the 16 datachannels are within skewspecification.

· Ensure that the DSC (17th)bit is valid:- correct header- match to the 16 data

channels

Fig 7d: SFI5 post processing

Figure 7c: SONET/SDH Editor

Figure 7b: 10GbE Processing Tool


Measurement SoftwareThe ParBERT measurement softwareincludes the following measure-ments:1. BER Measurement2. Fast Eye Mask Measurement3. DUT Output Timing Measurement4. Spectral Decomposition of Jitter5. DUT Output Level Measurement6. Eye opening

The ParBERT 81250 measure-ment software is a ready- to -use measurement user inter-face, which aids you with theverification and characteriza-tion of high-speed digital com-ponents and modules.

The measurement softwareoffers three different levels ofmeasurement analysis:1. Fast pass/fail measurementsideal for production.

If you work in production youcan test against limits, e.g. theBER is set at a given thresh-old. The fast pass/fail meas-urements allow you to testdevices at up to ten timesfaster than with previoustest methods - it typicallytakes less than one second!

2. Fast clock out to data out(setup and hold times), skewand eye opening specificationresults - no need to calculatevalues3. Graphical results fordetailed root cause analysis -see trends clearly and fast, e.g.pseudo color plot and contourplots.

If you are in R&D you cancharacterize your device undertest (DUT), find the limits andspecifications of the DUT andresults can be viewed graphi-cally. With its easy- to-useWindows 2000 or NT 4.0 basedGUI and graphical results, itsimplifies test development andallows

0 and 1 errors, accumulative 0and 1 BER and accumulative 1and 0 errors at once.Measurement results provided:· Displayed errored ones andzeros at the same time· Log file· Resynchronization· Pass/fail resultsThe Bit Error Rate measure-ment can be run as a singleshot or repeatedly.Several run and error countingoptions and stop criteria canbe defined. Repetitive modeoffers automatic resynchroniza-tion. It is the ideal mode forcharacterizing your device, sogood for R&D, for example,you can change the tempera-ture and measure how itaffects the BER. Single modeis particularly usefulfor manu-facturing as you can stop themeasurement after a specifiednumber of errors and/or sec-onds.

easy test execution. Data canbe exported and the graphicaland numerical results printed.

You can create test executivearound the measurement soft-ware using Agilent Vee,National Instruments' LabVIEW,Excel, Agilent TestExec, C/C++and Microsoft VisualBasic.

The Measurement Software isincluded in the standard soft-ware package which comeswith each ParBERT 81250 sys-tem.

BER Measurement

The Bit Error Ratio measure-ment measures the total num-ber of bits transferred and thenumber of errored bits, bitswhich don't meet the decisionthreshold. You can now viewhe actual 0 and 1 BER, actual

Generalworkspace

Store/recall Single Measurements

Copy/paste Measurement data to compare betweenmeasurements

PrintExport Of Measurement data (ASCII)

Online helpP&P Driver,Ready to use active X components to integrate

Remote interface complete measurements easily in VEE, VisualC++, VB, Labview, Mathlab and Excel

BER MeasurementMeasurement Parameters BER

Compared bitsErrors from expected 0sErrors from expected 1sTotal errorsParameters from last measurementperiodAccumulated parameters

Measurement mode Single or repetitiveRepetition rate is programmable inseconds (In this moderesynchronization can be enabled)

Pass/fail For actual and accumulatedparameters

Log file Logs all measured parametersPage 8/58 ParBERT Main Overview

Fast Eye Mask

The fast eye mask measure-ment is ideal for use in manu-facturing as a measurementtypically takes just one second(including synchronization).This measurement records theBER of a pre-defined numberof points (1 to 32), not thewhole eye, defined by athreshold and timing value rel-ative to the starting point ofthe measurement. You enterthe pass/fail criteria of themeasurement and the BERthreshold, find the middlepoint of the eye with thesequence and then run theBER. For example, you candefine a threshold andParBERT will find the optimalsample point and the high andlow levels automatically, e.g20% and 80%.

Measurement results provided:· BER at pre-defined sample

points· Pass/fail results

Starting Point, found by Sync

Measured Points, relative

Voltage/Threshold

Time

Frequency # channels # points measured Compared Bits Time Taken2.7Gbit/s 2 6 106 < 1 sec2.7Gbit/s 2 32 106 ~ 1 sec675 MHz 16 6 106 ~ 6 sec675 MHz 16 32 106 ~ 6 sec

Fast Eye Mask measurement time examples(run on a system via IEEE 1394 PC link)

Figure 9: The Fast Eye Mask set-up and results window

Figure 8: How the Fast Eye Mask measurement works


DUT Output Timing Measurement

This measurement measuresthe BER of a DUT’s outputversus sample point delay,which is shown graphically asa bath tub curve. The delay isalways centered to the opti-mum sampling delay point ofthe port (terminals).If a clock is defined theclock to data alignment ismeasured. If the absolute delaycan be measured it will alsobe displayed. Relative timing,where edges are compared, isalso possible.

Measurement results provided:· Clock out to data out timingrelations (setup/hold time)· Skew between outputs· Delay at optimum sample

point· Phase margin· Pass/fail results· Jitter results for total jitter,

random jitter and determin- istic jitter

There is also a numerical viewthat shows the "numericalreturn values" for the selectedBER threshold only.

DUT Output Timing MeasurementTiming Parameters Optimum sample point delay

Phase MarginClock to data out min.Clock to data out max.Skew between channels

Jitter Parameters RMS JitterMean ValuePeak Peak Jitter for specific BER

Pass/Fail For all timing and jitter parametersEach parameter can be individually enabled

Graph View of BER versus sample delay2 Markers: delay, BER

Figure 10b: Jitter can be directly equated from the bathtub curve. Viewthe jitter as a histogram.

Figure 10a : View the DUT output measurement results as a bathtubcurve


Spectral Decomposition of Jitter

This measurement provides atechnique for the SpectralDecomposition of Jitter compo-nents, which helps debuggingas well as design verificationand characterization of devices.This measurement hooks up onthe RJ/DJ Separation providedby the Output TimingMeasurement.

The decomposition techniqueallows inband and outbandcharacterizationof circuits and devices includ-ing PLLs and CDRs.

While debugging designs, thenew measurement allows thethorough exploration of thevarious components of deter-ministic jitter, helping to sepa-rate even the smallest amountsof periodic jitter (for example)from the random jitter floor.Measurement results provided:

- Top 10 frequency/powerspots

- Total Power- Noise Power

Spectral Decomposition of JitterParameters Data segment length

FFT WindowingPass/Fail Power FactorGraphs Spectrum Graph (Power vs.

Frequency)

Figure 11: Spectral Decomposition of Jitter


Output Level Measurement

This measurement performs a sweep ofthe analyzer threshold. It is shown graphi-cally as a bathtub curve, with the thresh-old on the Y-axis and BER on the X-axis(see figure 11a). From the data a his-togram showing BER versus threshold canbe derived (figure 11b) which can be usedto calculate one/zero level means andstandard deviations. Also a graph showingQ-factor from BER versus threshold (fig-ure 11c) can be derived, which shows theresult of two tail fitting operations for theinnermost gaussian distributions in theBER histogram.

Eye Opening

To measure the eye openingthe sampling delay and thethreshold of the receivingchannels are swept.

Measurement results provided:· Eye opening (voltage and

timing)· Optimum sample point

Output Level MeasurementMeasurement High/low levelParameters Mean level

AmplitudeThreshold marginHigh/low level standard deviationPeak peak noiseSignal/noise ratio (rms & peak-to-peak)Q factor

Pass/fail For all parametersEach parameter can be individually enabled

Graphs BER versus thresholdBER histogram versus thresholdQ from BER versus threshold

Eye OpeningMeasurement Optimum sampleParameters Point delay

Optimum thresholdEye opening (Volt)Phase margin

Pass/Fail For all parametersEach parameter can beindividually enabled

Graph Two markers: Voltage,delay, BER

Figure 12a) BER versus threshold 12b) BER Histogram versus threshold 12c) Q from BER versus threshold

Figure 13 a/b/c: View the BER for one terminal as a pseudo color plot or contour plot or equal BER at BER Threshold


Application Examples10GbE10GbE parts are used in theMAN area. The DUT is a mod-ule with 4x 3.125Gbit/s electri-cal inputs and outputs eachand 1x 10.3125Gbit/s opticalinput and output. The DUTsupplies a clock of 156.25MHZto all Systems. The optical sig-nals are converted electrically.

The configuration of ParBERT81250 for 10GbE testingincludes four clock groups andE/O and O/E convertersfor the optical signals at10.3125Gbit/s.

OC 192OC 192 parts are used in tele-com applications. Here theDUT consists of two chips, oneTX and one RX. There is noclock at the serial side. Fortesting 16x 675 Mbit/sGenerators and Analyzers onthe parallel side are needed.The serial side needs 1 times13.5 Gbit/s or 10.8 Gbit/sGenerator and Analyzer.

The 81250 configuration to theleft contains all necessaryresources to test Mux/Demux.Both parts of DUT can betested at one run-time, regard-less of whether memory-baseddata or PRBS/PRWS are used.

The 13.5 Gbit/s or 10.8 Gbit/schannels can be used togetherwith the 675 Mbit/s channels,as the multiplier is 16 (anoth-er multiplier would requireseparation into 2 clock groups,similar to the other two exam-ples). The combination of allgenerators and analyzers inindividual clock groups elimi-nates the synchronization limi-tations.

(4:32 demux

XAUI=>XGMII)

10B/8B dec

64B/66B enc,

x58+x39+1 scramler

32:16 mux,

66B/64B dec,

x58+x39+1 descramler

8B/10B enc

4 x 4:1mux

TX

RX w/ CDR

4 x

3.1

25

G d

iffe

ren

tial

dat

a

(8B

/10

B e

nco

ded)

10

.31

25

G optical

(66

B/6

4B

encode

d)

diff data

diff clock

DUT16:1

mux

1:16

demux

Clock

diff clock

diff data

byte

striping

4 Generators 3.35Gb/s

1 Analyzer 10.8Gb/s + O/E Converter

1 Generator 10.8Gb/s + E/O Converter

4 Analyzers 3.35Gb/s

(4:32 demux

XAUI=>XGMII)

10B/8B dec

64B/66B enc,

x58+x39+1 scramler

32:16 mux,

66B/64B dec,

x58+x39+1 descramler

8B/10B enc

4 x 4:1mux

TX

RX w/ CDR

4 x

3.1

25

G d

iffe

ren

tial

dat

a

(8B

/10

B e

nco

ded)

10

.31

25

G optical

(66

B/6

4B

encode

d)

diff data

diff clock

DUT16:1

mux

1:16

demux

Clock

diff clock

diff data

byte

striping

4 Generators 3.35Gb/s

1 Analyzer 10.8Gb/s + O/E Converter

1 Generator 10.8Gb/s + E/O Converter

4 Analyzers 3.35Gb/s

Ser Out

& In @

10 Gb/s

Par In

@ 625

Mb/s

MU

X

/16

/

16

1

DE

MU

X

/

Par Out

@ 625

Mb/s

Clock @ 625 MHz

/1

Clock

Trigger Out

16 Generators 675Mb/s 1Analyzer 10.8Gb/s

1 Generator 10.8Gb/s

Ext. Clock In

16 Analyzer 675Mb/s

Min. Channel Need (w/o Control)

Ser Out

& In @

10 Gb/s

Par In

@ 625

Mb/s

MU

X

/16

/

16

1

DE

MU

X

/

Par Out

@ 625

Mb/s

Clock @ 625 MHz

/1

Clock

Trigger Out


1 Generator 10.8Gb/s

Ext. Clock In

16 Analyzer 675Mb/s


Figure 14: 10GbE

Figure 15: OC 192 example


Ser Out

& In @

40 Gb/s

Par In

@ 10

Gb/s

MU

X

/4

/

4

1

DE

MU

X

/

Par Out

@ 10

Gb/s

Clock @ 10 GHz

/1

Clock

10GHz Clock

4 Generators 10Gb/s 1 DEMUX 40 Gb/s

1 MUX 40 Gb/s

Ext. Clock In

4 Analyzer 10Gb/s


Ser Out

& In @

40 Gb/s

Par In

@ 10

Gb/s

MU

X

/4

/

4

1

DE

MU

X

/

Par Out

@ 10

Gb/s

Clock @ 10 GHz

/1

Clock

10GHz Clock

4 Generators 10Gb/s 1 DEMUX 40 Gb/s

1 MUX 40 Gb/s

Ext. Clock In

4 Analyzer 10Gb/s


OC 768, 1:4Mux/DeMux ratioDUT consists of two chips, oneTX one RX. There is no clockat the serial side. This willrequire 4x 10.8 Gbit/s or 13.5Gbit/s Generator and Analyzerchannels for the parallel sideand 1x 43.2 Gbit/s Generatorand Error Detector BundleE4894B and E4895B. The81250 configuration, shown inFigure 16, contains all neces-sary resources to testMux/Demux. Both parts of theDUT could be tested at onerun-time using PRBS/PRWSdata

OC 768, SFI-5 (1:17)Mux/DeMuxThe DUT consists of two parts:a TX and RX part.Characteristic for SFI-5is the 17th bit, called DSC sig-nal. This carries specific timingalignment data. The modularParBERT 81250 architectureallows the easy addition of a17th generator and analyzerchannel to handlethe DSC signal. The 81250configuration, shown inFigure 16a, contains all neces-sary resources to test SFI-5Mux and Demux. Both parts ofDUT can be tested but not atone run-time. The parallel side(3.35 Gbit/s) includes 18 gen-erators and 18 analyzers, sobeside the 16 data bits, thetest system can handle theDSC signal (17th bit) and anyclock if necessary.

Ser Out

& In @

43.2 Gb/s

Par In

@ 2.7

Gb/s

MU

X/16

/

16

1

DE

MU

X

/

Par Out

@ 2.7

Gb/s

Clock @ 675 MHz

/1 Clock

1 Generator 3.35 Gb/s

16 Generators 3.35 Gb/s 1Analyzer 43.2 Gb/s


1 Analyzer 3.35 Gb/s



/DSC


/1


DSCSer Out

& In @

43.2 Gb/s

Par In

@ 2.7

Gb/s

MU

X/16

/

16

1

DE

MU

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@ 2.7

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Clock @ 675 MHz

/1 Clock


16 Generators 3.35 Gb/s 1Analyzer 43.2 Gb/s





/DSC


/1


DSC

fig 16a: OC-768 Example

fig 16a: OC-768 SFI-5 MUX and DeMUX


MUX

/

/

/

/

/1

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PLL/1

10

10 ..

DEMUX

Ser Out & In

@ 2.5Gb/s

Par In @

250 Mb/s

Control

Par Out @

250 Mb/s

Clocks

@ 125MHz

/1

10 Generators 675Mb/s

1Analyzer 2.7Gb/s10 Analyzers 675MHz 1 Analyzer 675MHz



MUX

/

/

/

/

/1

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PLL/1

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Ser Out & In

@ 2.5Gb/s

Par In @

250 Mb/s

Control

Par Out @

250 Mb/s

Clocks

@ 125MHz

/1


1Analyzer 2.7Gb/s10 Analyzers 675MHz 1 Analyzer 675MHz



/21

Par In @

up to

400 Mb/s

Clock up to 400 MHz

/1

R

PLL

G

B

En

co

de

r

PLL

R

G

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/21

Par Out @

up to 400 Mb/s

/1

Clock

up to 400 MHz

/Control

Data up to

2.5 Gb/s

Clock

up to 400 MHz

1 Generator 675MHz


1 Generator 2.7Gb/s

1 Analyzer 675Mb/s

7 Analyzer 675Mb/s


/21

Par In @

up to

400 Mb/s

Clock up to 400 MHz

/1

R

PLL

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Par Out @

up to 400 Mb/s

/1

Clock

up to 400 MHz

/Control

Data up to

2.5 Gb/s

Clock

up to 400 MHz

1 Generator 675MHz


1 Generator 2.7Gb/s

1 Analyzer 675Mb/s

7 Analyzer 675Mb/s


Gigabit EthernetGigabit ethernet tranceiverstake care for physical transre-ceiving data between a PC anda local network. The imple-mentation consists of one chip,containing one TX and oneRX. There is no clock at theserial side. (For 10 GigabitEthernet there would be sig-nals running at 3.125 Gbit/s)For testing this device withoutthe control inputs, 11x 675Mbit/s Generator and Analyzerchannels (1x Clock and 10xdata) would be needed for theparallel side. On the serial side1x 2.7 Gbit/s Generator andAnalyzer are needed. The81250 configuration, shown infigure 14, contains all neces-sary resources to testMux/Demux. As long asPRBS/PRWS data are used,both parts of the DUT can betested at one run-time. Ifmemory-based data is used,(due to synchronization limita-tions) only one part can betested at one run time.

fig 17: Gigabit Ethernet Example

fig 18: Video (DVI) Example

Digital videoFor transferring data betweenCPU and Display, a digitalvideo interface was created.The picture shown here is asimple example as there areseveral implementations creat-ed with more or less serialinterconnections (up to 8). Itis very common that theMux/Demux ratio is 1:7 withall of these video interfaces.The DUT consists of two chips,one TX and one RX. Besides3x serial there is also theclock at the speed of parallelside transferred. For a mini-mum test of this device, thenumber of channels needed is

counted to stimulate and ana-lyze one of the threeMux/Demux paths. So thiswould need a total of 8x675Mbit/s Generators andAnalyzers (1x for clock, 7x fordata) and 1x 2.7 Gbit/sGenerator and Analyzer for theserial side. The 81250 configu-ration, shown in figure 13,contains all necessary resourceto test Mux/Demux. Testing islimited to one serial interface(either R, G or B). As long asPRBS/PRWS data are usedboth parts of DUT could betested at one run-time. Ifmemory-based data is used,(due to synchronization limita-tions) only one part can betested at one run-time.


The following waveforms aretaken from the different speedclasses of the ParBERT family.

The pictures are taken showingonce the Generator output onthe scope and second theAnalyzer Inputs are connectedto an ideal source and withthe help of the eye openingmeasurement (page 9) the per-formance of the Analyzer isrecorded.

ParBERT Settings:Generator and Analyzer in sin-gle-ended mode, normal in/outused.

Frequency:625 Mbit/s used for:E4808A + E4832A + E4838A +E4835A

2.5 Gbit/s used for:E4808A + E4861A + E4862A +E4863A

10.0 Gbit/s used for:E4808A + E4866A + E4867A

Ideal source:for 675 Mbit/s, 2.7 Gbit/s,3.35 Gbit/s:transistion time 30ps,jitter <10ps pp, levels -.5V/OV

For 10.8 Gbit/s:transition time 10psjitter <8ps pp, levels + - .4V

Data:PRBS 223 -1 (stimulus andexpected) data

Generator levels:Low Level -.4V, High levels +.4V

Analyzer/Eye Opening:Single-ended, terminated togroundCompared Bits 106

BER Threshold 10- 3

Trigger Out: clock mode (625MHz), levels O/1V

Scope settings:

Agilent 81600 DCA with83484A 50 GHz module

· connected with 1m SMAcables

· external trigger from 81250trigger out

· signal adjusted with Autoscale

· every measurement for 300events


50mVpp @ 3.3Gbit/s 1.8Vpp @ 3.3Gbit/s

30% @ 3.3Gbit/s 70% @ 3.3Gbit/s

50% @ 3.3Gbit/s

Jitter modulated with Sine-Wave Jitter modulated with Rectangle-Wave

Jitter modulated with Triangle-Wave Jitter modulated with Noise-Generator

The 3.35 Gbit/s GeneratorOutput is designed for cleanand fast output signals. Itoffers a swing of 50mV to 1.8Vwithin voltage window suitedfor testing LVDS, CML, (P)ECLand SSTL –2 technologies.

The 3.35 Gbit/s Generatorallows a variable cross-over fordifferential signals. The cross-over can be programmed bythe user interface or remoteprogram between 30 to 70%.

The 3.35 Gbit/s Generator hasa Control Input for modulatingthe Delay with the help of anexternal signal. This modula-tion can be used to emulatejitter. The picture shows thismodulatioin for different typesof control voltages. The modu-lation can be used to test aDUT for jitter tolerance.


Figure 21a, b: Signal of E4866A Generator together with N4868A and E4867A Analyzer

Figure 20a, b: Signal of E4861B with E4862B and E4863B Analyzer

Figure 19a, b: Signals of E4832A with E4838A Generator and E4835A Analyzer



Agilent N4872A ParBERT 13.5 Gbit/s Generator Agilent N4873A ParBERT 13.5 Gbit/s Analyzer

Technical Specifications

Version 1.0 General

The N4872A Generator andN4873A Analyzer modules areeach one VXI slot wide andoperate in a range from 620Mbps up to 13.5 Gbit/s. TheParBERT 13.5 Gbit/s modulesrequire the E4809A 13.5 GHzCentral Clock module, whichcovers two VXI slots. All specifications, if not otherwisestated, are valid at the end ofthe recommended N4910Acable set (24'' matched pair2.4mm).

The N4872A Generator module generates hardware-basedPRBS up to 231-1, PRWS anduser-defined patterns and provides a memory depth of64 Mbit. The N4873A can synchronize on a 48bit detectword, or on a pure PRBS pattern without detect word .

Timing Specifications

The ParBERT 13.5 Gbit/s mod-ules are able to work withthree different clock modes. - Internal Clock Mode: Thecommon clock mode is provid-ed by the E4809A 13.5 GHzCentral Clock module, whichgenerates clock frequencies upto 13.5 GHz. - External Clock Mode: Thesystem also works synchro-nously with an external clock,which is connected to theE4809A clock module.

Figure 1: N4872A & N4873A and waveform

Table 1: N4872A Data Generator Timing Specifications (@ 50 % of amplitude, 50Ohm to GND)

Frequency range 620 MHz to 13.500 GHzDelay = Start delay+Fine delay Can be specified as leading edge delay in

fraction of bits in each channelStart Delay Range 0 to 100ns Fine Delay Range +/- 1Period (can be changed without stopping)Delay Resolution 100 fsAccuracy ±10 ps ± 20 ppm relative to the zero-delay

placement. (@ 25°C - 40°C ambient temp.)Relative Delay Accuracy 2ps + 2% typ. (@ 25°C - 40°C ambient temp.)Skew between modules of 20 ps after deskewing at customer levels andsame type unchanged system frequency.

(@ 25°C - 40°C ambient temp.)

- CDR Mode: Using theN4873A 13.5 Gbit/s AnalyzerCDR capabilities, it is requiredto connect the Analyzer’s CDROut to the E4809A ClockModule’s Clock In.


SequencingThe sequencer receives instructions from the centralsequencer and generates asequence according to that.The channel sequencer cangenerate a sequence with upto 60 segments.

An analyzer channel generatesfeedback signals that can control the channel sequencerand/or the central sequencer.In the case of parallel analyzerchannels, the feedback has tobe routed to the centralsequencer to allow a commonreaction of all parallel chan-nels. In the case of a singlereceive channel, the channelsequencer itself can handle thefeedback signals.

Pattern GenerationThe data stream is composedof segments. A segment can bemade up of the memory-basedpattern type, memory-basedPRBS or hardware generatedPRBS. A total of 64Mbit (atsegment length resolution512bits) are available for memory-based pattern andPRBS.

Memory-based PRBS is limitedto 215-1 or shorter. Memory-based PRBS allows specialPRBS modes like zero substitu-tion (also known as extendedzero run) and variable markratio.

A zero substitution patternextends the longest zero seriesby a user selectable number ofadditional zeroes. The next bitfollowing these zero series willbe forced to 1. Mark ratio isthe ratio of 1s and 0s in aPRBS stream, which is 1/2 ina normal PRBS. Variable markratio allows values of 1/8, 1/4,1/2, 3/4 and 7/8.

Due to granularity reasons aPRBS has to be written toRAM several times, at a multiplexing factor of 512 thenumber of repetitions is also512. That means that a 215- 1PRBS uses up to 16Mbit of thememory. Hardware-based PRBScan be a polynomial up to adegree of 231-1. No memory isused so is available for memo-ry-based pattern generation.Error insertion allows insertingsingle or multiple errors into adata stream. In case of anerror a bit will be inverted, soinstead of a 0 a 1 is generatedand vice versa.

Table 2: N4872A Pattern and SequencingPatterns: Memory-basedPRBS/PRWS Up to 64Mbit

Marker Density 2n-1, n= 7, 9, 10, 11, 15Errored PRBS/PRWS 1/8, 1/4, 1/2, 3/4, 7/8 at 2n-1, n= 7, 9, 10, 11, 15Extended ones or zeros 2n-1, n= 7, 9, 10, 11, 15

Hardware-basedPRBS 2n-1, n= 7, 10, 11, 15, 23, 31PRWS Port width 1, 2 , 4, 8, 16

Table 3: Data rate range, segment length resolution, available memory for synchronisation and fine delay operationData rate rangeMbit/s Segment length resolution Maximum memory depth, bits620 … 1.350,000 32 bits 4.194,304 620 … 2.700,000 64 bits 8.388,608 620 … 5.400,000 128 bits 16.777.216 620 … 10.800,000 256bits 33.554.432 620 … 13.500,000 512 bits 67.108.864


N4872A Generator Module

The N4872A generates differential or single-endeddata and clock signals operating from 620 Mbps up to13.5 Gbit/s. The output levelsare able to drive high-speeddevices with interfaces likeLVDS, ECL, PECL, CML andlow voltage CMOS. The nominal output impedance is50 Ohm typical. The DelayControl IN has a single-endedinput with 50 Ohm impedance.The input voltage allows oneto modulate a delay elementup to 1 GHz (200ps) withinthe Generator's differentialoutput.

The AUX IN has a single-ended input with a 50 Ohmimpedance. The AUX IN allowsinjecting gating signals.An active (TTL high) signal atthe auxiliary input forces(gates) the data to a logiczero.

Table 3: Parameters for N4872A ParBERT 13.5 Gbit/s GeneratorData Output 1, differential or single ended, 2.4mm(f) (1)Range of Operation 620 Mbps - 13.5 Gbit/sImpedance 50 Ohm typ.Output amplitude/Resolution 0.1Vpp – 1.8 Vpp / 5mVOutput voltage window -2.00 to +3.00 VShort circuit current 72 mA max.External termination voltage -2V to +3V (2)Data formats Data: NRZ, DNRZAddressable technologies LVDS, CML

PECL; ECL (terminated to 1.3V/0 V/-2 V)low voltage CMOS

Transition times (20%-80%) <20psJitter 9 ps peak-peak typ. (3)Cross-point adjustment 20%…80% typ.(Duty cycle distortion)

(1) In single-ended mode, the unused output must be terminated with 50 Ohm to GND.(2) External termination voltage must be less than 3V below VOH. External termination

voltage must be less than 3V above VOL. Termination into AC is possible.

(3) Clock Out to Data Out

Table 4: Parameters for N4872A ParBERT 13.5 Gbit/s GeneratorClock Output 1, differential or single-ended, 2.4mm(f) (1)Frequency 620 MHz - 13.5 GHzImpedance 50 Ohm typ.Output amplitude/Resolution 0.1Vpp – 1.8 Vpp / 5mVOutput voltage window -2.00 to +2.80 VShort circuit current 72 mA max.External termination voltage -2V to +3V (2)Addressable technologies LVDS, CML


Transition times (10%-90%) <25ps ppJitter 1 ps RMS typ.SSB phase noise < - 75dBc with clock module E4809A typ.(10GHz@ 10kHz offset, 1Hz bandwidth)



Table 5: Parameters for N4872A ParBERT 13.5 Gbit/s GeneratorDelay Control Input Single-ended; DC-coupled; SMA(f)Input voltage window -250mV ... +250mV (DC-coupled)Input Impedance 50 Ohm typ.Data Rate

Delay Range -100ps … +100psModulation Bandwidth DC … 1 GHz @ < 10.5 Gbit/s

Data OUT

Delay Control IN

Clock OUT

Table 6: Parameters for N4872A ParBERT 13.5 Gbit/s GeneratorInterface DC Coupled, 50 W nominalLevels TTL levelsMinimum Pulse Width 100 nsConnector SMA female

AUX IN


N4873A Analyzer Module

The analyzer features are:• Acquire data from start• Compare and acquire data

around error• Compare and count

erroneous ones and zeros tocalculate the Bit-Error-Rate.

Receive memory for acquireddata is up to 64Mbit deep,depending on segment lengthresolution. The stimulus por-tion of the channel generatesexpected data and mask data.Mask data is also available atthe maximum segment resolu-tion (32, 64, 128, 256, 512).

The analyzer is able to syn-chronize on a received datastream by means of a userselectable synchronizationword. The sync. word has alength of 48 bits and is com-posed of zeros, ones and Xs(don't cares). The detect wordmust be unique within thedata stream. Synchronizationon a pure PRBS data-streamis done without a detect-word,instead by simply loading anumber of the incoming bitsinto the internal PRBS genera-tor. A pre-condition for this isthat the polynomial of thereceived PRBS is known.

The input comparator has differential inputs with 50Ohm impedance. The sensitivi-ty of 50mV and the commonmode range of the comparatorallow the testing of all com-mon differential high-speeddevices. The user has thechoice of using the differentialinput with or without termina-tion voltage or as single-endedinput (with termination volt-age). The differential modedoes not need a threshold volt-age, whereas the single-endedmode does. But also in differentialmode the user can select one ofthe two inputs and compare thesignal to a threshold voltage.

Table 7: N4873A Analyzer Timing All timing parameters are measured at ECL levels,terminated with 50Ohm to GNDSampling rate 620 MHz to 13.500 GHzSample Delay Can be specified as leading edge delay in frac

tion of bits in each channelStart Delay Range 0 to 100 nsFine Delay Range +/- 1Period (can be changed without stopping)Delay Resolution Same as generatorAccuracy ±10 ps ± 50 ppm relative to the zero-delay

placement. (1)Relative Delay Accuracy 2 ps ± 2%Skew between modules of same type 20 ps after deskewing at customer levels and

unchanged system frequency. (1)(1) Temperature 25 - 40 °C

Table 9: Parameters for N4873A ParBERT 13.5 Gbps AnalyzerNumber of channels 1, differential or single ended, 2.4mm (f)Range of Operation 620 Mbps - 13.5 Gbit/sMax Input amplitude 2Vpp Input sensitivity 50 mVpp typical @ 10 Gbit/s, PRBS 231 -1, and BER 10-12

Input voltage range -2V … +3 (selectable 2V window)Internal termination voltage -2.0 to +3.0 V (must be within selected 2V window)(can be switched off )Threshold voltage range -2.0 to + 3.0 V (must be within selected 2V window)Threshold resolution 0.1 mVMinimum detectable 25ps typ.pulse widthPhase margin 1UI - 12ps typ.(Source: N4872A)Impedance 50 Ohm typ.

(100 Ohm differential, if termination voltage is switched off)

Data IN

Table 8: N4873A Pattern and SequencingAnalyzer Auto- On PRBS or Memory-based Datasynchronization Manual or automatic by:

Bit synchronization with or without automatic phase alignment Automatic delay alignment around a start sample delay (Range: ± 50 ns)

BER Threshold: 10-4 to 10-9


Clock Data RecoveryThe Analyzer module has integrated CDR capabilities,which allow the recovery ofeither clock or data. Beforethe CDR can lock onto theincoming data stream, the datarate must be defined withinthe user interface; commondata rates are pre-defined. InCDR mode, phase alignment tothe center of the eye is doneautomatically during synchronization. To ensure correct operation, the CDROutput must be connected tothe Clock Input of the E4809A13.5 GHz Central Clock module. In addition the gener-ator clock source and the ana-lyzer clock source must beindependent.

AUX OUTThe AUX OUT provides data orrecovered clock signals.

AUX INGating functionality: If a highlevel is applied at AUX IN,comparison is disabled andinternal counters are stopped.After resuming a low level atAUX IN, comparison is enabledand internal counters continue.The internal sequencing is notstopped.

ERROR OUT

Whenever one or more biterrors are detected, the ErrorOut signal is high for one seg-ment resolution. A high periodis always followed by a lowperiod (RZ-format) in order toensure Trigger possibility oncontinuous errors.

Table 10: Parameters for N4873A ParBERT 13.5 Gbit/s Analyzer - Clock Data RecoveryCommon Data Rates OC-192: 9.953Gbit/s

10GbE: 10.3125Gbit/sFiber Channel: 10.51875 Gbit/sG.709/G.975: 10.664Gbit/s / 10.709Gbit/sS-ATA/FireWire: 6.4Gbit/sPCI-Express: 6.4Gbit/sOC-48: 2.488Gbit/s10GbE: 3.125Gbit/sSAN: 3.187Gbit/sS-ATA/FireWire: 3.2Gbit/s

Frequency Ranges 9.9 GHz …10.90 GHz4.23 GHz ... 6.40 GHz2.115 GHz … 3.20 GHz

Ordering Information

N4872AParBERT 13.5 Gbit/s GeneratorModuleN4873AParBERT 13.5 Gbit/s AnalyzerModuleE4809A13.5 GHz Central Clock Module

Accessories:

N4910A2.4mm match cable pairN4912A2.4mm 50Ohm termination maleconnectorN4913A4 GHz deskew probe for E4809A

Technical SpecificationsAll specifications describe theinstrument’s warranted perform-ance. Non-warranted values aredescribed as typical. All specifica-tions are valid from 10° to 40° ambi-ent temperature after a 30 minutewarm-up phase, with outputs andinputs terminated with 50 Ohms toground at ECL levels if not specifiedotherwise.

Table 11: Parameters for N4873A 13.5 Gbit/s Analyzer - AUX OUTInterface AC Coupled, 50 W nominalAmplitude 600 mV nominalOutput Jitter (Clock @ AUX OUT) 0.01 UI rms typicalConnector SMA female


Table 12: Parameters for N4873A 13.5 Gbit/s Analyzer - AUX INResolution Segment resolutionTTL compatible Internal 500 hm termination to GND; Threshold @ 1.5 VConnector SMA femaleLow (0...1 V) Internal counters are enabledHigh (2 V...4 V) Internal counters are stoppedOpen Same as low

Table 13: Parameters for N4873A 13.5 Gbit/s Analyzer - ERROR OUTFormat RZ; active highOutput High Level 0 V ± 100 mVOutput Low Level +1 V ± 100 mVConnector SMA female


Agilent E4866A ParBERT 10.8 Gbit/s Generator ModuleAgilent N4868A ParBERT Booster ModuleAgilent E4867A ParBERT 10.8 Gbit/s Analyzer Module


E4866A/E4867A

There is one E4866A modulefor Generator 10.8 Gbit/s andone E4867A module for theAnalyzer 10.8 Gbit/s. N4868Ais a Booster Module for theE4866A Generator.

Clock Timing

The generator provides comple-mentary data and single-endedclock output. Both clock outand data out can be movedwith the variable delay, but itis the same delay for both.The analyzer also has a vari-able sampling delay. This con-sists of two parts: 1) the start delay with a large

range 2) the time delay of the ±1

period without stopping.

Data capabilities

PRBS/PRWS and memory-based data are defined by seg-ments. Segments are assignedto a generator for a stimulat-ing pattern. On an Analyzer itdefines the expected pattern where the incomingdata are compared to. Theexpected pattern can be setupwith mask bits. The segmentlength resolution is the resolution to which the lengthof a pattern segment can beset. The segment length resolu-tion is 256 bits for a total of32 Meg memory.

AC coupling behind sampling circuit

The AC coupling does notimpact the performance of theanalyzer as long as the inputdata is balanced or the follow-ing limitations are not exceeded:

1. For infinite time period amark density from 9/10 to10/9 is tolerated.2. All zero or all one patternsmust not be longer than 20000bits or 2 us.3. When data recovers fromimbalanced pattern to a bal-anced pattern a settling timeof maximum 200us takeseffect.

E4866A Timing Specifications (@ 50 % of amplitude, 50 Ohm to GND)Data range 9.5 Gbit/s to 10.8 Gbit/sClock range 9.5 GHz to 10.8 GHzDelay Range 0 to 300 ns Delay Resolution 1 psAccuracy ±20 ps ± 50 ppm relative to the zero-

delay placement.Skew between modules 50 ps typ. after deskewing at customer of same type levels and unchanged system frequency

E4866A Pattern and SequencingSegment length resolution 256bitsPatterns: Memory-based up to 33,554,432bitsPRBS/PRWS 2n-1, n= 7, 9, 10, 11, 15, 23, 31Marker Density 1/8, 1/4, 1/2, 3/4, 7/8 at 2n-1,

n=7, 9, 10, 11, 15Errored PRBS/PRWS 2n-1, n= 7, 9, 10, 11, 15Extended ones or zeros 2n-1, n= 7, 9, 10, 11, 15Clock patterns Divide or multiply by 1, 2, 4,


Parameters for Data output E4866A 10.8 Gbit/s with N4868A Booster *Outputs 1, differential, 50 Ohm typ. 1, differential or 2, single-

endedData formats NRZ NRZAmplitude / Resolution 0.3V to 1.8 V / 10 mV 1.0V to 2.5VAccuracy HiLevel /Amplitude ±2% ±10mV ±5% ±50mVExternal termination voltage -2V to +1.5VOutput voltage window -2.0 to +2.7 V AC CoupledMaximum external voltage -2.2V to +3.3 V Enable / Disable Relay -Transition times (20%-80%) < 60ps <20ps (15ps typ.)Overshoot/ringing 10% +20mV typ. -Jitter < 25ps peak-to-peak <25ps peak-to-peak

(20ps typ.)

Parameters for Clock output E4866A 10.8GHzOutput 1, single ended, AC coupled,

to be used into 50 OhmDuty cycle 50% typical;Maximum external voltage -2.2V to +3.3 VAmplitude/Resolution 0.5Vpp fixed typ.Transition times (20%-80%) sine waveClock Jitter < 2ps RMS

* Booster input to be driven with 1.8V amplitude from E4866A Generator

E4867A Analyzer Module

E4867A Timing Specifications (@ 50% of amplitude, 50 Ohm to GND)

Data range 9.5 Gbit/s to 10.8 Gbit/s Delay (between channels) Can be specified as leading edge delay (start delay) in

fraction of bits in each channel, fine delay can be changed with-out stopping the instrument

Start Delay Range 0 to 300 ns (not limited by period)Fine Delay Range ±1Period (w/out stopping)Resolution 1 psAccuracy ±20 ps ±50 ppm relative to the zero-delay

placement.Skew between modules 50 ps typ. after deskewing at customer levels and of same type unchanged system frequency

In general every time asequence is started this ACcoupled behavior has to betaken into account. There aretwo different methods of deal-ing with it, without gettinginvalid results.

1. Whenever possible use the synchronization feature (BitSync. or Auto DelayAlignment) followed by a balanced pattern according tothe specification above. In thiscase no recovery time is need-ed after starting a sequence. 2. If for some resason syn-chronization is impossible, usea preamble instead. The lengthof such a data segment willcorrespond to the specifiedsettling time. The pattern ofthe preamble as well as thefollowing data segment mustnot exceed the maximum toler-ated imbalance (9/10 to 10/9).

Figure 23: Internal AC Coupling of E4867A Analyzer


E4867A Pattern and SequencingSegment length resolution 256bitsPatterns: Memory based up to 33,554,432PRBS/PRWS 2n-1, n= 7, 9, 10, 11, 15, 23, 31Marker Density 1/8, 1/4, 1/2, 3/4, 7/8 at 2n-1, n= 7, 9, 10, 11, 15Errored PRBS/PRWS 2n-1, n= 7, 9, 10, 11, 15Extended ones or zeros 2n-1, n= 7, 9, 10, 11, 15User Data editor, file importAnalyzer expected DataMark Density 9/10...10/9Max consecutive 0 or 1 20000 or 2 usData recovery from imbalanced 200 usAnalyzer Auto-synchronization on PRBS or Memory-based Data manual or

automatic by:Bit synchronization* with or without automatic phase alignment. Automatic delay alignment

around a start sample delay BER Threshold: 10-4

to 10-9

*Bit synchronization on data is achieved by detecting a 48Bit unique word at the beginning of thesegment. (Don't cares can be programmed within the detect word). In this mode memory-baseddata cannot be sent within the same system. If several inputs synchronize, the delay difference between the terminals must be smaller ±5 segment length resolution.

Synchronization

Synchronization is the methodof automatically adjusting theproper bit phase for data com-parison on the incoming bitstream. The synchronizationcan be performed onPRBS/PRWS and memory-based data (it is not possiblewith a mix of PRxS and mem-ory-based data). There are two types of sychronization:• Bit synchronization• Auto delay alignment

Bit synchronization is able tocover a bit aligment for atotally unknown number ofcycles. Using memory- baseddata, the first 48 Bit withinthe expected data segment willwork as DETECT word wherethe incoming data are com-pared to. When the incomingdata match with this DetectWord, the further analysis isstarted.

Auto Delay aligment will beperformed using the analyzersampling delay. So there is alimited range while this ispossible of 10 ns.

Using Auto delay alignmentwill provide synchronizationwith an absolute timing rela-tion between a group of ana-lyzer channels. Therefore skew

measurements will be possible.

Input/Output

Addressable technologies:CML, SSTL-2, ECL (terminated to0 V/-2 V), LVPECL, (terminated to1.3V)Generator OutThe Generator output can beused as single-ended or differ-ential. Enable/Disable relayprovide on/off switching.Switched off will provideinternal termination. It is rec-ommended either to turn offor externally terminate unusedoutputs.

The generator outputs canwork into 50 Ohm centertapped termination or 100Ohm differential termination.The proper termination schemecan be chosen from the editorto adapt proper level program-ming.

Analyzer InputThe analyzer input providesmore than 90% eye openingwith an “ideal” input signal(10ps transition time). This isa superior performance forcharacterization tasks.

The analyzer channels can be operated: • Single-ended normal• Single-ended compliment• Differential

For termination there isalways 50 Ohm connected to aprogrammable termination volt-age. In differential mode thereis an additional, selectable 100 Ohm differentialtermination. Independently ofthe selected termination, onecan select whether the analysisof the incoming signal is per-formed on the input, the com-plimentary input or true dif-ferentially.


Parameters for Analyzer Module E4867A 10.8 Gbit/s Inputs 1, differential or single-ended Impedance 50 Ohm typ. 100 Ohm

differential if termination voltage is switched off

Input sensitivity 100 mV typ.,single-ended and differentialInternal termination voltage -2.0 to +2.0 V, can be switched off Threshold voltage range -2.0 to + 2.0 V Threshold resolution 1 mVThreshold accuracy ± 2% ±20 mVMaximum input voltage range

three ranges selectable: -2V to + 0V, -1V to +1V, 0V to 2VMaximum differential voltage 1.2V Enable/Disable RelayBandwidth, equivalent 35ps typ.transition time (20%-80%)Minimum detectable Data: 80 ps typ. Pulse Width Continuous clock: 40 ps typ. Phase Margin with ideal input >1 UI -15ps signal with E4866A Generator. > 1 UI -33ps

E4866A/E4867A/N4868A Modules

Booster N4868A

The N4868A delivers either 1 differential channel or 2 sin-gle-ended channels. TheN4868A 001 delivers either 2differential or 4 single-endedchannels. For differential oper-ation it is recommended thatthe N4869A cable kit be usedwith phase adjustment capabil-ity for the differential path.For the N4868A -001 twocable kits would be needed ifboth are used as differential.The N4868A -001 can also beused 1x differential and 2xsingle-ended to boost the clockoutput of the E4866A besidethe differential data.



Agilent N4874A ParBERT 7 Gbit/s Generator Agilent N4875A ParBERT 7 Gbit/s Analyzer


Version 1.0 General

The N4874A Generator andN4875A Analyzer modules areeach one VXI slot wide andoperate in a range from 620Mbps up to 7 Gbit/s. TheParBERT 7 Gbit/s modulesrequire the E4809A 13.5 GHzCentral Clock module. Allspecifications, if not otherwisestated, are valid at the end ofthe recommended N4910Acable set (24'' matched pair2.4mm).

The N4874A Generator module generates hardware-basedPRBS up to 231-1, PRWS anduser-defined patterns and provides a memory depth of64 Mbit. The N4875A can synchronize on a 48bit detectword, or on a pure PRBS pattern without detect word .

Timing SpecificationsThe ParBERT 13.5 Gbit/s mod-ules are able to work withthree different clock modes. - Internal Clock Mode: Thecommon clock mode is provided by the E4809A 13.5GHz Central Clock module,which generates clock frequen-cies up to 13.5 GHz. - External Clock Mode: Thesystem also works synchro-nously with an external clock,which is connected to theE4809A clock module.

Figure 1: N4874A & N4875A and waveform

- CDR Mode: Using theN4875A 7 Gbit/s Analyzer CDRcapabilities, it is required toconnect the Analyzer’s CDROut to the E4809A ClockModule’s Clock In.

(1) @25°C - 40°C ambient temperature

Table 1: N4874A Data Generator Timing Specifications (@ 50 % of amplitude, 50Ohm to GND)

Frequency range 620 MHz to 7 GHzDelay = Start delay+Fine delay Can be specified as leading edge delay in

fraction of bits in each channelStart Delay Range 0 to 100ns Fine Delay Range +/- 1Period (can be changed without stopping)Delay Resolution 100 fsAccuracy ±10 ps ± 20 ppm relative to the zero-delay

placement. (@ 25°C - 40°C ambient temp.)Relative Delay Accuracy ±2ps + 2% typ. (@ 25°C - 40°C ambient temp.)Skew between modules of 20 ps after deskewing at customer levels andsame type unchanged system frequency.

(@ 25°C - 40°C ambient temp.)


SequencingThe sequencer receives instructions from the centralsequencer and generates asequence according to that.The channel sequencer cangenerate a sequence with upto 60 segments.

An analyzer channel generatesfeedback signals that can control the channel sequencerand/or the central sequencer.In the case of parallel analyzerchannels, the feedback has tobe routed to the centralsequencer to allow a commonreaction of all parallel chan-nels. In the case of a singlereceive channel, the channelsequencer itself can handle thefeedback signals.

Pattern GenerationThe data stream is composedof segments. A segment can bemade up of the memory-basedpattern type, memory-basedPRBS or hardware generatedPRBS. A total of 64Mbit (atsegment length resolution512bits) are available for memory-based pattern andPRBS.

Memory-based PRBS is limitedto 215-1 or shorter. Memory-based PRBS allows specialPRBS modes like zero substitu-tion (also known as extendedzero run) and variable markratio.

A zero substitution patternextends the longest zero seriesby a user selectable number ofadditional zeroes. The next bitfollowing these zero series willbe forced to 1. Mark ratio isthe ratio of 1s and 0s in aPRBS stream, which is 1/2 ina normal PRBS. Variable markratio allows values of 1/8, 1/4,1/2, 3/4 and 7/8.

Due to granularity reasons aPRBS has to be written toRAM several times, at a multiplexing factor of 512 thenumber of repetitions is also512. That means that a 215- 1PRBS uses up to 16Mbit of thememory. Hardware-based PRBScan be a polynomial up to adegree of 231-1. No memory isused so is available for memo-ry-based pattern generation.Error insertion allows insertingsingle or multiple errors into adata stream. In case of anerror a bit will be inverted, soinstead of a 0 a 1 is generatedand vice versa.

Table 2: N4874A Pattern and SequencingPatterns: Memory-basedPRBS/PRWS Up to 64Mbit

Marker Density 2n-1, n= 7, 9, 10, 11, 15Errored PRBS/PRWS 1/8, 1/4, 1/2, 3/4, 7/8 at 2n-1, n= 7, 9, 10, 11, 15Extended ones or zeros 2n-1, n= 7, 9, 10, 11, 15

Hardware-basedPRBS 2n-1, n= 7, 10, 11, 15, 23, 31PRWS Port width 1, 2 , 4, 8, 16

Table 3: Data rate range, segment length resolution, available memory for synchronisation and fine delay operationData rate rangeMbit/s Segment length resolution Maximum memory depth, bits620 … 1.350,000 32 bits 4.194,304 620 … 2.700,000 64 bits 8.388,608 620 … 5.400,000 128 bits 16.777.216 620 … 7.000,000 256bits 33.554.432 620 … 7.000,000 512 bits 67.108.864


N4874A Generator Module

The N4874A generates differential or single-endeddata and clock signals operating from 620 Mb/s up to7 Gbit/s. The output levels areable to drive high-speeddevices with interfaces likeLVDS, ECL, PECL, CML andlow voltage CMOS. The nominal output impedance is50 Ohm typical. The DelayControl IN has a single-endedinput with 50 Ohm impedance.The input voltage allows oneto modulate a delay elementup to 1 GHz (200ps) withinthe Generator's differentialoutput.

The AUX IN has a single-ended input with a 50 Ohmimpedance. The AUX IN allowsinjecting gating signals.An active (TTL high) signal atthe auxiliary input forces(gates) the data to a logiczero.

Table 3: Parameters for N4874A ParBERT 7 Gbit/s GeneratorData Output 1, differential or single ended, 2.4mm(f) (1)Range of Operation 620 Mb/s - 7 Gbit/sImpedance 50 Ohm typ.Output amplitude/Resolution 0.1Vpp – 1.8 Vpp / 5mVOutput voltage window -2.00 to +3.00 VShort circuit current 72 mA max.External termination voltage -2V to +3V (2)Data formats Data: NRZ, DNRZAddressable technologies LVDS, CML

PECL - 3.3V; ECL (terminated to 1.3V/0 V/-2 V)low voltage CMOS, LVDS, CML

Transition times (20%-80%) <20psJitter 9 ps peak-peak typ. (3)Cross-point adjustment 20%…80% typ.



(3) Clock Out to Data Out

Table 4: Parameters for N4874A ParBERT 7 Gbit/s GeneratorClock Output 1, differential or single-ended, 2.4mm(f) (1)Frequency 620 MHz - 7 GHzImpedance 50 Ohm typ.Output amplitude/Resolution 0.1Vpp – 1.8 Vpp / 5mVOutput voltage window -2.00 to +2.80 VShort circuit current 72 mA max.External termination voltage -2V to +3V (2)Addressable technologies LVDS, CML


Transition times (10%-90%) <25psJitter 1 ps RMS typ.SSB phase noise < - 75dBc with clock module E4809A typ.(10GHz@ 10kHz offset, 1Hz bandwidth)



Table 5: Parameters for N4874A ParBERT 7 Gbit/s GeneratorDelay Control Input Single-ended; DC-coupled; SMA(f)Input voltage window -250mV ... +250mV (DC-coupled)Input Impedance 50 Ohm typ.Delay Range -100ps … +100psModulation Bandwidth DC … 1 GHz Data Rate < 10.5 Gbit/s

Data OUT

Delay Control IN

Clock OUT

Table 6: Parameters for N4874A ParBERT 7 Gbit/s GeneratorInterface DC Coupled, 50 W nominalLevels TTL levelsMinimum Pulse Width 100 nsConnector 5 MA female

AUX IN


N4875A Analyzer Module


around error• Compare and count

erroneous ones and zeros tocalculate the Bit-Error-Rate.

Receive memory for acquireddata is up to 64Mbit deep,depending on segment lengthresolution. The stimulus por-tion of the channel generatesexpected data and mask data.Mask data is also available atthe maximum segment resolu-tion (32, 64, 128, 256, 512).

The analyzer is able to syn-chronize on a received datastream by means of a userselectable synchronizationword. The sync. word has alength of 48 bits and is com-posed of zeros, ones and Xs(don't cares). The detect wordmust be unique within thedata stream. Synchronizationon a pure PRBS data-streamis done without a detect-word,instead by simply loading anumber of the incoming bitsinto the internal PRBS genera-tor. A pre-condition for this isthat the polynomial of thereceived PRBS is known.

The input comparator has differential inputs with 50Ohm impedance. The sensitivi-ty of 50mV and the commonmode range of the comparatorallow the testing of all com-mon differential high-speeddevices. The user has thechoice of using the differentialinput with or without termina-tion voltage or as single-endedinput (with termination volt-age). The differential modedoes not need a threshold volt-age, whereas the single-endedmode does. But also in differentialmode the user can select one ofthe two inputs and compare thesignal to a threshold voltage.

Table 7: N4875A Analyzer Timing All timing parameters are measured at ECL levels,terminated with 50Ohm to GNDSampling rate 620 MHz to 7 GHzSample Delay Can be specified as leading edge delay in frac

tion of bits in each channelStart Delay Range 0 to 100 nsFine Delay Range +/- 1Period (can be changed without stopping)Delay Resolution Same as generatorAccuracy ±10 ps ± 20 ppm relative to the zero-delay

placement. (1)Relative Delay Accuracy ±2 ps ± 2% typ. (1)Skew between modules of same type 20 ps after deskewing at customer levels and

unchanged system frequency. (1)(1) Temperature @ 25°C - 40°C ambient temp

Table 9: Parameters for N4875A ParBERT 7 Gbit/s AnalyzerNumber of channels 1, differential or single ended, 2.4mm (f)Range of Operation 620 Mbps - 7 Gbit/sMax Input amplitude 2Vpp Input sensitivity 50 mVpp typical @ 10 Gbit/s, PRBS 231 -1, and BER 10-12

Input voltage range -2V … +3 (selectable 2V window)Internal termination voltage -2.0 to +3.0 V (must be within selected 2V window)(can be switched off )Threshold voltage range -2.0 to + 3.0 V (must be within selected 2V window)Threshold resolution 0.1 mVMinimum detectable 25ps typ.pulse widthPhase margin 1UI - 12ps typ.(Source: N4874A)Impedance 50 Ohm typ.

(100 Ohm differential, if termination voltage is switched off)

Data IN

Table 8: N4875A Pattern and SequencingAnalyzer Auto- On PRBS or Memory-based Datasynchronization Manual or automatic by:

Bit synchronization with or without automatic phase alignment Automatic delay alignment around a start sample delay (Range: ± 50 ns)

BER Threshold: 10-4 to 10-9


Clock Data RecoveryThe Analyzer module has integrated CDR capabilities,which allow the recovery ofeither clock or data. Beforethe CDR can lock onto theincoming data stream, the datarate must be defined withinthe user interface; commondata rates are pre-defined. InCDR mode, phase alignment tothe center of the eye is doneautomatically during synchronization. To ensure correct operation, the CDROutput must be connected tothe Clock Input of the E4809ACentral Clock module. In addi-tion the generator clock sourceand the analyzer clock sourcemust be independent.

AUX OUTThe AUX OUT provides data orrecovered clock signals.

AUX INGating functionality: If a highlevel is applied at AUX IN,comparison is disabled andinternal counters are stopped.After resuming a low level atAUX IN, comparison is enabledand internal counters continue.The internal sequencing is notstopped.

ERROR OUT

Whenever one or more biterrors are detected, the ErrorOut signal is high for one seg-ment resolution. A high periodis always followed by a lowperiod (RZ-format) in order toensure Trigger possibility oncontinuous errors.

Table 10: Parameters for N4875A ParBERT 7 Gbit/s Analyzer - Clock Data RecoveryCommon Data Rates S-ATA/FireWire: 6.4Gbit/s

PCI-Express: 6.4Gbit/sOC-48: 2.488Gbit/s10GbE: 3.125Gbit/sSAN: 3.187Gbit/sS-ATA/FireWire: 3.2Gbit/s

Frequency Ranges 4.23 GHz ... 6.4GHz2.115 GHz … 3.2 GHz

Ordering Information

N4874AParBERT 7 Gbit/s GeneratorModuleN4875AParBERT 7 Gbit/s AnalyzerModuleE4809ACentral Clock Module

Accessories:

N4910A2.4mm match cable pairN4912A2.4mm 50Ohm terminationmale connectorN4913A4 GHz deskew for E4809A

Technical SpecificationsAll specifications describe the instru-ment’s warranted performance. Non-warranted values are described astypical. All specifications are validfrom 10° to 40° ambient temperatureafter a 30 minute warm-up phase,with outputs and inputs terminatedwith 50 Ohms to ground at ECL levelsif not specified otherwise.

Table 11: Parameters for N4875A 7 Gbit/s Analyzer - AUX OUTInterface AC Coupled, 50 W nominalAmplitude 600 mV nominalOutput Jitter (Clock @ AUX OUT) 0.01 UI rms typicalConnector SMA female

Table 12: Upgrades 7 Gbit/s - 13 Gbit/sOrder No. FeatureE4860AS-290 Upgrade N4874A to 13.5 GbpsE4860AS-291 Upgrade N4875A to 13.5 Gbps


Table 13: Parameters for N4875A 13.5 Gbit/s Analyzer - AUX INResolution Segment resolutionTTL compatible Internal 500 hm termination to GND; Threshold @ 1.5 VConnector SMA femaleLow (0...1 V) Internal counters are enabledHigh (2 V...4 V) Internal counters are stoppedOpen Same as low

Table 14: Parameters for N4875A 13.5 Gbit/s Analyzer - ERROR OUTFormat RZ; active highOutput High Level 0 V ± 100 mVOutput Low Level +1 V ± 100 mVConnector SMA female

Agilent E4861B ParBERT 3.35 Gbit/s Data ModuleAgilent E4862B ParBERT 3.35 Gbit/s Generator Front-EndAgilent E4863B ParBERT 3.35 Gbit/s Analyzer Front-End


General

A ParBERT 3.35 Gbit/s module houses two front-ends, eithertwo generators or analyzers orany mix. ParBERT 3.35 Gbit/smodules run with the E4808Amodule. The key specificationsof ParBERT 3.35 Gbit/s are:

• 21MHz … 3.350 GHz Clock/data rate

• 16Mbit memory depth at each channel

• HW-based PRBS generation up to the polynomial of 231- 1

• analyzer can synchronize on a 48bit detect word (memory-based data)

• analyzer can synchronize on a pure PRBS pattern without detect word.

Sequencing

The sequencer receives instruc-tions from the clock module.The channel sequencer cangenerate a sequence with upto 60 segments. An analyzerchannel can generate feedbacksignals which are combined inthe Clock module for a com-mon reaction of all parallelchannels. In case of a singlereceiver channel the channelsequencer itself can handle thefeedback signals.

E4861B Data Generator Timing Specification (@ 50% of amplitude, 50 Ohm to GND)Frequency range 20.834 MHz to 3.350 GHzDelay=start delay+fine delay Can be specified as leading edge delay in fraction of bits in

each channelStart Delay Range 0 to 200ns (not limited by period)Fine Delay Range ±1 Period (can be changed without stopping)Delay Resolution 1 psAccuracy Data Mode ±25 ps ±50 ppm relative to the zero-delay and temperature

change within ±10°C after autocalibrationClock mode ±50 ps ±50 ppm relative to the zero-delay

Skew between modules of same type 50 ps typ. after deskewing at customer levels and (Data Mode) unchanged system frequency

The variable delay is available in data mode and pulse mode. In clock mode the timing is fixed.

E4861B Analyzer Timing All timing parameters are measured at ECL levels,terminated with 50 Ohm to GNDSampling rate Same as generatorSample Delay Same as Delay = start delay + fine delayStart Delay Range Same as generatorFine Delay Range Same as generatorResolution Same as generatorAccuracy Same as generatorSkew Same as generator

Timing Capabilities

The frequency range of themodules is 21MHz … 3.350GHz.The ParBERT 3.35 Gbit/sfront-ends use a multiplyingPLL that multiplies system master clock by 4 or 8. Withthe help of the clock module,an external clock source canbe used. This external clockmust run continuously. If theclock signal is interrupted, themultiplying PLLs typicallyneeds 100 milliseconds to lockonto the clock again.

E4861B with E4862B & E4861Bwith E4863B


Dependancy of PRWS generation and port width. Almost all the combinations are possible except the following:

PRWS Port Width

27 -1 No restriction29-1 7210-1 3, 11, 31, 33211-1 23215-1 7, 31223-1 47231-1 No restriction

*With PRBS data, analyzers can autosyncronize on incoming PRBS data bits. Whenusing memory-based data, this data must contain a unique 48 bit detect Word at thebeginning of the segment, and the generators must be on a separate system clock. Don’tcares within detect word are possible. If several inputs synchromize, the delay difffer-ence between terminals must be smaller than ±5 segment lengths.

E4861B Pattern and SequencingPatterns:Memory-based Up to 16Mbit PRBS/PRWS

Marker Density 2n-1, n=7, 9, 10, 11, 15, 23, 31Errored PRBS/PRWS 1/8, 1/4, 1/2, 3/4, 7/8 at 2n-1, n=7, 9, 10, 11, 15Extended ones or zeros 2n-1, n=7, 9, 10, 11, 15

Clock patterns 2n-1, n=7, 9, 10, 11, 15User Divide or multiply by 1, 2, 4Analyzer Auto- On PRBS or Memory-based Datasynchronization Manual or automatic by:

Bit synchronization* with or without automatic phase alignment around a start sample delay (Range: +/-50ns)

BER Threshold: 104 to 108

Data rate range, segment length resolution, available memory for syn-chronization and fine delay operationData rate range Segment length Maximum memoryMbit/s resolution depth, bits20.834 ... 41.666 1bit 131,07220.834 ... 82.333 2bits 262,14420.834 ... 166.666 4bits 524,28820.834 ... 333.333 8bits 1,048,57620.834 ... 666.666 16bits 2,097,15220.834 ... 1,333.333 32bits 4,194,30420.834 ... 2,700.000 64bits 8,388,60820.834 ... 3,350.000 128bits 16,777,216


Pattern Generation

The data stream is composedof segments. A segment can beof the memory-based patterntype, memory-based PRBS orhardware generated PRBS. Atotal of 16Mbit (at segmentlength resolution 128bits) areavailable for memory-basedpattern and PRBS.

Memory-based PRBS is limitedto 215-1 or shorter. Memory-based PRBS allows specialPRBS modes like zero substitu-tion (also known as extendedzero run) and variable markratio. A zero substitution pattern extends the longestzero series by a user-selectablenumber of additional zeros.The next bit following these zero-series willbe forced to 1. Mark ratio isthe ratio of ones and zeros ina PRBS stream, which is 1/2in a normal PRBS. Variablemark ratio allows values of1/8, 1/4, 1/2, 3/4, 7/8. Due togranularity reasons a PRBShas to be written to RAM sev-eral times, at a multiplexingfactor of 128 the number ofrepetitions is also 128. Thatmeans that a 215-1 PRBS usesup to 4Mbit of the memory.

Generator Front End (E4862B)

The amplifier generates a dif-ferential output signal. Eachoutput can be individuallyswitched on and off. The out-put levels are sufficient todrive typical high-speeddevices with interfaces likeECL, PECL, and LVDS. Thenominal output impedance is50 Ohm. The Delay Control Inhas a single-ended input with 50Ohm impedance. The inputvoltage modulates a Delay elementwithin the generator’s differen-tial output. The user has theoption of turning the DelayControl In feature on or off.Additionally the user canselect between two delayranges.

Parameters for Generator Front-Ends E4862B 3.35 Gbit/sOutputs 1, differential or single-endedImpedance 50 Ohm typ.Data formats Data: NRZ, DNRZ, RZ, R1Pulse Mode

Range 150ps to (1UI - 150ps) Resolution 1psWidth accuracy 40 ps typ.

Output voltage window -2.00 to +3.00 VAbsolute maximum -2.2 V to +3.2 Vexternal voltageAddressable technologies LVDS, CML, PECL, ECL

low voltage CMOSAmplitude/Resolution 0.05 Vpp ... 1.8 Vpp/10 mVAccuracy HiLevel/Amplitude ±2% ±10 mVShort circuit current 72 mA max.Transition times (20%-80%) <75ps; 60ps typ.Overshoot/ringing 5% +10 mV typ.Jitter, NRZ data mode <30ps peak-peak (1)

Clock mode <2ps rms (1,2)Pulse, RZ, R1 mode 30ps peak-peak typ. (1,2)

Cross-point adjustment 30% ... 70% (in NRZ mode only)(Duty cycle distortion)

(1) Measured with E4808A Clock Module(2) Specified as Intra Channel Jitter.

Hardware-based PRBS can beof any polynomial up to adegree of 231-1. No memory isused, so the total memory isfree for memory-based patterngeneration. Error insertionallows inserting single or mul-tiple errors into a data stream.In case of an error a bit willbe inverted, so instead of a ‘0’a ‘1’ is generated and viceversa. Single errors can beinserted by P or via instruc-tion from the Centralsequencer. The user can triggeran error with a signal supplied to the qualifier podof the Central module. Anerror insertion with a fixedrate and a fixed distribution issupported. The user softwareallows the selection of erroredand error-free segments.


(1) Measured with E4808A Central Module(2) Terminate with 50 Ohm to GND, if not used

Analyzer Front End (E4863B)


around error• Compare and count erro

neous ones and zeros to cal-culate the Bit-Error-Rate

Receive memory for acquireddata up to 16Mbit deep,depending on the segmentlength resolution. The stimulusportion of the channel gener-ates expected data and maskdata. Mask data is also avail-able at the maximum granular-ity.

The analyzer is able to syn-chronize on a received datastream by means of a user-defined Detect Word. TheDetect Word is defined by thefirst bits within the expectedsegment, it has a length of 48bits and is composed of zeros, ones andXs (don’t cares). The detectword must be unique withinthe data stream. Synchronization on a pure-PRBS data-stream is donewithout a detect-word, by sim-ply loading a number of theincoming bits into the internalPRBS generator. A pre-condi-tion for this is that the poly-nomial of the received PRBS isknown.

The input comparator has dif-ferential inputs with 50 Ohmimpedance. The sensitivity ofdown to 50mV and the com-mon mode range of the comparator allows the testingof all common differential

Delay Control InInput voltage window -500mV ... +500mV (DC-coupled)Delay Range 1 -250ps ... +250psDelay Range 2 -25ps ... +25psModulation Bandwidth DC ... 200MHzInput Impedance 50 Ohm (typ.)

Parameters for Analyzer Front-Ends E4863B 3.35 Gbit/sNumber of channels 1, differential or single-endedImpedance 50 Ohm typ.

(100 Ohm differential if termination voltage is switched off)

Internal termination voltage -2.0 to +3.0 V(can be switched off)Threshold voltage range -2.0 to +3.0 VThreshold resolution 1 mVThreshold accuracy ±20 mV ±1%Input sensitivity <50mV(single-ended and differential)Minimum detectable <150pspulse widthMaximum input voltage range Three ranges selectable:

-2V to +1V-1V to +2V0V to 3V

Maximum differential voltage 1.8VPhase margin with >1UI - 30ps (1)ideal input signalPhase margin with >1UI - 50ps (1)E4862B GeneratorAuxilary out V out: 350mV pp typ., AC coupled (2)

high-speed devices. The userhas the option of using thedifferential input with or with-out termination voltage or assingle-ended input (with termi-nation voltage). The differentialmode does not need a thresh-old voltage, whereas the sin-gle-ended mode does. But alsoin differential mode the usercan select one of the twoinputs and compare the signalto a threshold voltage.

ProtectionInput and output relay switchoff automatically, if absolutemaximum voltage window isexceeded.


E4861A Generator / AnalyzerModule This module holds any combi-nation of up to two analyzerfront-ends (E4863A, E4865A)and generator front-ends(E4862A, E4864A).

With front-ends E4864A andE4865A the maxiumum speedis limited to 1.65Gbit/s. Themaximum speed of 2.7Gbit/s isachieved with front-endsE4862A and E4863A.

Clock Module/Data ModeThe generator can operate inclock mode or data mode.Clock mode is achieved whenthe generator is assigned as aPulse Port. Data mode isachieved when using it as aData Port. In Clock modethere is a fixed duty cycle of50%. In data mode there isNRZ format with variabledelay. The analyzer alwaysworks as Data Port with vari-able sampling delay. The sam-pling delay consists of two ele-ments: the start delay and thefine delay. The fine delay canbe varied within ±1 periodwithout stopping.

Agilent E4861A ParBERT 2.7 Gbit/s / 1.65 Gbit/s Data ModuleAgilent E4862A ParBERT 2.7 Gbit/s Generator Front-EndAgilent E4863A ParBERT 2.7 Gbit/s Analyzer Front-End

Agilent E4864A ParBERT 1.65 Gbit/s Generator Front-EndAgilent E4865A ParBERT 1.65 Gbit/s Analyzer Front-EndTechnical Specifications

E4861A Data Generator Timing Specifications (@ 50 % of amplitude, 50 Ohm to GNDFrequency range* Clock/Data mode 333.334 Mbit/s to 2.70 Gbit/s (1.65Gbit/s E4864A,E4865A)Delay (between channels) Can be specified as leading edge delay in fraction of bits in each

channelRange 0 to 300 ns (not limited by period)Resolution 1 psAccuracy ±50 ps ±50 ppm relative to the zero-delay placement. (From 20°C to

35°C without autocol)±80 ps ±50 ppm typ. relative to the zero-delay placement and temperature change within ±5°C after autocalibration

Skew between modules 50 ps typ. after deskewing at customer levels and unchanged systemof same type frequency Pulse width 50% of period typ. in clock mode

*See tables for front-end deratings

Data Capabilities

PRBS/PRWS and memory-based data are defined by seg-ments. Segments are assignedto a generator for a stimulat-ing pattern, on an analyzer itdefines the expected patternwhich the incoming data arecompared to. The expectedpattern can be set up withmask bits.

E4861A Module

The segment length resolutionis the resolution to which thelength of a pattern segment ormask can be set. The maxi-mum memory per channel ofthe E4861A can be set insteps of 64 bits up to a lengthof 8192 kbits. If the 64 bitsegment length resolution istoo coarse, memory depth andfrequency can be traded.


E4861A Pattern and Sequencing

Patterns:

Memory-based up to 8MbitPRBS/PRWS 2n-1, n=7, 9, 10, 11, 15, 23, 31

Marker Density 1/8, 1/4, 1/2, 3/4, 7/8 at PRBS/PRWS 2n-1, n=7, 9, 10, 11,15

Errored 2n-1, n=7, 9, 10, 11, 15Extended ones or zeros 2n-1, n=7, 9, 10, 11, 15

Clock patterns Divide or multiplied by 2, 4, 8, 16User Data editor, file importAnalyzer Auto- On PRBS or memory-based dataSynchronization: manual or automatic by:

Bit synchronization* with or without automatic phase alignmentAutomatic delay alignment around start sample delay (Range: ±10ns)BER Threshold: 104 to 109

*Bit synchronization on data is achieved by detecting a 48 Bit unique word at the begin-ning of the segment. Don’t cares within the detect word are possible. In this mode nomemory-based data can be sent within the same system. If several inputs synchronize thedelay difference between the terminals, it must be smaller ±5 segment length resolution.

Sub-frequencies

For applications requiring dif-ferent frequencies at a fractionof the system clock, the ratecan be divided or multipliedby 1, 2 or 4. This influencesthe dependency between segment length resolution andmaximum memory depth.

Synchronization

Synchronization is the methodof automatically adjusting theproper bit phase for data com-parison on the incoming bitstream. The sychronisation canbe performed on PRBS/PRWSand memory-based data but itis not possible on a mix ofPRxs and memory-based data.

There are two types of synchronization-bit synchronization-auto delay aligment

Bit synchronization is possibleto cover a bit alignment for atotally unknown number ofcycles. Using memory-baseddata, the first 48 bit withinthe expected data segment willwork as Detect Word whichthe incoming data is comparedto. When the incoming datamatch with the Detect Word,further analysis begins.

Auto Delay aligment will beperformed by using the analyz-er sampling delay. So there isa limited range while this ispossible of ±10ns.

Using Auto Delay, alignmentwill provide synchronizationwith an absolute timing rela-tion between a group of ana-lyzer channels. So skew meas-urements are possible.

E4861A Analyzer Timing All timing parameters are measured at ECLand levels, terminated with 50 Ohm to GNDSample delay = start delay + fine delay,fine delay can be changed without stoppingSampling rate* Same as generatorFine delay range ±1 periodSampling delay range Same as generatorAccuracy Same as generatorResolution Same as generatorSkew Same as generator

*See tables for front-end deratings

Data rate range, segment length resolution, available memory for syn-chronization and fine delay operation

Data rate range Segment length Maximum memoryM/bits resolution depth, bits333.334...666.666 16 bits 2,097,152666.667...1,333.333 32 bits 4,194,3041,333.334...2,666.667 64 bits 8,388,608

In general it is possible to set higher values for the segment length resolution and also at lower frequencies than are indicated in the table

Depending on the capability of generating PRWS and port width, almost allthe combinations are possible except the following:

PRWS Port Width27-1 No restriction29-1 7210-1 3, 11, 31, 33211-1 23215-1 7, 31223-1 47231-1 No restriction


Parameters for Analyzer Front-Ends E4863A 2.7 Gbit/s (E4865A 1.65 Gbit/s)

Number of channels 1, differential or single endedImpedance 50 Ohm typ.

100 Ohm differential if termination voltage is switched off

Internal termination voltage -2.0 to +3.0 V(can be switched off)Threshold voltage range -2.0 to + 3.0 VThreshold resolution 2 mVThreshold accuracy ± 1% ±20 mV Input sensitivity (single-ended 50mV typand differential)Minimum detectable 180 ps typ. at ECL levelspulse widthMaximum input voltage range Three ranges selectable:

-2V to + 1V-1V to +2V

0V to 3VMaximum differential voltage 1.8V operating

max. 3VPhase Margin, with ideal input signal >1UI - 50 ps

with generator E4862A > 1UI-75 psAuxiliary out Swing: 400 mV pp typ., AC coupled

Input/Output

Addressable technologiesLVDS, ECL (terminated with50 to 0 V/-2 V), PECL (termi-nated to +3 V Analyzer inputrequires use of a Bias Tee)

Analyzer InputThe analyzer channel can be operated:• Single-ended normal• Single-ended compliment• Differential

For termination there isalways 50 Ohm connected to aprogrammable termination volt-age. In differential mode thereis an additional, selectable 100Ohm differential termination.Independent of the selectedtermination, there is the choiceof whether the anaylsis of theincoming signal is performedon the input or true differen-tially. For connecting to PECLit is recommended a Bias Teeis used. The 2.7 Gbit/s analyz-er offers an auxiliary output,where the differential inputsignal is available as a single-ended signal. The bandwidth ofthe Aux Output is limited to2GHz.

Generator OutputThe Generator output can beused as single-ended or differ-ential. Enable/Disable relaysprovide on/off switching. Whenswitched off internal termina-tion is provided. It is recom-mended that unused outputsare either turned off or externally terminated.

The Generator outputs canwork into 50 Ohm centretapped termination or 100Ohm differential termination. The proper termi-nation scheme can be chosenfrom the editor to adapt prop-er level programming.

Parameters for Generator Front-ends E4862A 2.7 Gbit/s (E4864A 1.65 Gbit/s)Outputs 1, differential or single endedImpedance 50 Ohm Typ. Formats Clock: Duty cycle 50%±10% typ.

Data: NRZ, DNRZOutput voltage window -2.00 to + 3.00 V

3.00 V to 4.5 (terminated to +3V only)Maximum external voltage - 2.2 to +4.7 VExternal termination voltage -2V to +3VAmplitude/Resolution low voltage CMOS 0.05 to 1.8 Vpp* / 10mVAccuracy HiLevel/Amplitude ±2%±10 mVShort circuit current 72 mA maxTransition times (20%-80%) 90ps typ@ ECL,LVDS

110ps typ @ Vpp maxOvershooting/ringing 20% + 20mV typJitter, Data mode <50ps peak-to-peak

Clock mode <5ps, rms

*does double into open, but outputs may switch off

ProtectionInput and Output Relaysswitch off automatically ifmaximum voltages are about tobe exceeded.


E4832A 675 Mbit/sGenerator/Analyzer ModuleThis module holds any combi-nation of up to two analyzerfront-ends (E4835A) and fourgenerator front-ends (E4838A),

Clock Module/Data ModeThe generator can operate inclock mode or data mode.Clock mode is achieved whenthe generator is assigned as aPulse Part. Data mode isachieved with assigning it anddata part. In Clock mode thereis a fixed duty cycle of type50%. In data mode there isNRZ format with variabledelay. The analyzer works as adata part whenever used vari-able sampling delay. The sam-pling delay consists of two ele-ments: the start delay and thefine delay. The fine delay canbe varied within ±1 periodwithout stopping.

Data CapabilitiesPRBS/PRWS and memory-based data are defined by seg-ments. Segements are assignedto a generator for a stimulat-ing pattern, on an analyzer itdefines the expected patternwhich the incoming data arecompared to. The expectedpattern can be setup withmask bits.

The segment length resolutionis the resolution to which thelength of a pattern segmentcan be set. The maximum memory per channelof the E4832A can be set insteps of 16 bits up to a lengthof 2048 Kbit. If the 16-bit seg-ment length resolution is toocoarse, memory depth and frequency can be traded.

Sub-frequencies:For applications requiring dif-ferent frequencies at a fractionof the system clock, the ratiocan be divided or multipliedby 2, 4, 8, or 16. This influ-ences the dependency betweensegment length resolution andmaximum memory depth.

Agilent E4832A ParBERT 675 Mbits/s Data ModuleAgilent E4838A ParBERT 675 Mbit/s Generator Front-EndAgilent E4835A ParBERT 675 Mbit/s Analyzer Front-End


4 slots for the front-ends E4835A*, E4838A

Note:*occupy two front-end slots of the E4832A

E4832A Generator/Analyzer675Mbit/s Module

Figure 1: E4832A Module


*Valid at 15 ... 35ºC room temperature

Synchronization

Synchronization is the methodof automatically adjusting theproper bit phase for data com-parison on the incoming bitstream. The sychronisation canbe performed on PRBS/PRWSand memory-based data but itis not possible on a mix ofPRxs and memory based data.

There are two types of synchronization:• Bit synchronization• Auto delay alignment

Bit synchronization is possibleto cover a bit alignment for atotally unknown number ofcycles. Using memory-baseddata, the first 48 bit withinthe expected data segment willwork as Detect Word whichthe incoming data are com-pared to. When the incomingdata match with this detectword, further analysis willbegin.

Auto Delay alignment will be performed by using the analyz-er sampling delay. Thereforethere is a limited range of50ns while this is possible.

Using Auto Delay alignmentwill provide synchronizationwith an absolute timing rela-tion between a group of ana-lyzer channels. So skew meas-urements are possible.

E4832A Data Generator Timing Specifications(@ 50% of amplitude, 50 Ohm to GND and fastest transition times)Frequency range 333,334 kHz to 675 MHzDelay range 0 to 3.0 µs (not limited by period)Resolution 2 psAccuracy ±50 ps ±50 ppm relative to the zero-delay

Placement *Skew 50 ps typ. after deskewing at customer

levelsPulse width Can be specified as width or % of duty

cycleRange 750 ps to (Period-750 ps)Resolution 2 psAccuracy ±200 ps ±0.1%Duty Cycle 1% to 99%, subject to width limits

E4832A Analyzer Timing All timing parameters are measured at ECL andlevels terminated with 50 Ohm to GNDSample delay = start delay + fine delayFine delay can be changed without stopping**Sampling rate* Same as generatorFine delay range ±1 periodSampling delay range Same as generatorAccuracy Same as generatorResolution Same as generatorSkew Same as generator

*See tables for front-end deratings**Conditions: frequency > 20.8 MHz and by using the finest segment length resolution.


Pattern and Sequencing features of E4832A

Patterns:

Memory-based up to 2Mbit see table 24PRBS/PRWS 2n-1, n=7, 9, 10, 11, 15, 23, 31

Marker Density 1/8, 1/4, 1/2, 3/4, 7/8 at PRBS/PRWS 2n-1, n=7, 9, 10, 11,15

Errored 2n-1, n=7, 9, 10, 11, 15Extended ones or 0 2n-1, n=7, 9, 10, 11, 15

Clock patterns Divide or multiplied by 2, 4, 8, 16User Data editor, file importAnalyzer Auto- On PRBS or memory-based dataSynchronization:** manual or automatic by:

Bit synchronization* with or without automatic phasealignmentAutomatic delay alignment around start sample delay (Range: ±50ns)

BER Threshold: 104 to 109

*Bit synchronization on data is achieved by detecting a 48Bit unique word at the beginning of the segment. Don’t cares within the detect word are possible. In this mode no memory-based data can be sent within the same system. If several inputs synchronize the delay difference between the terminals, it must be smaller ±5 segment length resolution.**Condition: frequency >20.8 MHz and by using the finest segment length resolution.

Depending between the capability of generating PRWS and portwidth. Almost all the combinations are possible except the fol-lowing:PRWS Port Width

27 -1 No restriction29-1 7210-1 3, 11, 31, 33211-1 23215-1 7, 31223-1 47231-1 No restriction

Data rate range, segment length resolution, available memory forsynchronization and fine delay operationData rate range Segment length Maximum memoryMbit/s resolution depth, bits20.834 ... 41.666 1bit 131,00841.667 ... 83.333 2 bits 262,01683.334 ... 166.666 4 bits 524,032166.667 ... 333.333 8 bits 1,048,064333.334 ... 666.667 16 bits 2,097,152

In general it is possible to set higher values for the segmentlength resolution and also at lower frequencies than are indicatedin the table. In this case the fine delay function and the auto-synchronization function are unavailable.


Input/Output

Addressable technologiesLVDS, (P)ECL, TTL, 3.3 V CMOS

Analyzer InputThe analyzer channel can be operated:• Single-ended normal• Single-ended compliment• Differential

For termination there isalways 50 Ohm connected to aprogrammable termination volt-age. In differential mode thereis an additional, selectable 100Ohm differential termination.Independent of the selected termination, there is the choiceof whether the anaylsis of theincoming signal is performedon the input or true differen-tially.

Level Parameters for Differential Generator Front-end E4838A 675 Mbit/sNumber of channels 1, differential Impedance 50 Ohm typ.Data formats RZ, R1, NRZ, DNRZOutput voltage window -2.2 to +4.4 V (doubles into open up to

max. 5 Vpp)Amplitude/Resolution 0.1V to 3.50 V / 10 mVLevel accuracy ±3 %± 25 mV typ. after 5 ns settling time@LVDS/(P)ECL ±1 %±25 mV typ. after 5 ns settling timeVariable transition time range(10-90% of amplitude) 0.5 to 4.5 nsAccuracy ±5%±100 ps@LVDS/(P)ECL (20-80% of amplitude) 0.35 ns typOvershoot/ringing < 7% (< 5% typ).Jitter Data mode <100 ps peak to peak ((80ps typ)

Clock mode 8ps rms typ.Channel addition XOR and analog

1occupy two front-end slots of the E4832A. The E4835A contains two front-ends (E4835AZ) andone common data back end. In this document one front-end is referred to as E4835A.

Two Differential Analyzer Front-Ends E4835A1, 667 MSa/sNumber of channels 2, differential or single-ended (switchable)Impedance 50 Ohm typ.

100 Ohm differential if termination voltage is switched off

Termination Voltage (can be switched off) -2.0 to +3.0 VThreshold voltage range/ -2.00 to +4.50 V/±1% ±20mVThreshold accuracyThreshold resolution 2 mVInput sensitivity Differential 50 mV typ

Single-ended 100 mV typMinimum detectable pulsewidth 400ps typ. at ECL levels

Two ranges selectable:Input voltage range 0 to +5 V and -2 to +3 VPhase Margin with ideal input signal >1UI-100ps

with E4838A Generator >1 UI-180ps


Each ParBERT 81250 system consists of at least one clockmodule, which generates the system clock for at least one generator or analyzer or anymix. Please see the table to theright for a complete compati-bility overview!

SequencingThe sequencing can be used to specify the data flow:• single• looped• infinitely• event handling (branch)• synchronization.

Event HandlingWith the event handling theflow of data generation andAnalysis can be influencedwith external signals at runtime.Usage of Events:• stop and go of data• match loop• intergration with other equipment (ATE)

• trigger on errorFor event trigger resourcesand reaction


Agilent E4809A 13.5 GHz Central Clock ModuleAgilent E4808A High Performance Central Clock ModuleAgilent E4805B 675 MHz Central Clock Module


Modules/Central Clock E4805B E4808A E4809AE4832A - ParBERT 675 Mbit/s • • •E4861A - ParBERT 2.7/1.6 Gbit/s • •E4861B - ParBERT 3.35 Gbit/s • •E4810A/11A - ParBERT 3.3.5 Gbit/s optical •E4866A/67A - ParBERT 10.8 Gbit/s •N4872A/73A - ParBERT 13.5 Gbit/s •E4868B/69B - ParBERT 45 Gbit/s •

E4809A, E4808A and E4805B Sequencing FeaturesNumber of Segments 1 to 30 (every segment looped once)

1 to 60 (no segment looped)Looping levels Up to 4 nested loops plus one optional infinite loop

Loops can be set independently from 1 to 2 repetitionsStart/stop External input, manual, programmed (stop with E4832A only)Event handling React on internal and external events.

E4809A, E4808A and E4805B Event HandlingEvent trigger sourcesEvents can be defined as any combination of the following sources. A maximum of 10 events can be defined.- 8-line trigger input pod for TTL signals- VXI trigger lines TO and T1- Any capture error/or no error detected by one of the analyzer channels- Software command control: an event trigger command issued locally or remotelyReactions to an event can be set per data segment immediately or deferred and can be any combination of:- Data segment jump- Launch trigger pulse to the trigger output of the Clock Module- VXI trigger lines TO and T1 can be set to 01, 10 or 11


Master slave, multi-mainframe,different clock groups.Up to 3 clock modules can be combined to run in one clock grouping by connecting themaster slave cable. This isused to combine channelswhich do not fit into oneframe into one clock group.Omitting the master-slave con-nection will run the channelswithin separated clock groups.A system can be operatedusing different clock groups.So a bunch of channels arecombined with a clock module.The frequencies used can betotally asynchronous or m/nratio (see clock input multipli-er/divider). For separated clockgroups the master slave mustnot be connected. Within onesystem the modules mustalways be of the same type.

E4809A, E4808A and E4805B Trigger Pod characteristicsInput Lines 8, single-endedInput levels TTL compatibleInput threshold 1.5 VInput termination 5 k Ohm pullup to +5 VAbsolute max ratings for input voltages -1.2 V to + 7.0 VCable delay 11 ns typicalsampling clock frequency system frequency/segment length

resolutionTRIGGER OUTPUT CLOCK/REF INPUT

Setup time* 2.5ns -12.5nsHold time * 5 ns 20 ns

*includes the cable delay

E4809A Clock Module specifications Frequency range 20.834MHz…13,5GHzResolution 1HzSSB Phase Noise (at 10kHz offset) <-75dBc at 10GHzLatency External Start Input

• Start IN to Trig OUT with 7/13.5 Gbit/s 16 ns + (2 * system clock * segment resolution ± 1 clock (1)

• Start IN to Data OUT with 7/13.5 Gbit/s 416 ns + (2 * system clock * segment resolution ± 1 clock (1)

• IN to Trig OUT without 7/13.5 Gbit/s 16 ns ± 1 clock (1)• IN to Data OUT without 7/13.5 Gbit/s 48 ns ± 1 clock (1)

Figure 1: E4809A

General:E4809A is a 2-slot centralclock module enhancing thecapabilities of the E4808A by a13GHz clock distribution.ParBERT 81250 13.5 Gbit/smodules are designed to runwith the E4809A 13.5 GHzCentral Clock module.

Deskew Probe

(1) add 3 ns if expander frame is used


E4809A 13.5 GHz Central ClockModule

Clock for Expander Frames

GigaClockMasterClock

Clock Input

Trigger Out

10 MHz Reference In

Start In

Timing Capabilities

The E4809A supports three different operation modes.

• E4809A as system clockThe E4809A distributes clock signals to connected modulesin the range from 20.834 MHzup to 13.5 GHz. The E4809Aprovides GigaClock signals in arange from 500 MHz up to13.5 GHz to the ParBERT81250 13.5 Gbit/s modules(N4872A, N4873A). All other supported modules are workingwith the E4809A MasterClock.

• External Clock modeThe system will run synchro-nously to an external clock,which is connected to theclock module's clock input.There are two different sub-modes available.In the direct clock mode, thePLL (Phase Locked Loop) isbypassed and an external clocksignal can be distributed to allGigaClock connected modules.This direct external clockmode is operating in a rangefrom 500 MHz to 13.5 GHz. Inthis mode the external clockmay be FM or PM modulated.In the indirect external clockmode, the clock modules inter-nal PLL is used to generateflexible MasterClock andGigaClock signals.

• Clock Data Recovery (CDR) modeIf the CDR is used, the CDROut of the Analyzer must beconnected to the Clock Inputof the Clock module.

Start Input

A data sequence generationcan be started by an externalsignal.

Start Input Start Input DC coupled; 3.5mm(f)Threshold range -1.40V to +3,70VZin/Termination voltage 50 Ohm typ. / -2V to +3VSensitivity/max. levels 200mVpp / -3V…+6V

Reference Input

The Reference Input allowsParBERT to run synchronouslywith an external 10MHz clock.Usage of a continuous clock isnecessary. Burst clock can notbe used as an external clock.

Reference Input Reference Input AC coupled; 3.5mm(f)Frequency 10 MHzInput transition time <20nsRequired Duty cycle 50% ±10Zin 50 OhmSensitivity 200mVppRequired Input Phase Noise < -137 dBc @ 10 MHz offset


Clock Input

This input runs ParBERT syn-chronously with an externalclock. Usage of a continuousclock is necessary. Burst clockcan not be used as an exter-nal clock. Two modes areselectable: Indirect externalclock mode (clock module PLLis used) and Direct externalclock mode (clock module isbypassed).

Clock Input AC coupled; 3.5mm(f)Frequency range

Indirect mode 20.834MHz…13.5GHzDirect mode 500MHz…13.5GHz

Clock Input (Indirect mode only) m=1…256; n=1…256Multiplier(m)/divider(n) m x n<=1024; m/n x input freq.

input must fit data range input frequency/n>=5 MHz

Input transition/slope 30 ps typ.Zin 50 OhmSensitivity <150mVRequired Input Phase Noise <75 - 20 log (13.5 GHz / Fin) dBc / Hz

Trigger Output

This output will be used todeliver a trigger signal to aDUT, a Digital CommunicationAnalyzer (Agilent 86100BSeries) or as a stimulus forthe Analyzer deskew.

Trigger Output DC coupled, SMP (f)Frequency up to 675 MHzOutput transition/slope 70 ps typ. 10/90Zout/Termination voltage 50 Ohm / -2 to +3VOutput voltage window -2V to +3VOutput level 0.1 to 1.8 Vpp


External input and ext. clock/ext. ref. input E4805B

Zin/Termination voltage 50 Ohm/-2.10 V to 3.30 VSensitivity/max levels 400 mVpp/-3 V to + 6 V

Coupling dc,Ext. Input: Threshold Range: -1.40 V to +3.70 VExt. Clock/Ext. Ref: acInput transitions/slope < 20ns. Ext. input active edge is selectable

Clock input m=1...256; n=1...256multiplier(m)/ divider (n) m*n<=1024 m/n * input frequency must fit

data range input frequency/n>=1.3 MHZPLL lock time 100msInput frequency/periodExt. Clock 170 kHz - 2.7 GHzExt. Ref 1*, 2*, 5, or 10 MHzRequired duty cycle 50 ±10 %Latency (typical): to trigger Output to channel outputExt. input 16ns ±1 clock 46ns ±1 clock

Ext. clock 15ns 45nsAdd 3ns if an expander frame is used

E4808A50 Ohm/-2.10 V to 3.30 V200 mVpp/-3 V to + 6V for < 9.5Gbit/s300mVpp/-3V to+ 6V for > 9.5 Gbit/sdc, -1.40 V to +3.70 V ac< 20 ns. Ext. Input active edge isselectable

100 ms

170 kHz - 10.8 GHz1*, 2*, 5, or 10 MHz50 ±10 %to trigger Output to channel Output16ns ±1 clock 46ns ±1 clock**

15ns 45nsAdd 3ns if an expander frame is used

* Jitter performance may be degraded ** If frequency=667MHz

E4805B and E4808A CentralClock Modules

The central clock moduleincludes a PLL (Phase-LockedLoop) frequency generator toprovide a system clock.Depending on the frequencychosen, the data modules canbe clocked at a ratio of 1, 2,4, 8, 16, 32, 64 or 256 timeshigher or lower than the system clock.

External start/stop: The data run-ning can be started by anexternal signal applied to theexternal input. With moduleE4832A there is also Stop andGate mode.

Clock outputs for modules

Clock for Expander Frames

Clock/Ref. Input

External Input

Trigger output

Deskew Probe

Figure1: Clock Module

Trigger port input.Master- Slave connection

E4805B and E4808A Clock Module specificationsE4805B E4808A

Frequency range* 1kHZ to 675 MHZ 170 kHz to 675 MHz(can be entered as E4805B will run with: E4808A will run with: period or frequency) - E4866A/E4867A in range of 9.5GHz to

10.8GHzE4808A Clock - E4861A in range of 334 MHz to 2.7GHz - E4861B in range of 20.834 MHz to Module specifications - E4832A in range of 334KHZ to 675 MHz 3.35GHz- E4861A in range of 334 MHz to

2.7GHz- E4832A in range of 334KHZ to 675 MHz

Resolution 1 Hz 1 HzAccuracy ±50 ppm with internal PLL reference ±50 ppm with internal PLL reference

May be limited or enhanced by modules or frontends

Ext. Clock/Ext. Reference: Thisinput runs ParBERT 81250 synchronously with an ext.clock, or when a more accu-rate reference is needed thanthe internal oscillator. Usage ofa continuous clock is necessary. Burst clock cannotbe used as an external clock.Maximum external clock is 2.7GHz for the E4805B and10.8Gbit/s for the E4808A.(Note: no improvement of jitterspecifications will be achieved).

Guided deskew: Individual semi-automatic deskew per channel.The deskew probe 15447Aallows deskew on the DUT's(Device Under Test) fixture.


Trigger OuputCan be used in: • clock mode• sequence mode

In sequence mode a pulse willbe set to mark the start ofany segment.

The trigger output runs to a maximum of 675MHZ. If ahigher speed performanceclock is needed;• A 2.7GHZ Clock can be

obtained from a 2.7 Gbit/s channel operated as a pulseport.

• A 10.8GHZ clock is available from the 10.8 Gbit/s generated module as clock output.

Trigger output characteristics E4805B and E4808ATrigger output signals - Clock mode (up to 675 MHz).

- Sequence ModeOutput impedance 50 Ohm typ.Output level TTL (frequency < 180 MHz), 50 Ohm to GND

ECL 50 Ohm to GND/-2 V, PECL 50 Ohm +3VTrigger advance 30 ns typ. between trigger output and data output/sampling

point (delay set to zero in both cases)Maximum ext voltage -2 V to +3.3 VJitter (int. reference/int. < 10 ps rms (5ps typ.)clock)

Technical SpecificationsAll specifications describe the instru-ment’s warranted performance. Non-

warranted values are described astypical. All specifications are valid

from 10° to 40° ambient temperatureafter a 30 minute warm-up phase,with outputs and inputs terminate

with 50 Ohms to ground at ECL levelsif not specified otherwise.


General Characteristics

Mainframes: See table on page48.

Save/recall: Pattern segments,settings and complete settingsplus segments can be savedand recalled. The number ofsettings that can be stored islimited only by internal diskspace.

Vector import/export: Pattern filescan be imported/exported viaa 3.5 inch floppy disk, LAN orGPIB (IEEE 488.2). File formatis ASCII using a STIL subset.

Programming interface: GP-IB(IEEE 488.2) and LAN. Theinterface to applications suchas C, Visual Basic, or VEEmust be installed. Agilent81200 Plug & Play drivers foreasy programming are avail-able.

Programming language:SCPI 1992.0

Programming times: Vector trans-fer from memory to hardwaredepends on the amount ofdata.

On-line help: Context-sensitive.

Print-on-demand: Getting startedand programming guides canbe printed from .pdf filesincluded in the ParBERT81250 software.

Self-test: Module and systemselftests can be initiated.

Modules

Module size: VXI C-size, 1 slot.

Module type: Register-based;requires ParBERT 81250 usersoftware E4875A supplied withthe mainframes.

Weight: (including front-ends)Net: 2kg.

Shipping: 2.5 kg.

Warranty: 3 years return forrepair service, depending onsupport option.

Re-calibration period: 1 year.

Agilent Technologies QualityStandardsThe ParBERT 81250 is pro-duced to the ISO 9001 inter-national quality system stan-dard as part of AgilentTechnologies’ commitmentto continually increasing cus-tomer satisfaction throughimproved quality control.

Programming TimesProgramming time

Change of levels 6 ms typ.Change of delay 16 ms typ. Not applicable in run modeChange of period 60 ms typ. For one E4805 with one

E4832A. Not applicable in run mode.Increases with the number of modules but

Stop & start 32 ms typ.Synchronization* 50 ms typ. (without phase alignment)

110 ms typ. with 20% phase accuracy @ 660 MHz650 ms typ. with 1% ohase accuracy @ 660 MHz

Download valuesSystem with 4 channels < 1.5 s typ.1000,000 bit eachSysten with 120 channels < 20 s typ.1 Mbit eachSystem with 40 channels < 10 s typ.1 Mbit each+Add numbers for each synchronzing analyzer within one module

Cooling requirements for modules with front-ends installedModules ∆∆P mm H2O Air Flow Max

Liter/s ∆∆TempE4805B 0.25 3.6 10 °CE4808A 0.25 3.6 10 °CE4809A 1.08 3.7 12 °CE4832A 0.30 4.7 15 °CE4861A 0.40 5.2 10 °CE4861B* 0.40* 6.6 15 °CE4866A 0.30 5.2 10 °CE4867A 0.30* 5.5 15 °CN4872A/74A 1.20 7.5 13 °CN4873A/75A 0.85 5.4 12 °C


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General Mainframe Characteristics81250A Mainframe

Description E8403A 13 slot VXI C-size frameOrder Description 81250A - 149 (entry frame)

81250A - 152 (expander frame)Number of slots for ParBERT81250 data / clock modules 12Operating Temperature 10°C to 40°CStorage Temperature -20°C to +60°CHumidity 80% rel. humidity at 40°CPower Requirements 90-264 Vac +/- 10%, 47-66 Hz

90-264 Vac +/- 10%, 300 - 440 Hz (not recommended:leaky current may exceed safety limits @ > 132 Vac)

Power available for modules 950 W for 90 - 110 Vac supplies1000W for 110 - 264 Vac supplies

Electromagnetic compatibility EN 55011/CISPR 11 group 1, class A + 26 dBAcoustic noise 48 (56) dBA sounds pressure at low (high( fan speed)Safety IEC 348, UL 1244, CSA 22.2 #231, CE-markPhysical dimensions W: 424.5 mm, 16.71 inches

H: 352 mm, 13.85 inchesD: 631 mm, 24.84 inches

Weight (Net) 26.8 kg (25.3 kg)Weight (shipping) (max.) 72 kg (67 kg)


Short Ordering Guide - Overview

The ParBERT 81250 is a modular instrument, which can be tailored to your specific needs. Thereare Generator and Analyzer channels at different speed classes. The ParBERT 81250 channels con-sist of data modules and front-ends. The 13.5 Gbit/s, 10.8 Gbit/s, 7 Gbit/s and 3.35 Gbit/s opticalare dedicated data modules for Generators and Analyzers. At 3.35 Gbit/s and 2.7 Gbit/s the datamodule houses 2 Frontends, at 675 Mbit/s the data module houses 4 Front-ends. The data mod-ules operate with help of a clock module. The combination of data modules with a clock moduleis called 'Clock Group' and is represented in the ParBERT 81250 Software within one UserInterface. The following table lists the combination of data modules and front-ends together withusable clock modules:

Generator Analyzer Clock Module13.5 Gbit/s N4872 N4873 E4809A Dedicated Modules10 Gbit/s E4866A E4867A E4808A Dedicated ModulesData module7 Gbit/s N4874A N4875A E4809A Dedicated Modules3.35 Gbit/s Front-ends E4862B E4863B E4808A Front-endsData Module E4861B E4861B or E4809A Data Module houses 2 Front-ends2.7 Gbit/s/1.65 Gbit/s E4862A/E4864A E4863A/E4865A E4805B Front-endsFront-ends Data Module E4861A E4861A or E4808A Data Module houses 2 Front-ends675 Mbit/s E4835A E4835A E4805B Front-endsFront-ends Data Module E4832A E4832A or E4808A E4835A provides a pair of analyzers

or E4809A Data Module houses 4 Front-ends

Entry System:

The VXI frame offers 13 slots. Besides data modules and clock modules, there is the need for acomputer interface. The ParBERT 81250 works with an IEEE 1394 FireWire interface, which workswith an external PC (81250 #013, #014) or a laptop (81250 #015). The IEEE 1394 FireWire cardconsumes one VXI slot.Assuming the use of the Firewire interfaceand one Clock module in place, the Entry System canhold up to:

10 channels at 13.5 Gbit/s, 7 Gbit/s11 channels at 10.8 Gbit/s and 3.35 Gbit/s optical22 channels at 3.35Gbit/s or 2.7Gbit/s44 channels at 675 Mbit/s.

In some circumstances these maximum numbers cannot be achieved due to power restrictions.Before finalizing a configuration, it is necessary to calculate the power budget.The 675 Mbit/s Analyzer E4835A always comes as a pair and need to be configured side by side,providing two fully independent analyzer channels.

Max # of 675 Mbits 3.35 Gbit/s or 10.8 Gbit/s 13.5 Gbit/schannels 2.7 Gbit/s 7 Gbit/s

or 1.65 Gbit/sFireWire1 Frame 44 22 11 102 Frames 88 44 22 203 Frames 132 66 33 304 Frames 176 88 44 40

More than 3 frames require more than one clock group.


Multi-Mainframe/Master-Slave:

If the number of channels exceeds the number of available slots in the “entry” frame, it is possi-ble to add expander frames. To add channels within one Clock Group, there is the limit of a max-imum of two expander frames. If data modules are housed in an expander frame they need anadditional clock module, this clock module must be connected to the clock module in the entryframe (master frame) with the help of the master-slave connection. This connection cares for clockand data flow synchronization between the frames. The Master-Slave connection hardware is deliv-ered with the expander frames. Master-Slave connection is only possible between Clock Modules ofsame type.

Aside from the Master-Slave Connection between the Clock modules, the controller interface alsoneeds an extension into the expander frames:- The FireWire interface, consuming one slot, can be “daisy-chained” from frame to frame. Thiswould allow the configuration of a ParBERT 81250 system with virtually an unlimited number ofchannels (within different clock groups, see above limitation of max. channels per clock group).

Different Clock Groups

A clock group consists of a clock module, one or more data modules and the graphical user inter-face allowing to set the parameters. Within one clock group there can be data modules with gen-erators and analyzer front-ends from different speed classes combined as long as with help of thebinary frequency multipliers (…, 1/16, 1/8, 1/4, 1/2, 1 , 2 ,4 ,8 , 16, …) the data rate range possi-ble for each data module can be achieved. The configuration of more than one clock group is pos-sible. This will combine a clock module with one or more data modules. Several clock groups maybe housed in one frame or with help of expander frames. Each clock group will be operated fromits own graphical user interface. The user interface will actually be assigned to a certain hardwareset. If there is more than one clock group, the user interfaces may run from separate PCs, con-nected via LAN. To configure more than one clock group it is recommended:- to run different speeds (non binary ratio) between generators and/or analyzers- to run independent phase ratio between generators and/or analyzers- to make flexible use of data rate range when combining different speed classes- to use custom (memory) based data and use of bit synchronization for the analyzer(s).

Using different clock groups reduces the maximum number of channels given in the table on theprevious page. Within one system using different clock groups, all clock modules must be of sametype. A Master-Slave connection must not be installed between the clock modules if different clockgroups are desired.


Order Information Entry System:

1 x 81250A System Reference1 x 81250 # 149 Mainframe1 x E4805B/E4808A/ 1st Clock ModuleE4809AAdd data modules/front ends

Decide on Controller:1 x 81250A #013 FireWire (IEEE 1394) OC Link to VXI1 x 81250A #014 ext. PCor1 x 81250A #015 Laptop including PCMCIA IEEE 1394 card

Decide on Controller Accessories:1 x 15444A Monitor1 x 15445A ext. CD-ROM

Order Information Master-Slave/Different Clock Groups:

E4805B: clock module (usable with 675Mbit/s and 2.7 Gbit/s module)E4808A: clock module (usable with 675 Mbit/s, 1.65 Gbit/s, 2.7 Gbit/s, 3.35

Gbit/s, 10.8 Gbit/s and 45 Gbit/s modules)E4809A: clock module (usable with 675 Mbit/s, 3.35 Gbit/s, 7 Gbit/s and 13.5

Gbit/s modules)

Specific Rules: Do not mix E4809A, E4808A and E4805B:- Master-Slave Slave connection is possible only between

Clock Modules of the same type- One system must be configured with one type of clock module

Order Information Multi Mainframe:

1 x 81250 #152 FireWire (IEEE 1394) Expander Frame

1 x E4805B/E4808A/ Clock ModuleE4809A

Add data modules/front-ends

Cable Kit AccessoriesP/N Cable Kit Description No. of Cables Connectors to be used with Bandwidth Matching Length add. Parts

included15441A SMA to SCI 10 SMA (m) - SCI (f) 675 Mbit/s tt>= 500ps no 1.5 m 4 SCI adapters15442A SMA 4 SMA (m) - SMA (m) 675 Mbit/s/ tt>= 100ps no 1 m -

2.7/(3.35*) Gbit/s15443 SMA Matched Pair 2 SMA (m) - SMA (m) 675 Mbit/s/ tt>= 100ps yes 1 m -

2.7/(3.35*) Gbit/sN4869A SMA & Phase Shifter 3 SMA (m) - SMA (m) E4866A Out to tt>= 50ps adjustable 0.4 m mech. Phase

N4868A In Shifter +-50psN4870A 1.85 mm Matched 2 1.85/2.4 mm - N4868A Out tt>= 15ps +/- 1.5 ps 0.63 m -

1.85/2.4 mm E4868A/B OutE4869A/B In

N4871A SMA Matched 2 SMA (m) - SMA (m) 3.35/10.8 Gbit/s tt>= 50ps +/- 1.5 ps 1 m -frontends

N4910A 2.4 mm matched pair 2 2.4 mm - 2.4 mm 7 Gbit/s, 0.60 m -13.5 Gbit/s


Product Structure - ParBERT 81250 forOracle

Valid from 12th June 2002P/N Option Description81250A ParBERT 81250

#013 IEEE 1394 PC link to VXI#014 External PC#015 Laptop including PCMCIA IEEE 1394 card#149 Mainframe#152 IEEE 1394 'Firewire' Expander Frame#0B0 Do not include Tutorial CD Rom#AX4 Rack flange kit

SoftwareE4875A One licence and software CD ROM for

ParBERT 81250

Clock ModulesE4805B 675 MHz Central Clock Module

#UK6 Commercial cal. certificate w/ test dataE4808A High Performance Central Clock Module

#UK6 Commercial cal. certificate w/ test dataE4809A 13.5 GHz Central Clock Module

#UK6 Commercial cal. certificate w/ test data

Data Modules & Front EndsE4832A 675 Mbit/s Gen./An. Module

#UK6 Commercial cal. certificate w/ test dataE4835A Two Differential Analyzer Front-Ends, 675

Mbit/sE4838A Differential Generator Front-End, 675 Mbit/sE4861A 2.7 Gbit/s Gen./An. Module

#UK6 Commercial cal. certificate w/ test dataE4864A Generator Front-End 1.65 Gbit/s

#UK6 Commercial cal. certificate w/ test dataE4865A Analyzer Front-End 1.65 Gbit/s

#UK6 Commercial cal. certificate w/ test dataE4862A Generator Front-End 2.7 Gbit/s

#UK6 Commercial cal. certificate w/ test dataE4863A Analyzer Front-End 2.7 Gbit/s

#UK6 Commercial cal. certificate w/ test dataE4861B 3.35 Gbit/s Gen./An. Module

#UK6 Commercial cal. certificate w/ test dataE4862B Generator Front-End 3.35 Gbit/s

#UK6 Commercial cal. certificate w/ test dataE4863B Analyzer Front-End 3.35 Gbit/s


Warranty & ServicesAll systems automatically have 1 yearReturn to Agilent warranty (if bought asseparate pieces).All bundles (81250A, E4894A/95A/94B/95B/96A/97A) have 1 year on-site warranty. An on-site repair contract or Return to Agilent con-tract can be purchased once the 1 year on-site warran-ty has expired. Additional on-site warranty can be chosen for 3 or 5years. On-site productivity assistance is included in the bun-dles. Standard compliant and commercial calibration can bechosen for 3 or 5 years.Commercial calibration is NOTautomatically included.

E4810A #001 3.35 Gbit/s 850nm Electrical/Optical Generator Module

#UK6 Commercial cal. certificate w/ test dataE4811A #001 3.35 Gbit/s 750-1610nm

Optical/Electrical Analyzer Module (calibrated @ 850 nm)

#UK6 Commercial cal. certificate w/ test dataN4874A Generator Module 7 Gbit/sN4875A Analyzer Module 7 Gbit/sE4866A Generator Module 10.8 Gbit/s

#UK6 Commercial cal. certificate w/ test dataN4868A 10Gbit/s Booster Module (1 diff. or 2

single ended ch.)#UK6 Commercial cal. certificate w/ test data#001 10Gbit/s Booster Module (2 diff. or 4

single ended ch.)#U01 Commercial cal. certificate w/ test data

for N4868A-001E4867A Analyzer Module 10.8 Gbit/s

#UK6 Commercial cal. certificate w/ test dataN4872A Generator Module 13.5 Gbit/s

#UK6 Commercial cal. certificate w/ test dataN4873A Analyzer Module 13.5 Gbit/s

#UK6 Commercial cal. certificate w/ test dataE4868B 45/43.2Gbit/s Multiplexer Module

#UK6 Commercial cal. certificate w/ test dataE4869B 4 5/43.2Gbit/s Demultiplexer Module



43G Bundles

E4894B 43.2 Gbit/s Pattern Generator BundleUK6 Commercial cal. certificate w/ test data

E4895B 43.2 Gbit/s Error Detector BundleUK6 Commercial cal. certificate w/ test data

E4896A 45Gbit/s & 3.35Gbit/s Pattern Generator BundleUK6 Commercial cal. certificate w/ test data

E4897A 45Gbit/s & 3.35Gbit/s Error Detector BundleUK6 Commercial cal. certificate w/ test data

Accessories15440A Adapter kit: 4* SMA (M) I/O adapters15441A Cable kit: 10*SMA (m) to SCI connector15442A Cable kit: 4*SMA (m) to SMA (m)15443A Matched cable pair15444A Monitor15445A External CD-ROM15446A 8-line trigger input pod15447A Deskew ProbeE4839A Test fixture15448A Pogo cable kit: 4*SMA(m) & 2 Pogo adapter15449A DUT board 50 Ohm impedanceN4869A Cable Kit: 3 cables with phase adjuster for connecting E4866A with

N4868AN4870A Cable Kit: 2.4mm for N4868A outputN4871A Cable Kit: SMA matched pair,50psN4910A Cable Kit: matched cable pair for 13.5GN4911A #002 Adapter 3.5 mm female to 2.4 mm maleN4912A 2.4 mm 50 Ohm termination, male connectorN4913A 4 Ghz deskew probe


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Product specifications and descriptions inthis document subject to change withoutnotice.

© Agilent Technologies 2003Printed in Germany, 19 March 20045968-9188E

Related Literature Publication Number• 10GbE Technology and 5988-6960EN

Device Charaterization,Product Note

• Agilent ParBERT 81250 13.5 Gbps 5988-9201ENParallel Bit Error Ratio Test Platform, Photocard

• Agilent ParBERT 81250 7 Gbps 5988-9678ENParallel Bit Error Ratio Test Platform, Photocard

Documents

Agilent ParBERT 81250 Parallel Bit Error Ratio Testercc.ee.nchu.edu.tw/~aiclab/public_htm/Tools/measurement/... · 2007. 9. 6. · Generator Formats DNRZ, RZ, R1 2.7G:DNRZ DNRZ, separate