University of be prepared for the Next Revolution ...xputers.informatik.uni-kl.de/staff/hartenstein/lot/DDECS2002... · Tera Thinking Machines Saxpy Scientific Computer Systems (SCS)

The 5th IEEE Workshop on Design & Diagnosis of

Electronic Circuits & Systems (DDECS'02)

Configware / Software Co-Design:

be prepared for the Next Revolution! .

Reiner Hartenstein

University of Kaiserslautern

Brno, Czech Republic, April 17 - 19, 2002

viewgraph downloading: link in

http://kressarray.de

http://www.fit.vutbr.cz/events/ddecs02/

© 2001, [email protected] http://KressArray.de


Xputer Lab

2

Semiconductor Revolutions

“Mainstream Silicon Application is switching every 10 Years”

TTL µproc., memory

“The Programmable System-on-a-Chip is the next wave“

custom

standard

1957

1967

1977

1987

1997

2007

ASICs, accel’s

LSI, MSI 1st

Design

Crisis

2nd

Design

Crisis

Tredennick’s Paradigm Shifts

hardwired

algorithm: fixed

resources: fixed

procedural programming

algorithm: variable

resources: fixed

structural programming

algorithm: variable

resources: variable



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3

Impact of Makimoto’s wave

TTL µproc., memory

custom

standard

ASICs, accel’s

LSI, MSI

1957

1967

1977

1987

1997

2007

Procedural personalization via RAM-based

Machine Paradigm

Personalization (CAD) before fabrication

structural personalization:

RAM-based before run time

Software Industry’s Secret of Success

Repeat Success Story by new Machine Paradigm !

Configware Industry



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4 © 2001, [email protected] http://KressArray.de


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Reconfigurable goes mainstream

Topic adopted by congresses: ASP-DAC, DAC, DATE, ISCAS, SPIE ....

http://www.lirmm.fr/fpl2002/

FPL 2002: 214 Submissions -sensational increase by 83%

• FCCM, FPGA (founded 1992), and FPL (founded 1991 at Oxford, UK): International Conference on Field-programmable Logic and Applications

• FPL 2002, La Grande Motte (Montpellier, France), Sept. 2 – 4



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5

Makimoto’s 3rd wave

Reconfigurability

The next Revolution:

1978

Transistor entry: Applicon, Calma, CV ...

1992

Synthesis: Cadence, Synopsys ... 1985

Schematics entry: Daisy, Mentor, Valid ...

[Keutzer / Newton]

EDA industry paradigm switching every 7 years

1999 (Co-) Compilation &

Data-stream-based (r)DPAs [Hartenstein]

2006

Paradigm Shift

Mainstream

Tornado

[Richard Newton]

[Keutzer / Newton]

82% of designers hate their tools



Xputer Lab



Xputer Lab

missing the next revolution

Ignoring reconfigurable computing by teaching computing fundamentals within our CS curricula

causing the waste billions of dollars.

is one of the biggest mistakes in the history of information technology application



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7

.... it‘s an alternative culture ....

• now the area is going mainstream: a rapidly widening audience of non-specialists gets interested ...

• severe communication gaps due to educational deficits

• not only to users: still many hardware and EDA experts ask: isn’t it just logic design on a strange platform ?

• it is time to clarify and popularize fundamental aspects and to explain, that it is a fundamentally different culture



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>> Outline

• Introduction

• The CPU Machine Paradigm

• DPU & DPA : Antimatter of Computing

• Reconfigurable Computing

• Dominance of Embedded Systems http://www.uni-kl.de



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Antimatter Search

.... the Antimatter of CPU-based Computing

•Reconfigurable or Hardwired: Datastream-based Computing is the Antimatter of classical Computing

•This Antimatter has been mainly ignored

• „Antimatter: where is it ?“



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10

The anti universe

•Paul Dirac predicted a complete anti universe consisting of antimatter

•“There are regions in the universe, which consist of antimatter .....

•We are not aware, that there is a new area in computing sciences , which consists of antimatter of computing

• .... But there are asymmetries”

•Reconfigurable Computing is made from this antimatter, especially if it’s data-stream-based

•when a particle hits its antiparticle, both are converted into energy: Annihilation

• .... But there are asymmetries

•and Annihilation (CS curricula)



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11

Anti atom created

• 1956: anti neutron created on Bevatron

• 1928: Paul Dirac: „there should be an anti electron having positive charge“ (Nobel price 1933)

• 1932: Carl David Anderson detected this „positron“ in cosmic radiation (Nobel price 1936)

• 1955 Owen Chamberlain et al. create anti proton on Bevatron

• 1954: new accelerators: cyclotron, like Berkeley‘s Bevatron

• 1965: creation of a deuterium anti nucleus at CERN

hydrogen anti hydrogen

• 1995: hydrogen anti atom created at CERN – by forcing positron and anti proton to merge by very low energy.

sorry, there is no nobel price in CS



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Matter & Antimatter: Atom and Anti Atom

The World of Matter Machine paradigm: the Atom

Anti Matter

Machine paradigm: Anti Atom

+ + -

- - +



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13

Informatics: Matter & Antimatter:

Anti Machine

Machine and Anti Machine

+ CPU

- 1936 1st el. computer (Konrad Zuse)

Machine paradigm: „von Neumann“ Computer

1946 v. N. machine paradigm 1971 1st microprocessor (Ted Hoff) 1979 „data streams“ (systolic array: Kung / Leiserson)

1995 rDPA / DPSS (supersystolic: Rainer Kress)

data-procedural: Xputer

- DPU

+

1990 Xputer machine paradigm



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>> The CPU Machine Paradigm

• Introduction

• The CPU Machine Paradigm – Concurrency

• DPU & DPA: Antimatter of Computing – DPA

• rDPA: Reconfigurable Computing – FPGA boom




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RAM-based

+ CPU

Data Path

instruction sequencer

RAM

+ simple machine paradigm + scalability

+ relocatability + compatibility

= secret of success of software industry

CPU:



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Nasty Matter

+ CPU

Data Path


Central Processing Unit

RAM

Address Computation Overhead

Instruction Fetch Overhead

central von Neumann bottleneck

extremely power hungry and area inefficient

reconfigurable?

the wrong machine paradigm

alw. new instruction sequencer needed



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>>> Concurrency

• Introduction







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Parallelism by Concurrency

+ -

+ -

- +

- +

+ -

- +

- +

independent instruction streams



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Concurrent Computing

....

Bus(es) or switch box

Data Path


Data Path


Data Path


Data Path


Data Path


Data Path

instruction sequencer extremely inefficient

CPU

•massive switching activity at runtime •may affect far beyond Amdahl‘s law



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Dead Supercomputer Society

•ACRI •Alliant •American Supercomputer •Ametek •Applied Dynamics •Astronautics •BBN •CDC •Convex •Cray Computer •Cray Research •Culler-Harris •Culler Scientific •Cydrome •Dana/Ardent/ Stellar/Stardent

•DAPP •Denelcor •Elexsi •ETA Systems •Evans and Sutherland •Computer •Floating Point Systems •Galaxy YH-1 •Goodyear Aerospace MPP •Gould NPL •Guiltech •ICL •Intel Scientific Computers •International Parallel . Machines •Kendall Square Research •Key Computer Laboratories

[Gordon Bell, keynote at ISCA 2000].

•MasPar •Meiko •Multiflow •Myrias •Numerix •Prisma •Tera •Thinking Machines •Saxpy •Scientific Computer •Systems (SCS) •Soviet Supercomputers •Supertek •Supercomputer Systems •Suprenum •Vitesse Electronics



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>> DPU & DPA: Antimatter of Computing

• Introduction







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Some differences: CPU versus DPU

+ CPU

Data Path


transport- triggered

- DPU

Data Path Unit

DPU

dat

a st

ream

s

datastreams scheduled elsewhere

instruction stream routed here

RAM

data sequencer

RAM

data sequencer

external signal, or

nothing central

no vN bottleneck: multiple ports

no instruction fetch at run time: no overhead



Xputer Lab

23 © 2001, [email protected]


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instructions

program cou n ter: state register

Compiler RAM

Datapath

har dw ired

Sequencer

Computer tightly coupled by compact

instruction code

“von Neumann” does not support soft data paths

Datapath

Xputer

Scheduler

Compiler

RAM

(multiple) sequencer

Datapath Array

“instructions”


Xputer Lab

loosely coupled by decision data bits only

Xputer: The Soft Machine Paradigm reconfigurable

also for hardwired

Computer: the wrong Machine Paradigm

“von Neumann”

s d a ta cou n ter

(anti machine)



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Machine Paradigms

machine category Computer

(“v. Neumann”) Xputer

(no transputer!)

driven by: Instruction streams data streams (no “dataflow”)

engine principles instruction sequencing sequencing data streams

state register program counter (multiple) data counter(s)

communication path set-up

at run time at load time

resource DPU (e.g. single ALU) DPU or DPA (DPU array) etc. data path

operation sequential parallel pipe network etc.



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Programming Language Paradigms

language category Computer Languages Xputer Languages

both deterministic procedural sequencing: traceable, checkpointable

operationsequencedriven by:

read next instruction, goto (instr. addr.),

jump (to instr. addr.), instr. loop, loop nesting

no parallel loops, escapes,instruction stream branching

read next data item, goto (data addr.),

jump (to data addr.),data loop, loop nesting,parallel loops, escapes,data stream branching

state register program counter data counter(s)

addresscomputation

massive memorycycle overhead overhead avoided

Instruction fetch memory cycle overhead overhead avoided

parallel memorybank access interleaving only no restrictions



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>> DPA

• Introduction







Xputer Lab

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hardwired interconnect fabrics

Parallelism at data stream level

- DPU

- DPU

- DPU

- DPU

- DPU

- DPU

- DPU

- DPU

no switching overhead at run time

mapping before fabrication

reconfigurable interconnect fabrics

configured after fabrication

- rDPU

- rDPU

- rDPU

- rDPU

- rDPU

- rDPU

- rDPU

- rDPU



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machine paradigm: some differences

+ CPU

-

- DPA

+ +

+

- DPU

+

no. of streams 1



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DPA = DPU array

- DPA

- DPU

- DPU

- DPU

- DPU

- DPU

- DPU

- DPU

- DPU

- DPU -

DPA

+

+

+

+

+

+

+ +

+

coher

ent

dat

a st

ream

s sp

inni

ng a

roun

d



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DPA-based entire System

- DPA

RAM

RAM RAM

RAM

RAM

RAM

RAM RAM

memory communication architecture

mapping before fabrication



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DPA-based entire System

- rDPA

RAM

RAM RAM

RAM

RAM

RAM

RAM RAM

mapping after fabrication

reconfiguration

RAM

reconfigurable memory communication architecture

M. Herz, et al.: Memory Organisation for Stream-based Reconfigurable Computing; IEEE ICECS 2002, Sept. 15-18, 2002, Dubrovnik, Croatia

1995 rDPA Rainer Kress



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>> rDPA: Reconfigurable Computing

• Introduction







Xputer Lab

33 © 2001, [email protected] http://www.fpl.uni-kl.de


Xputer Lab

Commercial rDPA

XPU family : PACT AG, Munich

XPU128 http://pactcorp.com



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rDPU not used used for routing only operator and routing port location markerLegend: backbus connect

array size: 10 x 16 = 160 rDPUs à 32 bits

http://kressarray.de

Academic DPA example

rout thru only

not used backbus connect

SNN filter KressArray Mapping



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Super Pipe Networks

pipeline properties array applications

shape resources

mapping scheduling

(data stream formation)

systolic array

regular data

dependencies only

linear only

uniform only

linear projection or algebraic synthesis

super-systolic DPA

no restrictions simulated

annealing or P&R algorithm

(e.g. force-directed) scheduling algorithm

*) KressArray [ASP-DAC-1995]



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>> The FPGA boom

• Introduction



• rDPA: Reconfigurable Computing – The FPGA boom

• The Dominance of Embedded Systems http://www.uni-kl.de



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Top 4 FPGA Manufacturers 2000

Xilinx 42%

Altera 37%

Lattice 15%

Actel 6%

Top 4 PLD Manufacturers 2000

total: $3.7 Bio

• [Dataquest] > $7 billion by 2003.

• PLD vendors’ and their alliances provide libraries of “soft IPs” Configware Market

• fastest growing semiconductor market segment



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Soft rDPA ?

Memory soft CPU

miscellanous

HLL Compiler

• Rapid technology progress

• 50 million system gates soon

• FPGAs f. relocatable configware code ?

• Compatibility at configuration code level ?

• Slower clock: compensated by more parallelism: low power

• Even large rDPAs as a soft IP become feasible

• By >2005: don’t care about area efficiency ?



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>> The Dominance of Embedded Systems

• Introduction




• The Dominance of Embedded Systems http://www.uni-kl.de



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Ubiquitous embedded systems

20 billion µprocessors (2001)

> 90% in embedded systems

10 times more programmers will write embedded applications than computer software by 2010

That’s where our graduates will go

Embedded systems means:

• hardware / software co-design

• configware / software co-design

• hardware / configware / software co-design



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Annihilation?

- +

-

+ -

+ avoidable

by tools ....



Xputer Lab



Xputer Lab

Jürgen Becker’s Co-DE-X Co-Compiler

Analyzer / Profiler

Host Software

GNU C compiler

para d igm Computer machine

DPSS KressArray Configware

X-C compiler

Xputer machine paradigm

Partitioner

X-C is C language extended by MoPL X-C

Resource Parameters

supporting different platforms

supporting platform-based design



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CS education .....

hardware person

procedural

structural

software person

Configware / Software Co-Design? Hardware / Software Co-Design?



Xputer Lab



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However, current CS Education ….

Hardware invisible: under the surface

… is based on the Submarine Model

Brain usage: procedural-only

Algorithm

Assembly Language

procedural high level Programming Language

Hardware

This model disables ...



Xputer Lab



Xputer Lab

Hardware, Configware

Hardware and Software as Alternatives

Algorithm

Software

partitioning

Software only

Software & Hardw/Configw

procedural structural

Brain Usage: both Hemispheres

Hardw/Configw only



Xputer Lab



Xputer Lab

Dominance of the Submarine Model ...

Hardware

... indicates, that our CS education system produces zillions of mentally

disabled Persons

(procedural) structurally disabled

… completely disabled to cope with solutions other than software only

It‘s time to attack the software faculty dictatorship. Get involved!



Xputer Lab



Xputer Lab>>> thank you

thank you for your patience



Xputer Lab



Xputer Lab>>> END

Documents

University of be prepared for the Next Revolution ...xputers.informatik.uni-kl.de/staff/hartenstein/lot/DDECS2002... · Tera Thinking Machines Saxpy Scientific Computer Systems (SCS)