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√

30TH

APRIL 2010 30TH

APRIL 2010

PROF. DR. ABU KHARI BIN A’AIN 860822-35-5119

LEE CHIA YUN

22 AUGUST 1986

ANALOG MULTIPLIER DESIGN USING 0.18µm

SILTERRA TECHNOLOGY

2009/2010

“I acknowledge that I have studied this piece of work and in my opinion it is in

accordance with the scope requirement and quality for the purpose of awarding the

Bachelor of Engineering (Computer).”

Signature :

Name of Supervisor : Prof. Dr. Abu Khari bin A‟ain

Date : 30th

APRIL 2010

ANALOG MULTIPLIER DESIGN USING 0.18µm SILTERRA TECHNOLOGY

LEE CHIA YUN

A thesis submitted in partial fulfilment of the

requirements for the award of the degree of

Bachelor of Engineering (Computer)

Faculty of Electrical Engineering

Universiti Teknologi Malaysia

APRIL 2010

ii

I declare that this final year report entitled „Analog Multiplier Design Using 0.18µm

Silterra Technology’ is the result of my own studies and design except as cited in the

references. This work has not been accepted for any degree and is not concurrently

submitted in candidature of any other degree.”

i

Signature : .....................................

Name of Author: LEE CHIA YUN

Date : 30th

April 2010

iii

To my beloved mother, father, sisters and family members

iv

ACKNOWLEDGEMENT

Firstly, I would like to express my thankfulness to my supervisor, Prof. Dr.

Abu Khari bin A‟ain for the guidance and encouragements given throughout the

progress of this project. He has been so caring and kind to make me feel comfortable

under his supervision.

Secondly, I feel appreciated that I have family members who have been so

tolerant and supportive of me all these years. Thanks again for their pushing power,

love and emotional supports that they had given to me.

Besides that, I would also like to thank our Microelectronics lab assistant and

staffs, En Mohd Helmy Abdullah and En Ezam for their full co-operations, guidance

and assists in this project.

Nevertheless, my great appreciation is dedicated to my SEC course-mates of

year 2006 and those whom involve directly or indirectly with this project.

v

ABSTRACT

Multiplier is an essential part for many analog applications. It is used to

produce a linear product between two analog signals. It is used in many applications

such as voltage-controlled amplifier, ring modulator, product detector, frequency

mixer, companding, squelch, analog computer, analog signal processing, automatic

gain control, true RMS converter, analog filters. Since analog CMOS IC design is

fast improving in this few years, each function from the components now is getting

more demanding. Most multiplier nowadays only work in two quadrant or single

quadrant. Hence, to design analog multiplier, hand calculations and simulations is

needed. Here, Cadence is used to simulate the design. Basically, the analog

multiplier design can function in four quadrant, produce above average linearity

under 1.8V power supply.

vi

ABSTRAK

Pendarab merupakan bahagian yang penting dalam kebanyakan aplikasi

analog. Pendarab digunakan untuk menghasilkan hasil darab antara dua isyarat

analog. Aplikasinya termasuklah penguat pengendalian voltan, „ring modulator‟,

pengesan produk, pengadun frekuensi, „companding‟, „squelch‟, komputer beranalog,

pemprosesan isyarat analog, „automatic gain control‟, pengubah RMS benar, penapis

analog. Disebabkan bidang rekaan CMOS IC pesat membangun kebelakangan ini,

setiap fungsi daripada komponen-komponen perlu lebih efisien. Kebanyakan

pendarab masa kini hanya berfungsi dalam dua kuadran atau satu kuadran. Oleh

sebab itu, untuk merekacipta pendarab analog, pengiraan secara manual dan simulasi

menggunakan aplikasi komputer diperlukan. Untuk proses simulasi litar ini, Cadence

digunakan sebagai alat bantuan. Secara umumnya, pendarab analog tersebut

berupaya untuk berfungsi dalam empat kuadran di bawah bekalan kuasa 1.8V.

vii

TABLE OF CONTENTS

CHAPTER TITLE PAGE

DECLARATION ii

DEDICATION iii

ACKNOWLEDGEMENT iv

ABSTRACT v

ABSTRAK vi

TABLE OF CONTENTS vii

LIST OF TABLES ix

LIST OF FIGURES x

LIST OF SYMBOLS xii

LIST OF ABBREVIATIONS xiii

LIST OF APPENDICES xiv

1 INTRODUCTION 1

1.1 Background 1

1.2 Objectives 2

1.3 Scope Of Work 2

1.4 Outline of Thesis. 3

1.5 Summary of Works 3

2 THEORY AND LITERATURE REVIEW 5

2.1 Introduction 5

2.2 Theory 5

2.3 Literature Review 6

2.3.1 Online Journals and Papers 6

3 METHODOLOGY 12

viii

3.1 Introduction 12

3.2 Software Implementation 14

4 RESULTS AND DISCUSSIONS 25

4.1 Introduction 25

4.2 Design of Op-amp 26

4.2.1 Simulation Model 26

4.2.2 Bias Model 30

4.3 Analog Multiplier 34

5 CONCLUSION AND RECOMMENDATION 40

5.1 Conclusion 40

5.2 Problems 40

5.3 Recommendations 41

REFERENCES 42

APPENDIX 43

ix

LIST OF TABLE

TABLE NO. TITLE PAGE

4.1 Total Currents from Each Branch of Analog Multiplier 35

4.2 Total Currents from Each Branch of Differential Amplifier 36

4.3 Total Power for the Analog Multiplier 36

4.4 Voltages for the Analog Multiplier at Different Sweep Voltages 37

4.5 Linearity Error for the Analog Multiplier 38

4.6 Comparisons between Designs 38

x

LIST OF FIGURE

FIGURE NO. TITLE PAGE

1.1 Gantt Chart of the Project Schedule for Semester 1 4

1.2 Gantt Chart of the Project Schedule for Semester 2 4

2.1 Block Diagram of Analog Multiplier 6

2.2 Linearity Example 6

2.3 Analog Multiplier Circuit (a) 7

2.4 Proposed Combiner Circuit for Circuit (a) 7

2.5 Block Diagram for Circuit (a) 7

2.6 Analog Multiplier Circuit (b) 9

2.7 Linearity Errors With / Without Body Effect versus (a) x (when y =

0.2V) (b) y (when x = 0.2V) 10

2.8 New Proposed Subtractor Circuit 10

2.9 Analog Multiplier Circuit (c) 11

3.1 Analog IC Design Process Model 13

3.2 VNC Viewer 14

3.3 Cadence 14

3.4 Library Path Editor 15

3.5 Library Manager 16

3.6 Adding New Library 17

3.7 Technology File for New Library 18

3.8 Attach Design Library to Technology File 18

3.9 Create New File 19

3.10 Virtuoso Schematic Editing 19

3.11 Composer Schematic Editor Window 20

3.12 Simulation under Analog Environment 21

3.13 Simulation Window 22

3.14 Choosing Analysis 22

xi

3.15 Direct Plot 23

3.16 Trace Marking on Graph Plotted 24

4.1 Overall Analog Multiplier Circuit Design 25

4.2 Overall Analog Multiplier Circuit Design in Cadence 26

4.3 Simulation Model for Op-amp Design 27

4.4 Gain Response of Analog Multiplier Design 28

4.5 Netlist produced 29

4.6 Graph of Analog Multiplier Produced by Simulation Model 29

4.7 Basic Differential Amplifier 30

4.8 Common Source Amplifier 31

4.9 nMOS as Current Source 31

4.10 Overall Differential Amplifier 32

4.11 Overall Differential Amplifier in Cadence 32

4.12 Transfer Curve Produced by Bias Model 33

4.13 DC Response of Analog Multiplier Design 34

4.14 Gain and -3 dB Bandwidth of Analog Multiplier 35

4.15 Linearity of Analog Multiplier 36

xii

LIST OF SYMBOLS

µ - unit in terms of micro, in which is 10-6

in decimals

m - unit in terms of mili, in which is 10-3

in decimals

M - unit in terms of mega, in which is 106 in decimals

G - unit in terms of giga, in which is 109 in decimals

Hz - Hertz, frequency defined as the number of cycles per second

of a periodic phenomenon

W - Watt, derived unit of power

V - Volt, derived unit of electromotive force, "voltage"

Vp-p - peak-to-peak voltage

dB - logarithmic unit of measurement that expresses the magnitude

of a physical quantity

IDS - Current flowing from the drain to the source in MOSFET

VDD - Voltage Source

xiii

LIST OF ABBREVIATIONS

UTM - Universiti Teknologi Malaysia

IC - Integrated Circuit

FPGAs - Field Programmable Gate Arrays

RAM - Read Access Memory

ROM - Read Only Memory

ASICs - Application Specified ICs

RF - Radio frequency

PLL - Phase-locked loops

Op-amps - Operational amplifiers

EDA - Electronic design automation

PCBs - Printed circuit boards

MOSFETs - Metal–oxide–semiconductor field-effect transistor

nMOS - n-channel MOSFET

VLSI - Very Large Scale Integration

CMOS - Complementary metal–oxide–semiconductor

VNC - Virtual Network Computing

OS - Operating System

R - Resistor

L - Inductor

C - Capacitor

DC - Direct Current

xiv

LIST OF APPENDICES

APPENDIX TITLE PAGE

A Linearity 43

B Transistor parameters in Multiplying Quad of

Analog Multiplier / Power Dissipation 45

C Transistor parameters in Op-amp of

Analog Multiplier / Power Dissipation 47

1

CHAPTER 1

INTRODUCTION

1.1 Background

Integrated circuit (IC) design is a major part of electrical engineering, where

it requires one to have knowledge on logic and circuit design techniques before one

can be familiar with IC design. ICs are miniature components that built into an

electrical network on a monolithic semiconductor substrate by photolithography. In

simpler means, ICs are minute electrical components that can function as what it is

required to.

IC design can be categorized into different categories of digital and analog IC

design. Digital IC design is used to produce components like microprocessors,

FPGAs, memories (RAM, ROM and flash) and digital ASICs. On the other hand,

analog IC design concentrates in power IC design and RF IC design. It is used in

design of op-amps, linear regulators, PLL, oscillators and active filters. At the same

time, analog IC design is more concerned with the physics of the semiconductor

devices such as gain, matching, power dissipation and resistance.

Analog multiplier is a part of analog IC design. Literally, it is a device that

takes two analog signals and produces an output which is their product. It is used to

implement related function like squares and square-roots. There are several types of

analog multipliers namely, single quadrant analog multiplier, two quadrant analog

multiplier and four quadrant analog multiplier. A four quadrant multiplier is one

where inputs and outputs may swing positive and negative, while two-quadrant

2

multiplier only has one input that has one polarity. Besides that, single quadrant

analog multiplier only has inputs and outputs with only one polarity.

In terms of usage, analog multiplier is much more preferred than op-amps

because they are far more susceptible to noise and offset voltage-related problems.

The application of analog multiplier includes voltage-controlled amplifier where if

one input of an analog multiplier is held at a steady-state voltage, the output will be

the version of another input scaled according to the first input.

1.2 Objectives:

This final year project is to design an analog multiplier using 0.18µm Silterra

process with 1.8V power supply that can produce:

◦ Four-Quadrant

◦ At least 2MHz bandwidth

◦ At most 3mW power dissipation

1.3 Scope of Work:

To implement this final year project, reference book regarding the topic, read

journals and papers from internet, learn Cadence tools. To access to Cadence

software, fast internet connection is important to connect to the server in UTM.

Besides that, consultation from supervisor is vital for any queries occurred during the

project implementation. Regarding about the instructions to use Cadence, assist from

Mr. Ezam is essential when facing a problem.

3

1.4 Outline of Thesis.

This thesis consists of five chapters. In the first Chapter, it discusses about the

objective and scope of this project as well as summary of works. Meanwhile in

Chapter 2, there will be more discussions on theory and literature reviews that have

been done. It depicts other designs and hard works achieved by other academicians

from all over the world.

In Chapter 3, the discussion will concentrate on the methodology of software

implementation of this project. The result and discussion will be presented in Chapter

4. Last but not least, Chapter 5 discusses about the conclusion of this project and

future work that can be done.

1.5 Summary of Works

Implementations and works of the projects are summarized into the following

Gantt chart in Figure 1.1 and Figure 1.2 in which both shows the works that had been

implemented in the first and second semester.

4

Figure 1.1: Gantt Chart of the Project Schedule for Semester 1

Figure 1.2: Gantt Chart of the Project Schedule for Semester 2

5

CHAPTER 2

THEORY AND LITERATURE REVIEW

2.1 Introduction

This chapter includes basic theories of analog multiplier and literature

reviews from online journals and papers.

2.2 Theory

Baker, Li, Boyce (1997) shows the ideal output of the multiplier is

Vout = Km·VxVy, where Km = multiplier gain

Unit = V-1

Taking into consideration that ideal devices do not exist in these modern days,

the non-ideal case will produce

Vout = Km(Vx+Vosx)(Vy+Vosy)+Vosout+Vxn+Vy

m

where Vosx, Vosy, Vosout = offset voltages associated with x-input, y-input and output

Vxn, Vy

m = non-linearities

6

Figure 2.1: Block Diagram of Analog Multiplier

Linearity is the maximum deviation in percentages between a straight line

and the actual characteristic curve for some range of input voltages. It can be shown

as follows:

Figure 2.2: Linearity Example

2.3 Literature Review

2.3.1 Online Journals and Papers

Numerous researches and papers on analog multipliers have been done in the

recent years. Hsiao and Wu (1997) proposed a circuit which looks like follows:

7

Figure 2.3: Analog Multiplier Circuit (a)

Here, they proposed a new method which used combiner circuit which looks

like follows:

Figure 2.4: Proposed Combiner Circuit for Circuit (a)

The circuit can be represented by the following block diagram.

Figure 2.5: Block Diagram for Circuit (a)

8

The main concept from the author‟s viewpoint can be initiated from equations

below.

𝑍𝑖 = 𝐴1𝑋𝑖2 + 𝐴2𝑌𝑖

2 + 𝐴3𝑋𝑖 + 𝐴4𝑌𝑖 + 𝐴5 i = 1 ~ 4

𝑍𝑖 = 𝐵1𝑋𝑖2 + 𝐵2𝑌𝑖

2 + 𝐵3𝑋𝑖 + 𝐵4𝑌𝑖 + 𝐵5 i = 5,6

This further derives the individual output of each combiner circuit referring to

the Fig. 2.3 which gives

𝑍1 = 𝐴1(𝑉1+𝑣1)2 + 𝐴2(𝑉2+𝑣2)2 + 𝐴3(𝑉1+𝑣1) + 𝐴4(𝑉2+𝑣2) + 𝐴5

𝑍2 = 𝐴1(𝑉1−𝑣1)2 + 𝐴2(𝑉2−𝑣2)2 + 𝐴3(𝑉1−𝑣1) + 𝐴4(𝑉2−𝑣2) + 𝐴5

𝑍3 = 𝐴1(𝑉1+𝑣1)2 + 𝐴2(𝑉2−𝑣2)2 + 𝐴3(𝑉1+𝑣1) + 𝐴4(𝑉2−𝑣2) + 𝐴5

𝑍4 = 𝐴1(𝑉1−𝑣1)2 + 𝐴2(𝑉2+𝑣2)2 + 𝐴3(𝑉1−𝑣1) + 𝐴4(𝑉2+𝑣2) + 𝐴5

𝑍5 = 𝐵1𝑍12 + 𝐵2𝑍2

2 + 𝐵3𝑍1 + 𝐵4𝑍2 + 𝐵5

𝑍6 = 𝐵1𝑍32 + 𝐵2𝑍4

2 + 𝐵3𝑍3 + 𝐵4𝑍4 + 𝐵5

Assuming B1=B2 and B3=B4, vout = Z5-Z6 which yields

vout = 8B1(2A1V1+A3)(2A2V2+A4)v1v2 = Kv1v2

This circuit was designed and fabricated by 0.8µm N-well double-poly-

double-metal CMOS technology, where its experimental result showed that under

single 1.2V supply voltage, the circuit has 0.89% linearity error and 1.1% total

harmonic distortion under the maximum-scale input 500mVp-p at both inputs. Besides

that, the measured simulated -3 dB bandwidth is 2.2MHz and the power dissipation

is 2.8 mW. This paper focused more on low power dissipation and high linearity

properties.

Another paper proposed low-power design of analog multiplier by Chen and

Li (2006) where the circuit is as follows:

9

Figure 2.6: Analog Multiplier Circuit (b)

This circuit is intended to perform a linear product of two continuous signal x

and y producing output of z = Kxy. The design started by using electronic devices to

process the input signals, cancel or minimize errors caused by non-linearity of the

devices. Most transistors are biased to operate in the saturation region. To find drain

current in this operating region, we can use the following formula

𝐼𝐷 =1

2𝐾 𝑉𝐺𝑆 − 𝑉𝑇𝐻 2 1 + 𝜆𝑉𝐷𝑆 where

K = µ0CoxW/L (transconductance parameter),

VTH (threshold voltage of the device),

λ (channel length modulation effect for long channel devices)

Chen and Li (2006) proposed to bias the transistors in linear region because

by doing so, one can reduce the drain current while keeping a relatively large input

range. To find drain current in this operating region, we can use the following

formula

𝐼𝐷 = 𝐾 𝑉𝐺𝑆 − 𝑉𝑇𝐻 𝑉𝐷𝑆 −1

2𝑉𝐷𝑆

2 where

K = µ0CoxW/L (transconductance parameter),

VTH (threshold voltage of the device)

From the testing and post-layout simulation result, the circuit can produce

less than 5% linearity error, less than 50 µW power consumption and more than 1

GHz bandwidth. The graph on linearity error is as follows:

10

Figure 2.7: Linearity Errors With / Without Body Effect versus (a) x (when y = 0.2V)

(b) y (when x = 0.2V)

In addition to that, Chutham Sawigun et. al. (2007) proposed analog

multiplier which has low-voltage operation, very low power consumption, high

linearity and high operating frequency. This paper mainly refines the circuit (a)

where the author proposed a subtractor circuit to replace the combiner circuit in

circuit (a).

Figure 2.8: New Proposed Subtractor Circuit

11

Figure 2.9: Analog Multiplier Circuit (c)

The main advantage of this circuit (c) is that it minimizes the use of resistor

and branches to enhance physical area and power consumption. From simulation, the

-3dB bandwidths of the circuit is around 110 MHz for all gains.

12

CHAPTER 3

METHODOLOGY

3.1 Introduction

In this project to design this analog multiplier circuit, Cadence Design

Systems is used as it is widely used in today‟s industry. Cadence Design Systems is

electronic design automation (EDA) software. It is used as tools for designing and

producing electronic systems ranging from printed circuit boards (PCBs) to

integrated circuits.

Firstly, suitable architecture is needed to be identified from numerous sources

including text book, papers and journals as well as internet resources. Basically, the

advantages and disadvantages of the proposed architecture are being discussed on the

papers. Hence, the factors that lead to the pros and cons of the design are being noted.

After identifying the appropriate architecture, hand calculations on the

currents and voltages as well as the sizing of the MOSFETs lead to the desired

results. Formulas studied in Analog CMOS IC Design and VLSI classes can be used

as well.

By calculating some important parameters using hand calculations, the

parameters are then used inside Cadence system where circuits is being drawn and

being simulated. Here, some minor adjustments need to be done in the design in

Cadence to achieve more accurate results.

13

Referring to Figure 3.1, the flow chart shows how a design is being met by

first start with the specification need to be achieved. Then, we need to brain storm to

get the initial idea and evaluate it using simulation tools. If the specification is not

met, we need to improve the design by modifying it. After that, we will simulate it

again. Until the specification is being met, the design will be a solution to the

specification needed.

Figure 3.1: Analog IC Design Process Model

14

3.2 Software Implementation

In order to use the Cadence system, login information is needed to enter the

server situated in Electrical Engineering Faculty. The software used to login is VNC

Viewer developed by RealVNC. By typing the allocated IP address into the field

given, connection is made to the server.

Figure 3.2: VNC Viewer

After logging into the server, a Linux OS system appears where Cadence is

being implemented in Linux environment. To launch Cadence, open terminal and

insert parameter as follow:

Figure 3.3: Cadence

15

Cadence is the main simulation tool used to simulate the analog multiplier

circuit. Besides that, this program is able to design layout, verify layout, convert

format before sending for fabrication.

The first step in Cadence is to insert the 0.18 µm Silterra process package

development kit by first clicking on the “Tools” “Library Path Editor”. A window

will appear. Here, to insert the Silterra process package development kit, the exact

location on where they are in the server is required. A point to be noted is that the

library name should be the same with the folder name that contain the package

development kit. Here, “SILCMOS018” in Library field and

“/home/PDK/CADENCE/SILTERRA_CL018G/C18G_456LMPDK_071210/6LM/S

ILCMOS018” in Path are inserted.

Figure 3.4: Library Path Editor

After inserting the package development kit, a library with “SILCMOS018”

name will appear in the Library Manager. To enter the Library Manager screen, click

on “Tools” “Library Manager”.

16

Figure 3.5: Library Manager

Here, the library “SILCMOS018” is noticed in the library field. After that, we

are ready to start our schematic design. Now we need to start a new design by first

making a new library, for example “NEW” library. To realize that, click on “File”

“New” “Library”. Here, we will have the option to enter the absolute path name if

we want the library created somewhere else than the working directory.

17

Figure 3.6: Adding New Library

Since our design is using 0.18 µm Silterra process, we will need to attach our

design files with an existing techfile, which is the “SILCMOS018”. It can be done by

selecting the options of “Attach to an existing techfile” after clicking “OK” during

the library creation. Here, we can select any library to attach our design to the

technology file. For our design purpose, we need to select “SILCMOS018” and click

“OK” after that. Any notice occurred after this is just a reminder when drawing

layout.

18

Figure 3.7: Technology File for New Library

Figure 3.8: Attach Design Library to Technology File

Now we need to create a new cell where the design of our circuit is being

keyed in to the system. Here, we need to select the new library we created “NEW”

and then click “File” “New” “Cell View”. A window will appear for us to put

19

in the Cell Name. To do that, “New1” is inserted inside the “Cell Name” field.

Finally we click “OK” to complete the procedure.

Figure 3.9: Create New File

Subsequently, a new window will pop-up indicating that we can start our

schematic design. It is the Virtuoso Schematic Editing.

Figure 3.10: Virtuoso Schematic Editing

20

A few points are needed to introduce the Virtuoso Schematic Editing. The

components such as transistors, resistors, op-amps are referred to as “Instance” in

which they are in different libraries depending on the creator. Most components

(transistors, R, L, C, sources, rail terminals, etc.) are in the “analogLib” library. To

edit the properties of the components, press “q” on the component after selecting it.

However for transistors, the model is automatically set according to the technology

selected, and that some parameters (drain and source area and perimeter, etc) are

automatically calculated.

To connect the components, we use wires. Normally, it is done by clicking

the wire button on the bar on the left, then click on the first terminal followed by the

second terminal. To avoid confusion, labels can be created.

Some useful tools and shortcuts on the bar on the left is important for us to

create our design, such as “Check and Save” button which will check our design on

errors made, “Copy” button which will copy the selected item we wanted.

Figure 3.11: Composer Schematic Editor Window

21

After designing the schematic completely using the Schematic Editor, the

electrical parameters and functions of the circuit must be confirmed using a

Simulation tool. Using the simulation results, the designer usually modifies some of

the device properties (such as transistor width-to-length ratio) to optimize the

performance.

The initial simulation phase also serves to detect some of the design errors

that may have been created during the schematic entry step, such as a missing

connection or an unintended crossing of two signals in the schematic. Some of these

errors (e.g., floating nodes) can be detected even before simulation, by clicking the

“Check and Save” button in the schematic window.

Then, the second simulation phase will do the "extraction" of a mask layout

(post-layout simulation), to accurately assess the electrical performance of the

completed design. Like in other simulation software, it is the netlist text file that is

extracted from the schematic (or layout) what is actually simulated.

To start the simulation, click on “Tools” “Analog Environment”. By then,

a window will pop up showing the Virtuoso Analog Design Environment.

Figure 3.12: Simulation under Analog Environment

22

Figure 3.13: Simulation Window

Using the window, we need to select the analysis to be done. Among the

analyses available are transfer function analysis, DC analysis, AC analysis and other

suitable analyses. This is done by selecting the appropriate analysis through clicking

the “Choose analysis” button. Any variable set inside properties of components

inside schematic will be needed to list inside the “Design Variables” field. Since the

analog multiplier design needs VY as variable, parametric analysis is used to produce

linearity curve.

Figure 3.14: Choosing Analysis

23

After selecting the desired analyses, we click on “Run Simulation” to get the

netlist of the circuit inside the schematic. At the same time, analysis is being done to

get the correct electrical values on each component. If we need to plot graphs, we

will need to click on the “Results” on Virtuoso Analog Design Environment window.

Then, we select “Direct Plot” “Main Form”. With that, the graph that would like

to be viewed should be selected, such as DC curve or transfer curve.

Figure 3.15: Direct Plot

Once obtained the desired graph, the exact points on the graph can be known

by putting marker on the graph produced, through clicking the “Marker” tab

“Trace Marker” or tapping “t” key before clicking on the graph. To get the exact

position, we may need to double click the marker and change the X or Y properties.

24

Figure 3.16: Trace Marking on Graph Plotted

25

CHAPTER 4

RESULTS AND DISCUSSIONS

4.1 Introduction

The analog multiplier schematic design consists of two components, which

are the multiplying quad and the (Op-amp). The transistors M0 to M3 are the

multiplying quad which receives the inputs. The op-amp is to deduct the product

from the multiplying quad.

Figure 4.1: Overall Analog Multiplier Circuit Design

26

Figure 4.2: Overall Analog Multiplier Circuit Design in Cadence

4.2 Design of Op-amp

4.2.1 Simulation Model

For simulation purpose, the basic idea that op-amp is an electronic unit that

behaves like a voltage-controlled voltage source is adopted. As such, the op-amp is

as Figure 4.3.

27

Figure 4.3: Simulation Model for Op-amp Design

This op-amp can deliver amplification of 86.02dB, which is shown in Figure

4.4. Since this model doesn‟t include transistors, its amplification is not affected by

high frequencies.

28

Figure 4.4: Gain Response of Analog Multiplier Design

After saving this op-amp as a symbol, it is plugged into the analog multiplier

schematic circuit. The result is as follows:

29

Figure 4.5: Netlist produced

Figure 4.6: Graph of Analog Multiplier Produced by Simulation Model

30

Summary of the simulation design of the op-amp:

(1) Gain = 86.02 dB.

(2) Linearity = 100 %

4.2.2 Bias Model

After designing the simulation circuit, the bias circuit for the analog

multiplier design would be designed. Here, the op-amp is to be ensured to work

properly. Basically, the op-amp needs to subtract the voltage that results from the

multiplying quad and amplify the results. Initially, the design of fully-differential

folded-cascode op-amp is applied. After some considerations, a simpler op-amp

design that functions similarly as the fully-differential folded-cascode op-amp is

preferred, which is the basic differential amplifier and common source amplifier.

Figure 4.7: Basic Differential Amplifier

31

Figure 4.8: Common Source Amplifier

The current source could be replaced with nMOS where its bulk is connected

to its source.

Figure 4.9: nMOS as Current Source

32

Figure 4.10: Overall Differential Amplifier

Figure 4.11: Overall Differential Amplifier in Cadence

By using Cadence, transfer function test is run and the following transfer

curve is produced. This graph shows that this design can achieve gain at 31.63dB and

61.23 MHz. Well, this is enough to power up the analog multiplier design.

33

Figure 4.12: Transfer Curve Produced by Bias Model

34

4.3 Analog Multiplier

Using the bias model for the op-amp design, it is put into the analog

multiplier circuit. By implementing similar analysis, the following curve which can

show the linearity of the graph is obtained.

Figure 4.13: DC Response of Analog Multiplier Design

Besides that, the gain and the -3 dB bandwidth is -242.7mdB - -14.11dB and

425.4MHz – 461.4MHz respectively.

35

Figure 4.14: Gain and -3 dB Bandwidth of Analog Multiplier

Apart from that, the power dissipation produced by the analog multiplier is by

referring to the IDS for each branch of the input and VDD.

IDS

(A)

MOSFETs Y (V)

-1 -0.5 0 0.5 1

M0 31.53p 77.75n 516.8n 956.3n 7.398µ

M1 7.398µ 956.3n 516.8n 77.75n 31.53p

M2 7.398µ 956.3n 516.8n 77.75n 31.53p

M3 31.53p 77.75n 516.8n 956.3n 7.398µ

Total 12.796 µ 2.068 µ 2.0672 µ 2.068 µ 12.796 µ

Table 4.1: Total Currents from Each Branch of Analog Multiplier

|IDS

| (µA)

MOSFETs Y (V)

-1 -0.5 0 0.5 1

M11 108.2 99.63 99.63 99.63 108.20

M12 7.668 70.43 70.43 70.43 7.668

36

M4 108.2 99.63 99.63 99.63 108.20

M13 7.668 70.43 70.43 70.43 7.668

Total 231.736 340.12 340.12 340.12 231.736

Table 4.2: Total Currents from Each Branch of Differential Amplifier

Power is calculated through the following power equation.

𝑃 = 𝑉𝐷𝐷 ∗ 𝐼𝐷𝑆

Power (µW)

Components Y (V)

-1 -0.5 0 0.5 1

Multiplying

Quad, PM

11.5164 1.8612 1.8605 1.8612 11.5164

Op-amp, PO 417.1248 612.216 612.216 612.216 417.1248

Total 428.6412 614.0772 614.0765 614.0772 428.6412

Table 4.3: Total Power for the Analog Multiplier

Another property in analog multiplier design is linearity. It is being done by

taking 11 points on the graph. To make comparison between few papers referred to,

the range of the X-axis needs to be minimized as most of them are in this range.

Figure 4.15: Linearity of Analog Multiplier

37

Using scatter-plot method, 11 points were chosen from the graph.

Vx (mV) Vo+ - Vo- (V)

Y = -1 Y = -0.5 Y = 0 Y = 0.5 Y = 1

-250 M5 216.360u 99.571u 0.0 -99.571u -216.360u

-200 M4 171.370u 78.595u 0.0 -78.595u -171.370u

-150 M3 126.370u 57.618u 0.0 -57.618u -126.370u

-100 M2 83.795u 38.071u 0.0 -38.071u -83.795u

-50 M1 41.217u 18.524u 0.0 -18.524u -41.217u

0 M0 2.073n 47.700p 0.0 -47.700p -2.073n

50 M1

0 -41.213u -18.524u 0.0 18.524u 41.213u

100 M9 -83.795u -38.073u 0.0 38.073u 83.795u

150 M8 -126.380u -57.622u 0.0 57.622u 126.380u

200 M7 -171.370u -78.598u 0.0 78.598u 171.370u

250 M6 -216.360u -99.574u 0.0 99.574u 216.360u

Table 4.4: Voltages for the Analog Multiplier at Different Sweep Voltages

For Linearity, it must conform to the straight line equation, which is Y =

mX+C, which means the gradient is the same for each case.

For Y = -1V, assuming the gradient between the origin and the next point

after it is the gradient of the best-fit straight line. Hence

𝑑𝑦

𝑑𝑥(M1-M0) =

41.178𝜇𝑉

−49.947𝑚𝑉= −0.8 𝑥 10−3 (𝑡𝑜 1 𝑠. 𝑓. )

Referring to the gradient between point M1 AND M0, we shall approximate

the graph to be linear between the gradient of −0.75 𝑥 10−3 to −0.85 𝑥 10−3. Hence,

the linearity is between -161.37mV to 180.26mV. This means that the linearity is

79.02%. The linearity error is 20.98%.

For Y = -0.5V,

38

𝑑𝑦

𝑑𝑥(M1-M0) =

18.15𝜇𝑉

−49.947𝑚𝑉= −0.4 𝑥 10−3 (𝑡𝑜 1 𝑠. 𝑓. )

Referring to the gradient between point M1 AND M0, we shall approximate

the graph to be linear between the gradient of −0.35 𝑥 10−3 to −0.45 𝑥 10−3. Hence,

the linearity is between -250mV to 250mV. This means that the linearity is 100%.

The linearity error is 0%.

For Y = 0.5V and Y = 1V cases, it is the inverse of the cases for Y = -0.5V

and Y = -1V respectively.

For Y = 0V, there is no gradient produced as the line is parallel to x-axis

where it is X = 0.

Y (V)

-1 -0.5 0 0.5 1

Linearity

Error (%)

20.98 0 - 0 20.98

Table 4.5: Linearity Error for the Analog Multiplier

Besides that, some comparisons could be made to compare the designs with

papers and journals. Table 4.6 below are the few properties that is being compared.

Sources The Design [2] [3] [4]

Power

Dissipation

(W)

614.0772 µ 2.8 m 32 µ 34 µ

Linearity

Error (%) 20.98 0.89 3.2 Low *

-3 dB

Bandwidth

(Hz)

425.4M –

461.4M 2.2M 1.98G 110M

Gain (dB) -242.7m - -

14.11 - - -20 *

Table 4.6: Comparisons between Designs

* - The parameters are guessed from illustration.

39

Referring to the analog multiplier design from numerous sources, the analog

multiplier design can be considered average. From the point of power dissipation, the

analog multiplier design generates more power as the design is made up of

multiplying quad and differential amplifier. Looking at the calculations above,

certainly the differential amplifier used lots of power.

Apart from that, the linearity of the analog multiplier design is considered

above average as the linearity is above 60%. However, if compared to the papers, the

design is considered not appropriate, unless the VY is lower than 1V. This could be

due to the reason that the differential amplifier does not produce higher enough gain

to linearise the outputs.

Besides that, the -3 dB bandwidth of the analog multiplier is quite high

comparing to the different sources. This could be due to the reason that the

differential amplifier produces high bandwidth. Hence, the bandwidth cascades to the

analog multiplier design.

Finally, the gain produced by the analog multiplier design is in the range of -

242.7mdB - -14.11dB. It is considered acceptable as another sources produce -20dB

gain.

40

CHAPTER 5

CONCLUSION AND RECOMMENDATION

5.1 Conclusion

For this project, the schematic design of the following is settled:

An analog multiplier with 1.8V power supply that can produce:

◦ At least 2MHz bandwidth

◦ At most 3mW power dissipation

◦ Four-Quadrant

5.2 Problems

This project is aimed at familiarizing us with the modern tools used in

industry today. The experience to use Cadence is precious as it is being used widely

in industry. However, due to time constraints and limited resources, the complete

design with layout design is not done. Besides that, the design is considered above

average when compared to different sources.

Although the analog multiplier is functioning, it could be improved further as

it consumes some amount of power and produce below-par linearity. This is done

when comparing to the designs from numerous sources.

41

5.3 Recommendations

Regarding to the problems in this analog multiplier design, some parameters

can be improved further in future works, especially the power dissipation and

linearity property.

Commenting on the power dissipation, the analog multiplier design generates

more power as the design is made up of multiplying quad and differential amplifier.

Since the differential amplifier consumes large portion of the power, its power

dissipation could be lowered to minimize the power dissipation of the overall design.

Besides that, the linearity of the analog multiplier design, which is moderate,

could be improved. Unless the VY is lower than 1V, the design is considered not

appropriate. To produce greater gain that can help to linearise the design, other

alternatives for the architecture of the differential amplifier could be considered such

as the fully-differential folded-cascode op-amp.

42

REFERENCES

Baker, Li, Boyce 1997. CMOS: Circuit Design, Layout and Simulation. 2nd

ed. New York: John Wiley & Sons. 1997.

Charles Alexander, Matthew Sadiku et al. 2004. Fundamentals of Electric

Circuits 3rd ed. McGraw Hill 2004.

Shuo-Yuan Hsiao and Chung-Yu Wu. A 1.2V CMOS Four-Quadrant Analog

Multiplier. 1997 IEEE International Symposium on Circuits and Systems.

June 9-12, 1997. Hong Kong: IEEE. 1997. 241-244. [2]

Chunhong Chen and Zheng Li. A Low-Power CMOS Analog Multiplier.

IEEE Transactions on Circuits and Systems. 2006. 53(2): 100-104. [3]

Chutham Sawigun et. al. A Low-Voltage, Low-Power, High Linearity CMOS

Four-Quadrant Analog Multiplier. 2007. 751-754. [4]

Websites:

http://en.wikipedia.org/wiki/Analog_multiplier accessed on 2nd October

2009.

43

APPENDIX A

Linearity

44

45

APPENDIX B

Transistor parameters in Multiplying Quad of Analog Multiplier / Power Dissipation

M0

M1

46

M2

M3

47

APPENDIX C

Transistor parameters in Op-amp of Analog Multiplier / Power Dissipation