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Universal Verification Methodology (UVM) BenefitsMustafa KhairallahBoost Valley B
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Outline
Verification Needs UVM Benefits Example: I2S Conclusion
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Verification Needs
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Code ReuseTest Cases &
Scenarios Modification
Functional Coverage
Calculation
Generating & Managing Reports
Debugging Communication
Verification Needs - Development
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Code ReuseTest Cases &
Scenarios Modification
Functional Coverage
Calculation
Generating & Managing Reports
Debugging Communication
Verification Needs - Compilation
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Code ReuseTest Cases &
Scenarios Modification
Functional Coverage
Calculation
Generating & Managing Reports
Debugging Communication
Verification Needs - Runtime
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Code ReuseTest Cases &
Scenarios Modification
Functional Coverage
Calculation
Generating & Managing Reports
Debugging Communication
Verification Needs - Debugging
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Test Cases &Scenarios
Modification
Functional Coverage
Calculation
Generating & Managing Reports
Debugging Communication7
Verification Methodologies
Do the same things the same way: Ease of communication.
Test/Test-bench separation: Compile once, run many times.
Utilities: Functional coverage – reporting
mechanisms - … etc.
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UVM Benefits
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UVM Adoption
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Test/Test-bench separation
• Test Writer:• Selects sequences,• Configures the
environment(s)• Runs test.
Test
Test
Environment
Bus Agent
Active Agent
Passive Agent
Analysis Agent Register Model
Environment
Configurations
DUT
• UVC User: Integrates UVCs into environment to test different designs.
Env(Test-
bench)
• Developer: UVC Design
• Complication phase.UVCs B
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Test/Test-bench separation
Test Environment
Bus Agent
Active Agent
Passive Agent
Analysis Agent Register Model
Environment
Configurations
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Configurability
Controlled by the test writer.
Configurations can be: Structural configurations. Runtime configurations.
Provides topological flexibility: Components can be overridden, removed or
configured.
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Block 2’
TLM 2.0
UVM is compatible with the TLM 2.0 standard. Uses port/export communication. Hides communication details (pin level activities) Eases customization using configurations & overrides.
Block 1 Block 2 Boost
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Constrained Randomization
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Coverage Collector
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Checker (Reference Model)
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Checker (Assertions)
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Built-in reporting mechanisms.
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Built-in reporting mechanisms.
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Practical Example :I2S
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Introduction I2S stands for Inter-IC Sound, DUT is a slave I2S transceiver. It is around 2000 gates.
I2S Bus Purpose: Communicate PCM audio data between integrated circuits.
Characteristics Separates clock and serial data signals. Lower Jitter. Can recover clock from data stream.
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UVM Test-Bench Architecture
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Runtime Comparison
2 20 200 2000 20000 200000 20000000
5
10
15
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VHDL Test-BenchUVM Test-Bench
No. of test cases
> 10 Times
Reduction!!
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Time in minutes
VHDL UVM
Summary
Conventional Test-bench UVM Test-Bench
• Mainly simulation-based • Limited assertion-based
capabilities
• Simulation based• Advanced assertion-based
in System Verilog & UVM
Mostly directed testing Constrained random testing & directed testing
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Summary
Conventional Test-bench UVM Test-Bench
Can’t automatically guarantee full functional coverage Supports functional coverage
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Summary
Conventional Test-bench UVM Test-Bench
Strongly coupled with DUT Loosely coupled with DUT
Requires longer development time
Reusability reduces development time B
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Thank YouQuestions?
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